1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <usb.h> 12 #include "ehci.h" 13 #include <asm/arch/cpu.h> 14 15 #if defined(CONFIG_KIRKWOOD) 16 #include <asm/arch/soc.h> 17 #elif defined(CONFIG_ORION5X) 18 #include <asm/arch/orion5x.h> 19 #endif 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #define rdl(off) readl(MVUSB0_BASE + (off)) 24 #define wrl(off, val) writel((val), MVUSB0_BASE + (off)) 25 26 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) 27 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) 28 #define USB_TARGET_DRAM 0x0 29 30 /* 31 * USB 2.0 Bridge Address Decoding registers setup 32 */ 33 static void usb_brg_adrdec_setup(void) 34 { 35 int i; 36 u32 size, base, attrib; 37 38 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 39 40 /* Enable DRAM bank */ 41 switch (i) { 42 case 0: 43 attrib = MVUSB0_CPU_ATTR_DRAM_CS0; 44 break; 45 case 1: 46 attrib = MVUSB0_CPU_ATTR_DRAM_CS1; 47 break; 48 case 2: 49 attrib = MVUSB0_CPU_ATTR_DRAM_CS2; 50 break; 51 case 3: 52 attrib = MVUSB0_CPU_ATTR_DRAM_CS3; 53 break; 54 default: 55 /* invalide bank, disable access */ 56 attrib = 0; 57 break; 58 } 59 60 size = gd->bd->bi_dram[i].size; 61 base = gd->bd->bi_dram[i].start; 62 if ((size) && (attrib)) 63 wrl(USB_WINDOW_CTRL(i), 64 MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, 65 attrib, MVCPU_WIN_ENABLE)); 66 else 67 wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE); 68 69 wrl(USB_WINDOW_BASE(i), base); 70 } 71 } 72 73 /* 74 * Create the appropriate control structures to manage 75 * a new EHCI host controller. 76 */ 77 int ehci_hcd_init(int index, enum usb_init_type init, 78 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 79 { 80 usb_brg_adrdec_setup(); 81 82 *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100); 83 *hcor = (struct ehci_hcor *)((uint32_t) *hccr 84 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 85 86 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", 87 (uint32_t)*hccr, (uint32_t)*hcor, 88 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 89 90 return 0; 91 } 92 93 /* 94 * Destroy the appropriate control structures corresponding 95 * the the EHCI host controller. 96 */ 97 int ehci_hcd_stop(int index) 98 { 99 return 0; 100 } 101