1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <usb.h> 12 #include "ehci.h" 13 #include <linux/mbus.h> 14 #include <asm/arch/cpu.h> 15 #include <dm.h> 16 17 #if defined(CONFIG_KIRKWOOD) 18 #include <asm/arch/soc.h> 19 #elif defined(CONFIG_ORION5X) 20 #include <asm/arch/orion5x.h> 21 #endif 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) 26 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) 27 #define USB_TARGET_DRAM 0x0 28 29 /* 30 * USB 2.0 Bridge Address Decoding registers setup 31 */ 32 #ifdef CONFIG_DM_USB 33 34 struct ehci_mvebu_priv { 35 struct ehci_ctrl ehci; 36 fdt_addr_t hcd_base; 37 }; 38 39 /* 40 * Once all the older Marvell SoC's (Orion, Kirkwood) are converted 41 * to the common mvebu archticture including the mbus setup, this 42 * will be the only function needed to configure the access windows 43 */ 44 static void usb_brg_adrdec_setup(u32 base) 45 { 46 const struct mbus_dram_target_info *dram; 47 int i; 48 49 dram = mvebu_mbus_dram_info(); 50 51 for (i = 0; i < 4; i++) { 52 writel(0, base + USB_WINDOW_CTRL(i)); 53 writel(0, base + USB_WINDOW_BASE(i)); 54 } 55 56 for (i = 0; i < dram->num_cs; i++) { 57 const struct mbus_dram_window *cs = dram->cs + i; 58 59 /* Write size, attributes and target id to control register */ 60 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | 61 (dram->mbus_dram_target_id << 4) | 1, 62 base + USB_WINDOW_CTRL(i)); 63 64 /* Write base address to base register */ 65 writel(cs->base, base + USB_WINDOW_BASE(i)); 66 } 67 } 68 69 static int ehci_mvebu_probe(struct udevice *dev) 70 { 71 struct ehci_mvebu_priv *priv = dev_get_priv(dev); 72 struct ehci_hccr *hccr; 73 struct ehci_hcor *hcor; 74 75 /* 76 * Get the base address for EHCI controller from the device node 77 */ 78 priv->hcd_base = dev_get_addr(dev); 79 if (priv->hcd_base == FDT_ADDR_T_NONE) { 80 debug("Can't get the EHCI register base address\n"); 81 return -ENXIO; 82 } 83 84 usb_brg_adrdec_setup(priv->hcd_base); 85 86 hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100); 87 hcor = (struct ehci_hcor *) 88 ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 89 90 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", 91 (u32)hccr, (u32)hcor, 92 (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 93 94 return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); 95 } 96 97 static int ehci_mvebu_remove(struct udevice *dev) 98 { 99 int ret; 100 101 ret = ehci_deregister(dev); 102 if (ret) 103 return ret; 104 105 return 0; 106 } 107 108 static const struct udevice_id ehci_usb_ids[] = { 109 { .compatible = "marvell,orion-ehci", }, 110 { } 111 }; 112 113 U_BOOT_DRIVER(ehci_mvebu) = { 114 .name = "ehci_mvebu", 115 .id = UCLASS_USB, 116 .of_match = ehci_usb_ids, 117 .probe = ehci_mvebu_probe, 118 .remove = ehci_mvebu_remove, 119 .ops = &ehci_usb_ops, 120 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 121 .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv), 122 .flags = DM_FLAG_ALLOC_PRIV_DMA, 123 }; 124 125 #else 126 #define MVUSB_BASE(port) MVUSB0_BASE 127 128 static void usb_brg_adrdec_setup(int index) 129 { 130 int i; 131 u32 size, base, attrib; 132 133 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 134 135 /* Enable DRAM bank */ 136 switch (i) { 137 case 0: 138 attrib = MVUSB0_CPU_ATTR_DRAM_CS0; 139 break; 140 case 1: 141 attrib = MVUSB0_CPU_ATTR_DRAM_CS1; 142 break; 143 case 2: 144 attrib = MVUSB0_CPU_ATTR_DRAM_CS2; 145 break; 146 case 3: 147 attrib = MVUSB0_CPU_ATTR_DRAM_CS3; 148 break; 149 default: 150 /* invalide bank, disable access */ 151 attrib = 0; 152 break; 153 } 154 155 size = gd->bd->bi_dram[i].size; 156 base = gd->bd->bi_dram[i].start; 157 if ((size) && (attrib)) 158 writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, 159 attrib, MVCPU_WIN_ENABLE), 160 MVUSB0_BASE + USB_WINDOW_CTRL(i)); 161 else 162 writel(MVCPU_WIN_DISABLE, 163 MVUSB0_BASE + USB_WINDOW_CTRL(i)); 164 165 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i)); 166 } 167 } 168 169 /* 170 * Create the appropriate control structures to manage 171 * a new EHCI host controller. 172 */ 173 int ehci_hcd_init(int index, enum usb_init_type init, 174 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 175 { 176 usb_brg_adrdec_setup(index); 177 178 *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100); 179 *hcor = (struct ehci_hcor *)((uint32_t) *hccr 180 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 181 182 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", 183 (uint32_t)*hccr, (uint32_t)*hcor, 184 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 185 186 return 0; 187 } 188 189 /* 190 * Destroy the appropriate control structures corresponding 191 * the the EHCI host controller. 192 */ 193 int ehci_hcd_stop(int index) 194 { 195 return 0; 196 } 197 198 #endif /* CONFIG_DM_USB */ 199