1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <usb.h> 28 #include "ehci.h" 29 #include "ehci-core.h" 30 #include <asm/arch/cpu.h> 31 32 #if defined(CONFIG_KIRKWOOD) 33 #include <asm/arch/kirkwood.h> 34 #elif defined(CONFIG_ORION5X) 35 #include <asm/arch/orion5x.h> 36 #endif 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 #define rdl(off) readl(MVUSB0_BASE + (off)) 41 #define wrl(off, val) writel((val), MVUSB0_BASE + (off)) 42 43 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) 44 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) 45 #define USB_TARGET_DRAM 0x0 46 47 /* 48 * USB 2.0 Bridge Address Decoding registers setup 49 */ 50 static void usb_brg_adrdec_setup(void) 51 { 52 int i; 53 u32 size, base, attrib; 54 55 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 56 57 /* Enable DRAM bank */ 58 switch (i) { 59 case 0: 60 attrib = MVUSB0_CPU_ATTR_DRAM_CS0; 61 break; 62 case 1: 63 attrib = MVUSB0_CPU_ATTR_DRAM_CS1; 64 break; 65 case 2: 66 attrib = MVUSB0_CPU_ATTR_DRAM_CS2; 67 break; 68 case 3: 69 attrib = MVUSB0_CPU_ATTR_DRAM_CS3; 70 break; 71 default: 72 /* invalide bank, disable access */ 73 attrib = 0; 74 break; 75 } 76 77 size = gd->bd->bi_dram[i].size; 78 base = gd->bd->bi_dram[i].start; 79 if ((size) && (attrib)) 80 wrl(USB_WINDOW_CTRL(i), 81 MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, 82 attrib, MVCPU_WIN_ENABLE)); 83 else 84 wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE); 85 86 wrl(USB_WINDOW_BASE(i), base); 87 } 88 } 89 90 /* 91 * Create the appropriate control structures to manage 92 * a new EHCI host controller. 93 */ 94 int ehci_hcd_init(void) 95 { 96 usb_brg_adrdec_setup(); 97 98 hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100); 99 hcor = (struct ehci_hcor *)((uint32_t) hccr 100 + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 101 102 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", 103 (uint32_t)hccr, (uint32_t)hcor, 104 (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 105 106 return 0; 107 } 108 109 /* 110 * Destroy the appropriate control structures corresponding 111 * the the EHCI host controller. 112 */ 113 int ehci_hcd_stop(void) 114 { 115 return 0; 116 } 117