1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <asm/byteorder.h> 25 #include <usb.h> 26 #include <asm/io.h> 27 #include <malloc.h> 28 #include <watchdog.h> 29 30 #include "ehci.h" 31 32 int rootdev; 33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ 34 volatile struct ehci_hcor *hcor; 35 36 static uint16_t portreset; 37 static struct QH qh_list __attribute__((aligned(32))); 38 39 static struct descriptor { 40 struct usb_hub_descriptor hub; 41 struct usb_device_descriptor device; 42 struct usb_linux_config_descriptor config; 43 struct usb_linux_interface_descriptor interface; 44 struct usb_endpoint_descriptor endpoint; 45 } __attribute__ ((packed)) descriptor = { 46 { 47 0x8, /* bDescLength */ 48 0x29, /* bDescriptorType: hub descriptor */ 49 2, /* bNrPorts -- runtime modified */ 50 0, /* wHubCharacteristics */ 51 0xff, /* bPwrOn2PwrGood */ 52 0, /* bHubCntrCurrent */ 53 {}, /* Device removable */ 54 {} /* at most 7 ports! XXX */ 55 }, 56 { 57 0x12, /* bLength */ 58 1, /* bDescriptorType: UDESC_DEVICE */ 59 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 60 9, /* bDeviceClass: UDCLASS_HUB */ 61 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 62 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 63 64, /* bMaxPacketSize: 64 bytes */ 64 0x0000, /* idVendor */ 65 0x0000, /* idProduct */ 66 cpu_to_le16(0x0100), /* bcdDevice */ 67 1, /* iManufacturer */ 68 2, /* iProduct */ 69 0, /* iSerialNumber */ 70 1 /* bNumConfigurations: 1 */ 71 }, 72 { 73 0x9, 74 2, /* bDescriptorType: UDESC_CONFIG */ 75 cpu_to_le16(0x19), 76 1, /* bNumInterface */ 77 1, /* bConfigurationValue */ 78 0, /* iConfiguration */ 79 0x40, /* bmAttributes: UC_SELF_POWER */ 80 0 /* bMaxPower */ 81 }, 82 { 83 0x9, /* bLength */ 84 4, /* bDescriptorType: UDESC_INTERFACE */ 85 0, /* bInterfaceNumber */ 86 0, /* bAlternateSetting */ 87 1, /* bNumEndpoints */ 88 9, /* bInterfaceClass: UICLASS_HUB */ 89 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 90 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 91 0 /* iInterface */ 92 }, 93 { 94 0x7, /* bLength */ 95 5, /* bDescriptorType: UDESC_ENDPOINT */ 96 0x81, /* bEndpointAddress: 97 * UE_DIR_IN | EHCI_INTR_ENDPT 98 */ 99 3, /* bmAttributes: UE_INTERRUPT */ 100 8, /* wMaxPacketSize */ 101 255 /* bInterval */ 102 }, 103 }; 104 105 #if defined(CONFIG_EHCI_IS_TDI) 106 #define ehci_is_TDI() (1) 107 #else 108 #define ehci_is_TDI() (0) 109 #endif 110 111 #if defined(CONFIG_EHCI_DCACHE) 112 /* 113 * Routines to handle (flush/invalidate) the dcache for the QH and qTD 114 * structures and data buffers. This is needed on platforms using this 115 * EHCI support with dcache enabled. 116 */ 117 static void flush_invalidate(u32 addr, int size, int flush) 118 { 119 if (flush) 120 flush_dcache_range(addr, addr + size); 121 else 122 invalidate_dcache_range(addr, addr + size); 123 } 124 125 static void cache_qtd(struct qTD *qtd, int flush) 126 { 127 u32 *ptr = (u32 *)qtd->qt_buffer[0]; 128 int len = (qtd->qt_token & 0x7fff0000) >> 16; 129 130 flush_invalidate((u32)qtd, sizeof(struct qTD), flush); 131 if (ptr && len) 132 flush_invalidate((u32)ptr, len, flush); 133 } 134 135 136 static inline struct QH *qh_addr(struct QH *qh) 137 { 138 return (struct QH *)((u32)qh & 0xffffffe0); 139 } 140 141 static void cache_qh(struct QH *qh, int flush) 142 { 143 struct qTD *qtd; 144 struct qTD *next; 145 static struct qTD *first_qtd; 146 147 /* 148 * Walk the QH list and flush/invalidate all entries 149 */ 150 while (1) { 151 flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush); 152 if ((u32)qh & QH_LINK_TYPE_QH) 153 break; 154 qh = qh_addr(qh); 155 qh = (struct QH *)qh->qh_link; 156 } 157 qh = qh_addr(qh); 158 159 /* 160 * Save first qTD pointer, needed for invalidating pass on this QH 161 */ 162 if (flush) 163 first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay & 164 0xffffffe0); 165 else 166 qtd = first_qtd; 167 168 /* 169 * Walk the qTD list and flush/invalidate all entries 170 */ 171 while (1) { 172 if (qtd == NULL) 173 break; 174 cache_qtd(qtd, flush); 175 next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0); 176 if (next == qtd) 177 break; 178 qtd = next; 179 } 180 } 181 182 static inline void ehci_flush_dcache(struct QH *qh) 183 { 184 cache_qh(qh, 1); 185 } 186 187 static inline void ehci_invalidate_dcache(struct QH *qh) 188 { 189 cache_qh(qh, 0); 190 } 191 #else /* CONFIG_EHCI_DCACHE */ 192 /* 193 * 194 */ 195 static inline void ehci_flush_dcache(struct QH *qh) 196 { 197 } 198 199 static inline void ehci_invalidate_dcache(struct QH *qh) 200 { 201 } 202 #endif /* CONFIG_EHCI_DCACHE */ 203 204 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 205 { 206 uint32_t result; 207 do { 208 result = ehci_readl(ptr); 209 udelay(5); 210 if (result == ~(uint32_t)0) 211 return -1; 212 result &= mask; 213 if (result == done) 214 return 0; 215 usec--; 216 } while (usec > 0); 217 return -1; 218 } 219 220 static void ehci_free(void *p, size_t sz) 221 { 222 223 } 224 225 static int ehci_reset(void) 226 { 227 uint32_t cmd; 228 uint32_t tmp; 229 uint32_t *reg_ptr; 230 int ret = 0; 231 232 cmd = ehci_readl(&hcor->or_usbcmd); 233 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 234 ehci_writel(&hcor->or_usbcmd, cmd); 235 ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000); 236 if (ret < 0) { 237 printf("EHCI fail to reset\n"); 238 goto out; 239 } 240 241 if (ehci_is_TDI()) { 242 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE); 243 tmp = ehci_readl(reg_ptr); 244 tmp |= USBMODE_CM_HC; 245 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 246 tmp |= USBMODE_BE; 247 #endif 248 ehci_writel(reg_ptr, tmp); 249 } 250 out: 251 return ret; 252 } 253 254 static void *ehci_alloc(size_t sz, size_t align) 255 { 256 static struct QH qh __attribute__((aligned(32))); 257 static struct qTD td[3] __attribute__((aligned (32))); 258 static int ntds; 259 void *p; 260 261 switch (sz) { 262 case sizeof(struct QH): 263 p = &qh; 264 ntds = 0; 265 break; 266 case sizeof(struct qTD): 267 if (ntds == 3) { 268 debug("out of TDs\n"); 269 return NULL; 270 } 271 p = &td[ntds]; 272 ntds++; 273 break; 274 default: 275 debug("unknown allocation size\n"); 276 return NULL; 277 } 278 279 memset(p, 0, sz); 280 return p; 281 } 282 283 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 284 { 285 uint32_t addr, delta, next; 286 int idx; 287 288 addr = (uint32_t) buf; 289 idx = 0; 290 while (idx < 5) { 291 td->qt_buffer[idx] = cpu_to_hc32(addr); 292 td->qt_buffer_hi[idx] = 0; 293 next = (addr + 4096) & ~4095; 294 delta = next - addr; 295 if (delta >= sz) 296 break; 297 sz -= delta; 298 addr = next; 299 idx++; 300 } 301 302 if (idx == 5) { 303 debug("out of buffer pointers (%u bytes left)\n", sz); 304 return -1; 305 } 306 307 return 0; 308 } 309 310 static int 311 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 312 int length, struct devrequest *req) 313 { 314 struct QH *qh; 315 struct qTD *td; 316 volatile struct qTD *vtd; 317 unsigned long ts; 318 uint32_t *tdp; 319 uint32_t endpt, token, usbsts; 320 uint32_t c, toggle; 321 uint32_t cmd; 322 int ret = 0; 323 324 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 325 buffer, length, req); 326 if (req != NULL) 327 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 328 req->request, req->request, 329 req->requesttype, req->requesttype, 330 le16_to_cpu(req->value), le16_to_cpu(req->value), 331 le16_to_cpu(req->index)); 332 333 qh = ehci_alloc(sizeof(struct QH), 32); 334 if (qh == NULL) { 335 debug("unable to allocate QH\n"); 336 return -1; 337 } 338 qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 339 c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && 340 usb_pipeendpoint(pipe) == 0) ? 1 : 0; 341 endpt = (8 << 28) | 342 (c << 27) | 343 (usb_maxpacket(dev, pipe) << 16) | 344 (0 << 15) | 345 (1 << 14) | 346 (usb_pipespeed(pipe) << 12) | 347 (usb_pipeendpoint(pipe) << 8) | 348 (0 << 7) | (usb_pipedevice(pipe) << 0); 349 qh->qh_endpt1 = cpu_to_hc32(endpt); 350 endpt = (1 << 30) | 351 (dev->portnr << 23) | 352 (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); 353 qh->qh_endpt2 = cpu_to_hc32(endpt); 354 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 355 356 td = NULL; 357 tdp = &qh->qh_overlay.qt_next; 358 359 toggle = 360 usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 361 362 if (req != NULL) { 363 td = ehci_alloc(sizeof(struct qTD), 32); 364 if (td == NULL) { 365 debug("unable to allocate SETUP td\n"); 366 goto fail; 367 } 368 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 369 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 370 token = (0 << 31) | 371 (sizeof(*req) << 16) | 372 (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); 373 td->qt_token = cpu_to_hc32(token); 374 if (ehci_td_buffer(td, req, sizeof(*req)) != 0) { 375 debug("unable construct SETUP td\n"); 376 ehci_free(td, sizeof(*td)); 377 goto fail; 378 } 379 *tdp = cpu_to_hc32((uint32_t) td); 380 tdp = &td->qt_next; 381 toggle = 1; 382 } 383 384 if (length > 0 || req == NULL) { 385 td = ehci_alloc(sizeof(struct qTD), 32); 386 if (td == NULL) { 387 debug("unable to allocate DATA td\n"); 388 goto fail; 389 } 390 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 391 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 392 token = (toggle << 31) | 393 (length << 16) | 394 ((req == NULL ? 1 : 0) << 15) | 395 (0 << 12) | 396 (3 << 10) | 397 ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); 398 td->qt_token = cpu_to_hc32(token); 399 if (ehci_td_buffer(td, buffer, length) != 0) { 400 debug("unable construct DATA td\n"); 401 ehci_free(td, sizeof(*td)); 402 goto fail; 403 } 404 *tdp = cpu_to_hc32((uint32_t) td); 405 tdp = &td->qt_next; 406 } 407 408 if (req != NULL) { 409 td = ehci_alloc(sizeof(struct qTD), 32); 410 if (td == NULL) { 411 debug("unable to allocate ACK td\n"); 412 goto fail; 413 } 414 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 415 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 416 token = (toggle << 31) | 417 (0 << 16) | 418 (1 << 15) | 419 (0 << 12) | 420 (3 << 10) | 421 ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); 422 td->qt_token = cpu_to_hc32(token); 423 *tdp = cpu_to_hc32((uint32_t) td); 424 tdp = &td->qt_next; 425 } 426 427 qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH); 428 429 /* Flush dcache */ 430 ehci_flush_dcache(&qh_list); 431 432 usbsts = ehci_readl(&hcor->or_usbsts); 433 ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); 434 435 /* Enable async. schedule. */ 436 cmd = ehci_readl(&hcor->or_usbcmd); 437 cmd |= CMD_ASE; 438 ehci_writel(&hcor->or_usbcmd, cmd); 439 440 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS, 441 100 * 1000); 442 if (ret < 0) { 443 printf("EHCI fail timeout STD_ASS set\n"); 444 goto fail; 445 } 446 447 /* Wait for TDs to be processed. */ 448 ts = get_timer(0); 449 vtd = td; 450 do { 451 /* Invalidate dcache */ 452 ehci_invalidate_dcache(&qh_list); 453 token = hc32_to_cpu(vtd->qt_token); 454 if (!(token & 0x80)) 455 break; 456 WATCHDOG_RESET(); 457 } while (get_timer(ts) < CONFIG_SYS_HZ); 458 459 /* Disable async schedule. */ 460 cmd = ehci_readl(&hcor->or_usbcmd); 461 cmd &= ~CMD_ASE; 462 ehci_writel(&hcor->or_usbcmd, cmd); 463 464 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0, 465 100 * 1000); 466 if (ret < 0) { 467 printf("EHCI fail timeout STD_ASS reset\n"); 468 goto fail; 469 } 470 471 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 472 473 token = hc32_to_cpu(qh->qh_overlay.qt_token); 474 if (!(token & 0x80)) { 475 debug("TOKEN=%#x\n", token); 476 switch (token & 0xfc) { 477 case 0: 478 toggle = token >> 31; 479 usb_settoggle(dev, usb_pipeendpoint(pipe), 480 usb_pipeout(pipe), toggle); 481 dev->status = 0; 482 break; 483 case 0x40: 484 dev->status = USB_ST_STALLED; 485 break; 486 case 0xa0: 487 case 0x20: 488 dev->status = USB_ST_BUF_ERR; 489 break; 490 case 0x50: 491 case 0x10: 492 dev->status = USB_ST_BABBLE_DET; 493 break; 494 default: 495 dev->status = USB_ST_CRC_ERR; 496 if ((token & 0x40) == 0x40) 497 dev->status |= USB_ST_STALLED; 498 break; 499 } 500 dev->act_len = length - ((token >> 16) & 0x7fff); 501 } else { 502 dev->act_len = 0; 503 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 504 dev->devnum, ehci_readl(&hcor->or_usbsts), 505 ehci_readl(&hcor->or_portsc[0]), 506 ehci_readl(&hcor->or_portsc[1])); 507 } 508 509 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 510 511 fail: 512 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 513 while (td != (void *)QT_NEXT_TERMINATE) { 514 qh->qh_overlay.qt_next = td->qt_next; 515 ehci_free(td, sizeof(*td)); 516 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 517 } 518 ehci_free(qh, sizeof(*qh)); 519 return -1; 520 } 521 522 static inline int min3(int a, int b, int c) 523 { 524 525 if (b < a) 526 a = b; 527 if (c < a) 528 a = c; 529 return a; 530 } 531 532 int 533 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, 534 int length, struct devrequest *req) 535 { 536 uint8_t tmpbuf[4]; 537 u16 typeReq; 538 void *srcptr = NULL; 539 int len, srclen; 540 uint32_t reg; 541 uint32_t *status_reg; 542 543 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 544 printf("The request port(%d) is not configured\n", 545 le16_to_cpu(req->index) - 1); 546 return -1; 547 } 548 status_reg = (uint32_t *)&hcor->or_portsc[ 549 le16_to_cpu(req->index) - 1]; 550 srclen = 0; 551 552 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 553 req->request, req->request, 554 req->requesttype, req->requesttype, 555 le16_to_cpu(req->value), le16_to_cpu(req->index)); 556 557 typeReq = req->request | req->requesttype << 8; 558 559 switch (typeReq) { 560 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 561 switch (le16_to_cpu(req->value) >> 8) { 562 case USB_DT_DEVICE: 563 debug("USB_DT_DEVICE request\n"); 564 srcptr = &descriptor.device; 565 srclen = 0x12; 566 break; 567 case USB_DT_CONFIG: 568 debug("USB_DT_CONFIG config\n"); 569 srcptr = &descriptor.config; 570 srclen = 0x19; 571 break; 572 case USB_DT_STRING: 573 debug("USB_DT_STRING config\n"); 574 switch (le16_to_cpu(req->value) & 0xff) { 575 case 0: /* Language */ 576 srcptr = "\4\3\1\0"; 577 srclen = 4; 578 break; 579 case 1: /* Vendor */ 580 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 581 srclen = 14; 582 break; 583 case 2: /* Product */ 584 srcptr = "\52\3E\0H\0C\0I\0 " 585 "\0H\0o\0s\0t\0 " 586 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 587 srclen = 42; 588 break; 589 default: 590 debug("unknown value DT_STRING %x\n", 591 le16_to_cpu(req->value)); 592 goto unknown; 593 } 594 break; 595 default: 596 debug("unknown value %x\n", le16_to_cpu(req->value)); 597 goto unknown; 598 } 599 break; 600 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 601 switch (le16_to_cpu(req->value) >> 8) { 602 case USB_DT_HUB: 603 debug("USB_DT_HUB config\n"); 604 srcptr = &descriptor.hub; 605 srclen = 0x8; 606 break; 607 default: 608 debug("unknown value %x\n", le16_to_cpu(req->value)); 609 goto unknown; 610 } 611 break; 612 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 613 debug("USB_REQ_SET_ADDRESS\n"); 614 rootdev = le16_to_cpu(req->value); 615 break; 616 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 617 debug("USB_REQ_SET_CONFIGURATION\n"); 618 /* Nothing to do */ 619 break; 620 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 621 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 622 tmpbuf[1] = 0; 623 srcptr = tmpbuf; 624 srclen = 2; 625 break; 626 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 627 memset(tmpbuf, 0, 4); 628 reg = ehci_readl(status_reg); 629 if (reg & EHCI_PS_CS) 630 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 631 if (reg & EHCI_PS_PE) 632 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 633 if (reg & EHCI_PS_SUSP) 634 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 635 if (reg & EHCI_PS_OCA) 636 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 637 if (reg & EHCI_PS_PR) 638 tmpbuf[0] |= USB_PORT_STAT_RESET; 639 if (reg & EHCI_PS_PP) 640 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 641 642 if (ehci_is_TDI()) { 643 switch ((reg >> 26) & 3) { 644 case 0: 645 break; 646 case 1: 647 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 648 break; 649 case 2: 650 default: 651 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 652 break; 653 } 654 } else { 655 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 656 } 657 658 if (reg & EHCI_PS_CSC) 659 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 660 if (reg & EHCI_PS_PEC) 661 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 662 if (reg & EHCI_PS_OCC) 663 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 664 if (portreset & (1 << le16_to_cpu(req->index))) 665 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 666 667 srcptr = tmpbuf; 668 srclen = 4; 669 break; 670 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 671 reg = ehci_readl(status_reg); 672 reg &= ~EHCI_PS_CLEAR; 673 switch (le16_to_cpu(req->value)) { 674 case USB_PORT_FEAT_ENABLE: 675 reg |= EHCI_PS_PE; 676 ehci_writel(status_reg, reg); 677 break; 678 case USB_PORT_FEAT_POWER: 679 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) { 680 reg |= EHCI_PS_PP; 681 ehci_writel(status_reg, reg); 682 } 683 break; 684 case USB_PORT_FEAT_RESET: 685 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 686 !ehci_is_TDI() && 687 EHCI_PS_IS_LOWSPEED(reg)) { 688 /* Low speed device, give up ownership. */ 689 debug("port %d low speed --> companion\n", 690 req->index - 1); 691 reg |= EHCI_PS_PO; 692 ehci_writel(status_reg, reg); 693 break; 694 } else { 695 int ret; 696 697 reg |= EHCI_PS_PR; 698 reg &= ~EHCI_PS_PE; 699 ehci_writel(status_reg, reg); 700 /* 701 * caller must wait, then call GetPortStatus 702 * usb 2.0 specification say 50 ms resets on 703 * root 704 */ 705 wait_ms(50); 706 /* terminate the reset */ 707 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 708 /* 709 * A host controller must terminate the reset 710 * and stabilize the state of the port within 711 * 2 milliseconds 712 */ 713 ret = handshake(status_reg, EHCI_PS_PR, 0, 714 2 * 1000); 715 if (!ret) 716 portreset |= 717 1 << le16_to_cpu(req->index); 718 else 719 printf("port(%d) reset error\n", 720 le16_to_cpu(req->index) - 1); 721 } 722 break; 723 default: 724 debug("unknown feature %x\n", le16_to_cpu(req->value)); 725 goto unknown; 726 } 727 /* unblock posted writes */ 728 (void) ehci_readl(&hcor->or_usbcmd); 729 break; 730 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 731 reg = ehci_readl(status_reg); 732 switch (le16_to_cpu(req->value)) { 733 case USB_PORT_FEAT_ENABLE: 734 reg &= ~EHCI_PS_PE; 735 break; 736 case USB_PORT_FEAT_C_ENABLE: 737 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE; 738 break; 739 case USB_PORT_FEAT_POWER: 740 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) 741 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP); 742 case USB_PORT_FEAT_C_CONNECTION: 743 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC; 744 break; 745 case USB_PORT_FEAT_OVER_CURRENT: 746 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; 747 break; 748 case USB_PORT_FEAT_C_RESET: 749 portreset &= ~(1 << le16_to_cpu(req->index)); 750 break; 751 default: 752 debug("unknown feature %x\n", le16_to_cpu(req->value)); 753 goto unknown; 754 } 755 ehci_writel(status_reg, reg); 756 /* unblock posted write */ 757 (void) ehci_readl(&hcor->or_usbcmd); 758 break; 759 default: 760 debug("Unknown request\n"); 761 goto unknown; 762 } 763 764 wait_ms(1); 765 len = min3(srclen, le16_to_cpu(req->length), length); 766 if (srcptr != NULL && len > 0) 767 memcpy(buffer, srcptr, len); 768 else 769 debug("Len is 0\n"); 770 771 dev->act_len = len; 772 dev->status = 0; 773 return 0; 774 775 unknown: 776 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 777 req->requesttype, req->request, le16_to_cpu(req->value), 778 le16_to_cpu(req->index), le16_to_cpu(req->length)); 779 780 dev->act_len = 0; 781 dev->status = USB_ST_STALLED; 782 return -1; 783 } 784 785 int usb_lowlevel_stop(void) 786 { 787 return ehci_hcd_stop(); 788 } 789 790 int usb_lowlevel_init(void) 791 { 792 uint32_t reg; 793 uint32_t cmd; 794 795 if (ehci_hcd_init() != 0) 796 return -1; 797 798 /* EHCI spec section 4.1 */ 799 if (ehci_reset() != 0) 800 return -1; 801 802 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 803 if (ehci_hcd_init() != 0) 804 return -1; 805 #endif 806 807 /* Set head of reclaim list */ 808 memset(&qh_list, 0, sizeof(qh_list)); 809 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 810 qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); 811 qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); 812 qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 813 qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 814 qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40); 815 816 /* Set async. queue head pointer. */ 817 ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list); 818 819 reg = ehci_readl(&hccr->cr_hcsparams); 820 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 821 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 822 /* Port Indicators */ 823 if (HCS_INDICATOR(reg)) 824 descriptor.hub.wHubCharacteristics |= 0x80; 825 /* Port Power Control */ 826 if (HCS_PPC(reg)) 827 descriptor.hub.wHubCharacteristics |= 0x01; 828 829 /* Start the host controller. */ 830 cmd = ehci_readl(&hcor->or_usbcmd); 831 /* 832 * Philips, Intel, and maybe others need CMD_RUN before the 833 * root hub will detect new devices (why?); NEC doesn't 834 */ 835 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 836 cmd |= CMD_RUN; 837 ehci_writel(&hcor->or_usbcmd, cmd); 838 839 /* take control over the ports */ 840 cmd = ehci_readl(&hcor->or_configflag); 841 cmd |= FLAG_CF; 842 ehci_writel(&hcor->or_configflag, cmd); 843 /* unblock posted write */ 844 cmd = ehci_readl(&hcor->or_usbcmd); 845 wait_ms(5); 846 reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); 847 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 848 849 rootdev = 0; 850 851 return 0; 852 } 853 854 int 855 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 856 int length) 857 { 858 859 if (usb_pipetype(pipe) != PIPE_BULK) { 860 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 861 return -1; 862 } 863 return ehci_submit_async(dev, pipe, buffer, length, NULL); 864 } 865 866 int 867 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 868 int length, struct devrequest *setup) 869 { 870 871 if (usb_pipetype(pipe) != PIPE_CONTROL) { 872 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 873 return -1; 874 } 875 876 if (usb_pipedevice(pipe) == rootdev) { 877 if (rootdev == 0) 878 dev->speed = USB_SPEED_HIGH; 879 return ehci_submit_root(dev, pipe, buffer, length, setup); 880 } 881 return ehci_submit_async(dev, pipe, buffer, length, setup); 882 } 883 884 int 885 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 886 int length, int interval) 887 { 888 889 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 890 dev, pipe, buffer, length, interval); 891 return -1; 892 } 893