1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <asm/byteorder.h> 25 #include <usb.h> 26 #include <asm/io.h> 27 #include <malloc.h> 28 #include <watchdog.h> 29 30 #include "ehci.h" 31 32 int rootdev; 33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ 34 volatile struct ehci_hcor *hcor; 35 36 static uint16_t portreset; 37 static struct QH qh_list __attribute__((aligned(32))); 38 39 static struct descriptor { 40 struct usb_hub_descriptor hub; 41 struct usb_device_descriptor device; 42 struct usb_linux_config_descriptor config; 43 struct usb_linux_interface_descriptor interface; 44 struct usb_endpoint_descriptor endpoint; 45 } __attribute__ ((packed)) descriptor = { 46 { 47 0x8, /* bDescLength */ 48 0x29, /* bDescriptorType: hub descriptor */ 49 2, /* bNrPorts -- runtime modified */ 50 0, /* wHubCharacteristics */ 51 10, /* bPwrOn2PwrGood */ 52 0, /* bHubCntrCurrent */ 53 {}, /* Device removable */ 54 {} /* at most 7 ports! XXX */ 55 }, 56 { 57 0x12, /* bLength */ 58 1, /* bDescriptorType: UDESC_DEVICE */ 59 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 60 9, /* bDeviceClass: UDCLASS_HUB */ 61 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 62 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 63 64, /* bMaxPacketSize: 64 bytes */ 64 0x0000, /* idVendor */ 65 0x0000, /* idProduct */ 66 cpu_to_le16(0x0100), /* bcdDevice */ 67 1, /* iManufacturer */ 68 2, /* iProduct */ 69 0, /* iSerialNumber */ 70 1 /* bNumConfigurations: 1 */ 71 }, 72 { 73 0x9, 74 2, /* bDescriptorType: UDESC_CONFIG */ 75 cpu_to_le16(0x19), 76 1, /* bNumInterface */ 77 1, /* bConfigurationValue */ 78 0, /* iConfiguration */ 79 0x40, /* bmAttributes: UC_SELF_POWER */ 80 0 /* bMaxPower */ 81 }, 82 { 83 0x9, /* bLength */ 84 4, /* bDescriptorType: UDESC_INTERFACE */ 85 0, /* bInterfaceNumber */ 86 0, /* bAlternateSetting */ 87 1, /* bNumEndpoints */ 88 9, /* bInterfaceClass: UICLASS_HUB */ 89 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 90 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 91 0 /* iInterface */ 92 }, 93 { 94 0x7, /* bLength */ 95 5, /* bDescriptorType: UDESC_ENDPOINT */ 96 0x81, /* bEndpointAddress: 97 * UE_DIR_IN | EHCI_INTR_ENDPT 98 */ 99 3, /* bmAttributes: UE_INTERRUPT */ 100 8, /* wMaxPacketSize */ 101 255 /* bInterval */ 102 }, 103 }; 104 105 #if defined(CONFIG_EHCI_IS_TDI) 106 #define ehci_is_TDI() (1) 107 #else 108 #define ehci_is_TDI() (0) 109 #endif 110 111 #if defined(CONFIG_EHCI_DCACHE) 112 /* 113 * Routines to handle (flush/invalidate) the dcache for the QH and qTD 114 * structures and data buffers. This is needed on platforms using this 115 * EHCI support with dcache enabled. 116 */ 117 static void flush_invalidate(u32 addr, int size, int flush) 118 { 119 if (flush) 120 flush_dcache_range(addr, addr + size); 121 else 122 invalidate_dcache_range(addr, addr + size); 123 } 124 125 static void cache_qtd(struct qTD *qtd, int flush) 126 { 127 u32 *ptr = (u32 *)qtd->qt_buffer[0]; 128 int len = (qtd->qt_token & 0x7fff0000) >> 16; 129 130 flush_invalidate((u32)qtd, sizeof(struct qTD), flush); 131 if (ptr && len) 132 flush_invalidate((u32)ptr, len, flush); 133 } 134 135 136 static inline struct QH *qh_addr(struct QH *qh) 137 { 138 return (struct QH *)((u32)qh & 0xffffffe0); 139 } 140 141 static void cache_qh(struct QH *qh, int flush) 142 { 143 struct qTD *qtd; 144 struct qTD *next; 145 static struct qTD *first_qtd; 146 147 /* 148 * Walk the QH list and flush/invalidate all entries 149 */ 150 while (1) { 151 flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush); 152 if ((u32)qh & QH_LINK_TYPE_QH) 153 break; 154 qh = qh_addr(qh); 155 qh = (struct QH *)qh->qh_link; 156 } 157 qh = qh_addr(qh); 158 159 /* 160 * Save first qTD pointer, needed for invalidating pass on this QH 161 */ 162 if (flush) 163 first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay & 164 0xffffffe0); 165 else 166 qtd = first_qtd; 167 168 /* 169 * Walk the qTD list and flush/invalidate all entries 170 */ 171 while (1) { 172 if (qtd == NULL) 173 break; 174 cache_qtd(qtd, flush); 175 next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0); 176 if (next == qtd) 177 break; 178 qtd = next; 179 } 180 } 181 182 static inline void ehci_flush_dcache(struct QH *qh) 183 { 184 cache_qh(qh, 1); 185 } 186 187 static inline void ehci_invalidate_dcache(struct QH *qh) 188 { 189 cache_qh(qh, 0); 190 } 191 #else /* CONFIG_EHCI_DCACHE */ 192 /* 193 * 194 */ 195 static inline void ehci_flush_dcache(struct QH *qh) 196 { 197 } 198 199 static inline void ehci_invalidate_dcache(struct QH *qh) 200 { 201 } 202 #endif /* CONFIG_EHCI_DCACHE */ 203 204 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 205 { 206 mdelay(50); 207 } 208 209 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 210 __attribute__((weak, alias("__ehci_powerup_fixup"))); 211 212 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 213 { 214 uint32_t result; 215 do { 216 result = ehci_readl(ptr); 217 udelay(5); 218 if (result == ~(uint32_t)0) 219 return -1; 220 result &= mask; 221 if (result == done) 222 return 0; 223 usec--; 224 } while (usec > 0); 225 return -1; 226 } 227 228 static void ehci_free(void *p, size_t sz) 229 { 230 231 } 232 233 static int ehci_reset(void) 234 { 235 uint32_t cmd; 236 uint32_t tmp; 237 uint32_t *reg_ptr; 238 int ret = 0; 239 240 cmd = ehci_readl(&hcor->or_usbcmd); 241 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 242 ehci_writel(&hcor->or_usbcmd, cmd); 243 ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000); 244 if (ret < 0) { 245 printf("EHCI fail to reset\n"); 246 goto out; 247 } 248 249 if (ehci_is_TDI()) { 250 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE); 251 tmp = ehci_readl(reg_ptr); 252 tmp |= USBMODE_CM_HC; 253 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 254 tmp |= USBMODE_BE; 255 #endif 256 ehci_writel(reg_ptr, tmp); 257 } 258 259 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH 260 cmd = ehci_readl(&hcor->or_txfilltuning); 261 cmd &= ~TXFIFO_THRESH(0x3f); 262 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); 263 ehci_writel(&hcor->or_txfilltuning, cmd); 264 #endif 265 out: 266 return ret; 267 } 268 269 static void *ehci_alloc(size_t sz, size_t align) 270 { 271 static struct QH qh __attribute__((aligned(32))); 272 static struct qTD td[3] __attribute__((aligned (32))); 273 static int ntds; 274 void *p; 275 276 switch (sz) { 277 case sizeof(struct QH): 278 p = &qh; 279 ntds = 0; 280 break; 281 case sizeof(struct qTD): 282 if (ntds == 3) { 283 debug("out of TDs\n"); 284 return NULL; 285 } 286 p = &td[ntds]; 287 ntds++; 288 break; 289 default: 290 debug("unknown allocation size\n"); 291 return NULL; 292 } 293 294 memset(p, 0, sz); 295 return p; 296 } 297 298 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 299 { 300 uint32_t addr, delta, next; 301 int idx; 302 303 addr = (uint32_t) buf; 304 idx = 0; 305 while (idx < 5) { 306 td->qt_buffer[idx] = cpu_to_hc32(addr); 307 td->qt_buffer_hi[idx] = 0; 308 next = (addr + 4096) & ~4095; 309 delta = next - addr; 310 if (delta >= sz) 311 break; 312 sz -= delta; 313 addr = next; 314 idx++; 315 } 316 317 if (idx == 5) { 318 debug("out of buffer pointers (%u bytes left)\n", sz); 319 return -1; 320 } 321 322 return 0; 323 } 324 325 static int 326 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 327 int length, struct devrequest *req) 328 { 329 struct QH *qh; 330 struct qTD *td; 331 volatile struct qTD *vtd; 332 unsigned long ts; 333 uint32_t *tdp; 334 uint32_t endpt, token, usbsts; 335 uint32_t c, toggle; 336 uint32_t cmd; 337 int timeout; 338 int ret = 0; 339 340 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 341 buffer, length, req); 342 if (req != NULL) 343 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 344 req->request, req->request, 345 req->requesttype, req->requesttype, 346 le16_to_cpu(req->value), le16_to_cpu(req->value), 347 le16_to_cpu(req->index)); 348 349 qh = ehci_alloc(sizeof(struct QH), 32); 350 if (qh == NULL) { 351 debug("unable to allocate QH\n"); 352 return -1; 353 } 354 qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 355 c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && 356 usb_pipeendpoint(pipe) == 0) ? 1 : 0; 357 endpt = (8 << 28) | 358 (c << 27) | 359 (usb_maxpacket(dev, pipe) << 16) | 360 (0 << 15) | 361 (1 << 14) | 362 (usb_pipespeed(pipe) << 12) | 363 (usb_pipeendpoint(pipe) << 8) | 364 (0 << 7) | (usb_pipedevice(pipe) << 0); 365 qh->qh_endpt1 = cpu_to_hc32(endpt); 366 endpt = (1 << 30) | 367 (dev->portnr << 23) | 368 (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); 369 qh->qh_endpt2 = cpu_to_hc32(endpt); 370 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 371 372 td = NULL; 373 tdp = &qh->qh_overlay.qt_next; 374 375 toggle = 376 usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 377 378 if (req != NULL) { 379 td = ehci_alloc(sizeof(struct qTD), 32); 380 if (td == NULL) { 381 debug("unable to allocate SETUP td\n"); 382 goto fail; 383 } 384 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 385 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 386 token = (0 << 31) | 387 (sizeof(*req) << 16) | 388 (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); 389 td->qt_token = cpu_to_hc32(token); 390 if (ehci_td_buffer(td, req, sizeof(*req)) != 0) { 391 debug("unable construct SETUP td\n"); 392 ehci_free(td, sizeof(*td)); 393 goto fail; 394 } 395 *tdp = cpu_to_hc32((uint32_t) td); 396 tdp = &td->qt_next; 397 toggle = 1; 398 } 399 400 if (length > 0 || req == NULL) { 401 td = ehci_alloc(sizeof(struct qTD), 32); 402 if (td == NULL) { 403 debug("unable to allocate DATA td\n"); 404 goto fail; 405 } 406 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 407 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 408 token = (toggle << 31) | 409 (length << 16) | 410 ((req == NULL ? 1 : 0) << 15) | 411 (0 << 12) | 412 (3 << 10) | 413 ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); 414 td->qt_token = cpu_to_hc32(token); 415 if (ehci_td_buffer(td, buffer, length) != 0) { 416 debug("unable construct DATA td\n"); 417 ehci_free(td, sizeof(*td)); 418 goto fail; 419 } 420 *tdp = cpu_to_hc32((uint32_t) td); 421 tdp = &td->qt_next; 422 } 423 424 if (req != NULL) { 425 td = ehci_alloc(sizeof(struct qTD), 32); 426 if (td == NULL) { 427 debug("unable to allocate ACK td\n"); 428 goto fail; 429 } 430 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 431 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 432 token = (toggle << 31) | 433 (0 << 16) | 434 (1 << 15) | 435 (0 << 12) | 436 (3 << 10) | 437 ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); 438 td->qt_token = cpu_to_hc32(token); 439 *tdp = cpu_to_hc32((uint32_t) td); 440 tdp = &td->qt_next; 441 } 442 443 qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH); 444 445 /* Flush dcache */ 446 ehci_flush_dcache(&qh_list); 447 448 usbsts = ehci_readl(&hcor->or_usbsts); 449 ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); 450 451 /* Enable async. schedule. */ 452 cmd = ehci_readl(&hcor->or_usbcmd); 453 cmd |= CMD_ASE; 454 ehci_writel(&hcor->or_usbcmd, cmd); 455 456 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS, 457 100 * 1000); 458 if (ret < 0) { 459 printf("EHCI fail timeout STD_ASS set\n"); 460 goto fail; 461 } 462 463 /* Wait for TDs to be processed. */ 464 ts = get_timer(0); 465 vtd = td; 466 timeout = USB_TIMEOUT_MS(pipe); 467 do { 468 /* Invalidate dcache */ 469 ehci_invalidate_dcache(&qh_list); 470 token = hc32_to_cpu(vtd->qt_token); 471 if (!(token & 0x80)) 472 break; 473 WATCHDOG_RESET(); 474 } while (get_timer(ts) < timeout); 475 476 /* Check that the TD processing happened */ 477 if (token & 0x80) { 478 printf("EHCI timed out on TD - token=%#x\n", token); 479 } 480 481 /* Disable async schedule. */ 482 cmd = ehci_readl(&hcor->or_usbcmd); 483 cmd &= ~CMD_ASE; 484 ehci_writel(&hcor->or_usbcmd, cmd); 485 486 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0, 487 100 * 1000); 488 if (ret < 0) { 489 printf("EHCI fail timeout STD_ASS reset\n"); 490 goto fail; 491 } 492 493 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 494 495 token = hc32_to_cpu(qh->qh_overlay.qt_token); 496 if (!(token & 0x80)) { 497 debug("TOKEN=%#x\n", token); 498 switch (token & 0xfc) { 499 case 0: 500 toggle = token >> 31; 501 usb_settoggle(dev, usb_pipeendpoint(pipe), 502 usb_pipeout(pipe), toggle); 503 dev->status = 0; 504 break; 505 case 0x40: 506 dev->status = USB_ST_STALLED; 507 break; 508 case 0xa0: 509 case 0x20: 510 dev->status = USB_ST_BUF_ERR; 511 break; 512 case 0x50: 513 case 0x10: 514 dev->status = USB_ST_BABBLE_DET; 515 break; 516 default: 517 dev->status = USB_ST_CRC_ERR; 518 if ((token & 0x40) == 0x40) 519 dev->status |= USB_ST_STALLED; 520 break; 521 } 522 dev->act_len = length - ((token >> 16) & 0x7fff); 523 } else { 524 dev->act_len = 0; 525 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 526 dev->devnum, ehci_readl(&hcor->or_usbsts), 527 ehci_readl(&hcor->or_portsc[0]), 528 ehci_readl(&hcor->or_portsc[1])); 529 } 530 531 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 532 533 fail: 534 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 535 while (td != (void *)QT_NEXT_TERMINATE) { 536 qh->qh_overlay.qt_next = td->qt_next; 537 ehci_free(td, sizeof(*td)); 538 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 539 } 540 ehci_free(qh, sizeof(*qh)); 541 return -1; 542 } 543 544 static inline int min3(int a, int b, int c) 545 { 546 547 if (b < a) 548 a = b; 549 if (c < a) 550 a = c; 551 return a; 552 } 553 554 int 555 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, 556 int length, struct devrequest *req) 557 { 558 uint8_t tmpbuf[4]; 559 u16 typeReq; 560 void *srcptr = NULL; 561 int len, srclen; 562 uint32_t reg; 563 uint32_t *status_reg; 564 565 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 566 printf("The request port(%d) is not configured\n", 567 le16_to_cpu(req->index) - 1); 568 return -1; 569 } 570 status_reg = (uint32_t *)&hcor->or_portsc[ 571 le16_to_cpu(req->index) - 1]; 572 srclen = 0; 573 574 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 575 req->request, req->request, 576 req->requesttype, req->requesttype, 577 le16_to_cpu(req->value), le16_to_cpu(req->index)); 578 579 typeReq = req->request | req->requesttype << 8; 580 581 switch (typeReq) { 582 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 583 switch (le16_to_cpu(req->value) >> 8) { 584 case USB_DT_DEVICE: 585 debug("USB_DT_DEVICE request\n"); 586 srcptr = &descriptor.device; 587 srclen = 0x12; 588 break; 589 case USB_DT_CONFIG: 590 debug("USB_DT_CONFIG config\n"); 591 srcptr = &descriptor.config; 592 srclen = 0x19; 593 break; 594 case USB_DT_STRING: 595 debug("USB_DT_STRING config\n"); 596 switch (le16_to_cpu(req->value) & 0xff) { 597 case 0: /* Language */ 598 srcptr = "\4\3\1\0"; 599 srclen = 4; 600 break; 601 case 1: /* Vendor */ 602 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 603 srclen = 14; 604 break; 605 case 2: /* Product */ 606 srcptr = "\52\3E\0H\0C\0I\0 " 607 "\0H\0o\0s\0t\0 " 608 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 609 srclen = 42; 610 break; 611 default: 612 debug("unknown value DT_STRING %x\n", 613 le16_to_cpu(req->value)); 614 goto unknown; 615 } 616 break; 617 default: 618 debug("unknown value %x\n", le16_to_cpu(req->value)); 619 goto unknown; 620 } 621 break; 622 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 623 switch (le16_to_cpu(req->value) >> 8) { 624 case USB_DT_HUB: 625 debug("USB_DT_HUB config\n"); 626 srcptr = &descriptor.hub; 627 srclen = 0x8; 628 break; 629 default: 630 debug("unknown value %x\n", le16_to_cpu(req->value)); 631 goto unknown; 632 } 633 break; 634 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 635 debug("USB_REQ_SET_ADDRESS\n"); 636 rootdev = le16_to_cpu(req->value); 637 break; 638 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 639 debug("USB_REQ_SET_CONFIGURATION\n"); 640 /* Nothing to do */ 641 break; 642 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 643 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 644 tmpbuf[1] = 0; 645 srcptr = tmpbuf; 646 srclen = 2; 647 break; 648 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 649 memset(tmpbuf, 0, 4); 650 reg = ehci_readl(status_reg); 651 if (reg & EHCI_PS_CS) 652 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 653 if (reg & EHCI_PS_PE) 654 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 655 if (reg & EHCI_PS_SUSP) 656 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 657 if (reg & EHCI_PS_OCA) 658 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 659 if (reg & EHCI_PS_PR) 660 tmpbuf[0] |= USB_PORT_STAT_RESET; 661 if (reg & EHCI_PS_PP) 662 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 663 664 if (ehci_is_TDI()) { 665 switch ((reg >> 26) & 3) { 666 case 0: 667 break; 668 case 1: 669 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 670 break; 671 case 2: 672 default: 673 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 674 break; 675 } 676 } else { 677 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 678 } 679 680 if (reg & EHCI_PS_CSC) 681 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 682 if (reg & EHCI_PS_PEC) 683 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 684 if (reg & EHCI_PS_OCC) 685 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 686 if (portreset & (1 << le16_to_cpu(req->index))) 687 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 688 689 srcptr = tmpbuf; 690 srclen = 4; 691 break; 692 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 693 reg = ehci_readl(status_reg); 694 reg &= ~EHCI_PS_CLEAR; 695 switch (le16_to_cpu(req->value)) { 696 case USB_PORT_FEAT_ENABLE: 697 reg |= EHCI_PS_PE; 698 ehci_writel(status_reg, reg); 699 break; 700 case USB_PORT_FEAT_POWER: 701 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) { 702 reg |= EHCI_PS_PP; 703 ehci_writel(status_reg, reg); 704 } 705 break; 706 case USB_PORT_FEAT_RESET: 707 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 708 !ehci_is_TDI() && 709 EHCI_PS_IS_LOWSPEED(reg)) { 710 /* Low speed device, give up ownership. */ 711 debug("port %d low speed --> companion\n", 712 req->index - 1); 713 reg |= EHCI_PS_PO; 714 ehci_writel(status_reg, reg); 715 break; 716 } else { 717 int ret; 718 719 reg |= EHCI_PS_PR; 720 reg &= ~EHCI_PS_PE; 721 ehci_writel(status_reg, reg); 722 /* 723 * caller must wait, then call GetPortStatus 724 * usb 2.0 specification say 50 ms resets on 725 * root 726 */ 727 ehci_powerup_fixup(status_reg, ®); 728 729 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 730 /* 731 * A host controller must terminate the reset 732 * and stabilize the state of the port within 733 * 2 milliseconds 734 */ 735 ret = handshake(status_reg, EHCI_PS_PR, 0, 736 2 * 1000); 737 if (!ret) 738 portreset |= 739 1 << le16_to_cpu(req->index); 740 else 741 printf("port(%d) reset error\n", 742 le16_to_cpu(req->index) - 1); 743 } 744 break; 745 default: 746 debug("unknown feature %x\n", le16_to_cpu(req->value)); 747 goto unknown; 748 } 749 /* unblock posted writes */ 750 (void) ehci_readl(&hcor->or_usbcmd); 751 break; 752 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 753 reg = ehci_readl(status_reg); 754 switch (le16_to_cpu(req->value)) { 755 case USB_PORT_FEAT_ENABLE: 756 reg &= ~EHCI_PS_PE; 757 break; 758 case USB_PORT_FEAT_C_ENABLE: 759 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE; 760 break; 761 case USB_PORT_FEAT_POWER: 762 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) 763 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP); 764 case USB_PORT_FEAT_C_CONNECTION: 765 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC; 766 break; 767 case USB_PORT_FEAT_OVER_CURRENT: 768 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; 769 break; 770 case USB_PORT_FEAT_C_RESET: 771 portreset &= ~(1 << le16_to_cpu(req->index)); 772 break; 773 default: 774 debug("unknown feature %x\n", le16_to_cpu(req->value)); 775 goto unknown; 776 } 777 ehci_writel(status_reg, reg); 778 /* unblock posted write */ 779 (void) ehci_readl(&hcor->or_usbcmd); 780 break; 781 default: 782 debug("Unknown request\n"); 783 goto unknown; 784 } 785 786 mdelay(1); 787 len = min3(srclen, le16_to_cpu(req->length), length); 788 if (srcptr != NULL && len > 0) 789 memcpy(buffer, srcptr, len); 790 else 791 debug("Len is 0\n"); 792 793 dev->act_len = len; 794 dev->status = 0; 795 return 0; 796 797 unknown: 798 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 799 req->requesttype, req->request, le16_to_cpu(req->value), 800 le16_to_cpu(req->index), le16_to_cpu(req->length)); 801 802 dev->act_len = 0; 803 dev->status = USB_ST_STALLED; 804 return -1; 805 } 806 807 int usb_lowlevel_stop(void) 808 { 809 return ehci_hcd_stop(); 810 } 811 812 int usb_lowlevel_init(void) 813 { 814 uint32_t reg; 815 uint32_t cmd; 816 817 if (ehci_hcd_init() != 0) 818 return -1; 819 820 /* EHCI spec section 4.1 */ 821 if (ehci_reset() != 0) 822 return -1; 823 824 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 825 if (ehci_hcd_init() != 0) 826 return -1; 827 #endif 828 829 /* Set head of reclaim list */ 830 memset(&qh_list, 0, sizeof(qh_list)); 831 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 832 qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); 833 qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); 834 qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 835 qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 836 qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40); 837 838 /* Set async. queue head pointer. */ 839 ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list); 840 841 reg = ehci_readl(&hccr->cr_hcsparams); 842 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 843 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 844 /* Port Indicators */ 845 if (HCS_INDICATOR(reg)) 846 descriptor.hub.wHubCharacteristics |= 0x80; 847 /* Port Power Control */ 848 if (HCS_PPC(reg)) 849 descriptor.hub.wHubCharacteristics |= 0x01; 850 851 /* Start the host controller. */ 852 cmd = ehci_readl(&hcor->or_usbcmd); 853 /* 854 * Philips, Intel, and maybe others need CMD_RUN before the 855 * root hub will detect new devices (why?); NEC doesn't 856 */ 857 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 858 cmd |= CMD_RUN; 859 ehci_writel(&hcor->or_usbcmd, cmd); 860 861 /* take control over the ports */ 862 cmd = ehci_readl(&hcor->or_configflag); 863 cmd |= FLAG_CF; 864 ehci_writel(&hcor->or_configflag, cmd); 865 /* unblock posted write */ 866 cmd = ehci_readl(&hcor->or_usbcmd); 867 mdelay(5); 868 reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); 869 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 870 871 rootdev = 0; 872 873 return 0; 874 } 875 876 int 877 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 878 int length) 879 { 880 881 if (usb_pipetype(pipe) != PIPE_BULK) { 882 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 883 return -1; 884 } 885 return ehci_submit_async(dev, pipe, buffer, length, NULL); 886 } 887 888 int 889 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 890 int length, struct devrequest *setup) 891 { 892 893 if (usb_pipetype(pipe) != PIPE_CONTROL) { 894 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 895 return -1; 896 } 897 898 if (usb_pipedevice(pipe) == rootdev) { 899 if (rootdev == 0) 900 dev->speed = USB_SPEED_HIGH; 901 return ehci_submit_root(dev, pipe, buffer, length, setup); 902 } 903 return ehci_submit_async(dev, pipe, buffer, length, setup); 904 } 905 906 int 907 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 908 int length, int interval) 909 { 910 911 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 912 dev, pipe, buffer, length, interval); 913 return ehci_submit_async(dev, pipe, buffer, length, NULL); 914 } 915