1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <asm/byteorder.h> 25 #include <usb.h> 26 #include <asm/io.h> 27 #include <malloc.h> 28 #include <watchdog.h> 29 30 #include "ehci.h" 31 32 int rootdev; 33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ 34 volatile struct ehci_hcor *hcor; 35 36 static uint16_t portreset; 37 static struct QH qh_list __attribute__((aligned(32))); 38 39 static struct descriptor { 40 struct usb_hub_descriptor hub; 41 struct usb_device_descriptor device; 42 struct usb_linux_config_descriptor config; 43 struct usb_linux_interface_descriptor interface; 44 struct usb_endpoint_descriptor endpoint; 45 } __attribute__ ((packed)) descriptor = { 46 { 47 0x8, /* bDescLength */ 48 0x29, /* bDescriptorType: hub descriptor */ 49 2, /* bNrPorts -- runtime modified */ 50 0, /* wHubCharacteristics */ 51 10, /* bPwrOn2PwrGood */ 52 0, /* bHubCntrCurrent */ 53 {}, /* Device removable */ 54 {} /* at most 7 ports! XXX */ 55 }, 56 { 57 0x12, /* bLength */ 58 1, /* bDescriptorType: UDESC_DEVICE */ 59 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 60 9, /* bDeviceClass: UDCLASS_HUB */ 61 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 62 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 63 64, /* bMaxPacketSize: 64 bytes */ 64 0x0000, /* idVendor */ 65 0x0000, /* idProduct */ 66 cpu_to_le16(0x0100), /* bcdDevice */ 67 1, /* iManufacturer */ 68 2, /* iProduct */ 69 0, /* iSerialNumber */ 70 1 /* bNumConfigurations: 1 */ 71 }, 72 { 73 0x9, 74 2, /* bDescriptorType: UDESC_CONFIG */ 75 cpu_to_le16(0x19), 76 1, /* bNumInterface */ 77 1, /* bConfigurationValue */ 78 0, /* iConfiguration */ 79 0x40, /* bmAttributes: UC_SELF_POWER */ 80 0 /* bMaxPower */ 81 }, 82 { 83 0x9, /* bLength */ 84 4, /* bDescriptorType: UDESC_INTERFACE */ 85 0, /* bInterfaceNumber */ 86 0, /* bAlternateSetting */ 87 1, /* bNumEndpoints */ 88 9, /* bInterfaceClass: UICLASS_HUB */ 89 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 90 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 91 0 /* iInterface */ 92 }, 93 { 94 0x7, /* bLength */ 95 5, /* bDescriptorType: UDESC_ENDPOINT */ 96 0x81, /* bEndpointAddress: 97 * UE_DIR_IN | EHCI_INTR_ENDPT 98 */ 99 3, /* bmAttributes: UE_INTERRUPT */ 100 8, /* wMaxPacketSize */ 101 255 /* bInterval */ 102 }, 103 }; 104 105 #if defined(CONFIG_EHCI_IS_TDI) 106 #define ehci_is_TDI() (1) 107 #else 108 #define ehci_is_TDI() (0) 109 #endif 110 111 #if defined(CONFIG_EHCI_DCACHE) 112 /* 113 * Routines to handle (flush/invalidate) the dcache for the QH and qTD 114 * structures and data buffers. This is needed on platforms using this 115 * EHCI support with dcache enabled. 116 */ 117 static void flush_invalidate(u32 addr, int size, int flush) 118 { 119 if (flush) 120 flush_dcache_range(addr, addr + size); 121 else 122 invalidate_dcache_range(addr, addr + size); 123 } 124 125 static void cache_qtd(struct qTD *qtd, int flush) 126 { 127 u32 *ptr = (u32 *)qtd->qt_buffer[0]; 128 int len = (qtd->qt_token & 0x7fff0000) >> 16; 129 130 flush_invalidate((u32)qtd, sizeof(struct qTD), flush); 131 if (ptr && len) 132 flush_invalidate((u32)ptr, len, flush); 133 } 134 135 136 static inline struct QH *qh_addr(struct QH *qh) 137 { 138 return (struct QH *)((u32)qh & 0xffffffe0); 139 } 140 141 static void cache_qh(struct QH *qh, int flush) 142 { 143 struct qTD *qtd; 144 struct qTD *next; 145 static struct qTD *first_qtd; 146 147 /* 148 * Walk the QH list and flush/invalidate all entries 149 */ 150 while (1) { 151 flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush); 152 if ((u32)qh & QH_LINK_TYPE_QH) 153 break; 154 qh = qh_addr(qh); 155 qh = (struct QH *)qh->qh_link; 156 } 157 qh = qh_addr(qh); 158 159 /* 160 * Save first qTD pointer, needed for invalidating pass on this QH 161 */ 162 if (flush) 163 first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay & 164 0xffffffe0); 165 else 166 qtd = first_qtd; 167 168 /* 169 * Walk the qTD list and flush/invalidate all entries 170 */ 171 while (1) { 172 if (qtd == NULL) 173 break; 174 cache_qtd(qtd, flush); 175 next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0); 176 if (next == qtd) 177 break; 178 qtd = next; 179 } 180 } 181 182 static inline void ehci_flush_dcache(struct QH *qh) 183 { 184 cache_qh(qh, 1); 185 } 186 187 static inline void ehci_invalidate_dcache(struct QH *qh) 188 { 189 cache_qh(qh, 0); 190 } 191 #else /* CONFIG_EHCI_DCACHE */ 192 /* 193 * 194 */ 195 static inline void ehci_flush_dcache(struct QH *qh) 196 { 197 } 198 199 static inline void ehci_invalidate_dcache(struct QH *qh) 200 { 201 } 202 #endif /* CONFIG_EHCI_DCACHE */ 203 204 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 205 { 206 mdelay(50); 207 } 208 209 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 210 __attribute__((weak, alias("__ehci_powerup_fixup"))); 211 212 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 213 { 214 uint32_t result; 215 do { 216 result = ehci_readl(ptr); 217 udelay(5); 218 if (result == ~(uint32_t)0) 219 return -1; 220 result &= mask; 221 if (result == done) 222 return 0; 223 usec--; 224 } while (usec > 0); 225 return -1; 226 } 227 228 static void ehci_free(void *p, size_t sz) 229 { 230 231 } 232 233 static int ehci_reset(void) 234 { 235 uint32_t cmd; 236 uint32_t tmp; 237 uint32_t *reg_ptr; 238 int ret = 0; 239 240 cmd = ehci_readl(&hcor->or_usbcmd); 241 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 242 ehci_writel(&hcor->or_usbcmd, cmd); 243 ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000); 244 if (ret < 0) { 245 printf("EHCI fail to reset\n"); 246 goto out; 247 } 248 249 if (ehci_is_TDI()) { 250 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE); 251 tmp = ehci_readl(reg_ptr); 252 tmp |= USBMODE_CM_HC; 253 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 254 tmp |= USBMODE_BE; 255 #endif 256 ehci_writel(reg_ptr, tmp); 257 } 258 out: 259 return ret; 260 } 261 262 static void *ehci_alloc(size_t sz, size_t align) 263 { 264 static struct QH qh __attribute__((aligned(32))); 265 static struct qTD td[3] __attribute__((aligned (32))); 266 static int ntds; 267 void *p; 268 269 switch (sz) { 270 case sizeof(struct QH): 271 p = &qh; 272 ntds = 0; 273 break; 274 case sizeof(struct qTD): 275 if (ntds == 3) { 276 debug("out of TDs\n"); 277 return NULL; 278 } 279 p = &td[ntds]; 280 ntds++; 281 break; 282 default: 283 debug("unknown allocation size\n"); 284 return NULL; 285 } 286 287 memset(p, 0, sz); 288 return p; 289 } 290 291 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 292 { 293 uint32_t addr, delta, next; 294 int idx; 295 296 addr = (uint32_t) buf; 297 idx = 0; 298 while (idx < 5) { 299 td->qt_buffer[idx] = cpu_to_hc32(addr); 300 td->qt_buffer_hi[idx] = 0; 301 next = (addr + 4096) & ~4095; 302 delta = next - addr; 303 if (delta >= sz) 304 break; 305 sz -= delta; 306 addr = next; 307 idx++; 308 } 309 310 if (idx == 5) { 311 debug("out of buffer pointers (%u bytes left)\n", sz); 312 return -1; 313 } 314 315 return 0; 316 } 317 318 static int 319 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 320 int length, struct devrequest *req) 321 { 322 struct QH *qh; 323 struct qTD *td; 324 volatile struct qTD *vtd; 325 unsigned long ts; 326 uint32_t *tdp; 327 uint32_t endpt, token, usbsts; 328 uint32_t c, toggle; 329 uint32_t cmd; 330 int timeout; 331 int ret = 0; 332 333 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 334 buffer, length, req); 335 if (req != NULL) 336 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 337 req->request, req->request, 338 req->requesttype, req->requesttype, 339 le16_to_cpu(req->value), le16_to_cpu(req->value), 340 le16_to_cpu(req->index)); 341 342 qh = ehci_alloc(sizeof(struct QH), 32); 343 if (qh == NULL) { 344 debug("unable to allocate QH\n"); 345 return -1; 346 } 347 qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 348 c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && 349 usb_pipeendpoint(pipe) == 0) ? 1 : 0; 350 endpt = (8 << 28) | 351 (c << 27) | 352 (usb_maxpacket(dev, pipe) << 16) | 353 (0 << 15) | 354 (1 << 14) | 355 (usb_pipespeed(pipe) << 12) | 356 (usb_pipeendpoint(pipe) << 8) | 357 (0 << 7) | (usb_pipedevice(pipe) << 0); 358 qh->qh_endpt1 = cpu_to_hc32(endpt); 359 endpt = (1 << 30) | 360 (dev->portnr << 23) | 361 (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); 362 qh->qh_endpt2 = cpu_to_hc32(endpt); 363 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 364 365 td = NULL; 366 tdp = &qh->qh_overlay.qt_next; 367 368 toggle = 369 usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 370 371 if (req != NULL) { 372 td = ehci_alloc(sizeof(struct qTD), 32); 373 if (td == NULL) { 374 debug("unable to allocate SETUP td\n"); 375 goto fail; 376 } 377 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 378 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 379 token = (0 << 31) | 380 (sizeof(*req) << 16) | 381 (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); 382 td->qt_token = cpu_to_hc32(token); 383 if (ehci_td_buffer(td, req, sizeof(*req)) != 0) { 384 debug("unable construct SETUP td\n"); 385 ehci_free(td, sizeof(*td)); 386 goto fail; 387 } 388 *tdp = cpu_to_hc32((uint32_t) td); 389 tdp = &td->qt_next; 390 toggle = 1; 391 } 392 393 if (length > 0 || req == NULL) { 394 td = ehci_alloc(sizeof(struct qTD), 32); 395 if (td == NULL) { 396 debug("unable to allocate DATA td\n"); 397 goto fail; 398 } 399 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 400 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 401 token = (toggle << 31) | 402 (length << 16) | 403 ((req == NULL ? 1 : 0) << 15) | 404 (0 << 12) | 405 (3 << 10) | 406 ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); 407 td->qt_token = cpu_to_hc32(token); 408 if (ehci_td_buffer(td, buffer, length) != 0) { 409 debug("unable construct DATA td\n"); 410 ehci_free(td, sizeof(*td)); 411 goto fail; 412 } 413 *tdp = cpu_to_hc32((uint32_t) td); 414 tdp = &td->qt_next; 415 } 416 417 if (req != NULL) { 418 td = ehci_alloc(sizeof(struct qTD), 32); 419 if (td == NULL) { 420 debug("unable to allocate ACK td\n"); 421 goto fail; 422 } 423 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 424 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 425 token = (toggle << 31) | 426 (0 << 16) | 427 (1 << 15) | 428 (0 << 12) | 429 (3 << 10) | 430 ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); 431 td->qt_token = cpu_to_hc32(token); 432 *tdp = cpu_to_hc32((uint32_t) td); 433 tdp = &td->qt_next; 434 } 435 436 qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH); 437 438 /* Flush dcache */ 439 ehci_flush_dcache(&qh_list); 440 441 usbsts = ehci_readl(&hcor->or_usbsts); 442 ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); 443 444 /* Enable async. schedule. */ 445 cmd = ehci_readl(&hcor->or_usbcmd); 446 cmd |= CMD_ASE; 447 ehci_writel(&hcor->or_usbcmd, cmd); 448 449 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS, 450 100 * 1000); 451 if (ret < 0) { 452 printf("EHCI fail timeout STD_ASS set\n"); 453 goto fail; 454 } 455 456 /* Wait for TDs to be processed. */ 457 ts = get_timer(0); 458 vtd = td; 459 timeout = USB_TIMEOUT_MS(pipe); 460 do { 461 /* Invalidate dcache */ 462 ehci_invalidate_dcache(&qh_list); 463 token = hc32_to_cpu(vtd->qt_token); 464 if (!(token & 0x80)) 465 break; 466 WATCHDOG_RESET(); 467 } while (get_timer(ts) < timeout); 468 469 /* Check that the TD processing happened */ 470 if (token & 0x80) { 471 printf("EHCI timed out on TD - token=%#x\n", token); 472 } 473 474 /* Disable async schedule. */ 475 cmd = ehci_readl(&hcor->or_usbcmd); 476 cmd &= ~CMD_ASE; 477 ehci_writel(&hcor->or_usbcmd, cmd); 478 479 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0, 480 100 * 1000); 481 if (ret < 0) { 482 printf("EHCI fail timeout STD_ASS reset\n"); 483 goto fail; 484 } 485 486 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 487 488 token = hc32_to_cpu(qh->qh_overlay.qt_token); 489 if (!(token & 0x80)) { 490 debug("TOKEN=%#x\n", token); 491 switch (token & 0xfc) { 492 case 0: 493 toggle = token >> 31; 494 usb_settoggle(dev, usb_pipeendpoint(pipe), 495 usb_pipeout(pipe), toggle); 496 dev->status = 0; 497 break; 498 case 0x40: 499 dev->status = USB_ST_STALLED; 500 break; 501 case 0xa0: 502 case 0x20: 503 dev->status = USB_ST_BUF_ERR; 504 break; 505 case 0x50: 506 case 0x10: 507 dev->status = USB_ST_BABBLE_DET; 508 break; 509 default: 510 dev->status = USB_ST_CRC_ERR; 511 if ((token & 0x40) == 0x40) 512 dev->status |= USB_ST_STALLED; 513 break; 514 } 515 dev->act_len = length - ((token >> 16) & 0x7fff); 516 } else { 517 dev->act_len = 0; 518 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 519 dev->devnum, ehci_readl(&hcor->or_usbsts), 520 ehci_readl(&hcor->or_portsc[0]), 521 ehci_readl(&hcor->or_portsc[1])); 522 } 523 524 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 525 526 fail: 527 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 528 while (td != (void *)QT_NEXT_TERMINATE) { 529 qh->qh_overlay.qt_next = td->qt_next; 530 ehci_free(td, sizeof(*td)); 531 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 532 } 533 ehci_free(qh, sizeof(*qh)); 534 return -1; 535 } 536 537 static inline int min3(int a, int b, int c) 538 { 539 540 if (b < a) 541 a = b; 542 if (c < a) 543 a = c; 544 return a; 545 } 546 547 int 548 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, 549 int length, struct devrequest *req) 550 { 551 uint8_t tmpbuf[4]; 552 u16 typeReq; 553 void *srcptr = NULL; 554 int len, srclen; 555 uint32_t reg; 556 uint32_t *status_reg; 557 558 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 559 printf("The request port(%d) is not configured\n", 560 le16_to_cpu(req->index) - 1); 561 return -1; 562 } 563 status_reg = (uint32_t *)&hcor->or_portsc[ 564 le16_to_cpu(req->index) - 1]; 565 srclen = 0; 566 567 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 568 req->request, req->request, 569 req->requesttype, req->requesttype, 570 le16_to_cpu(req->value), le16_to_cpu(req->index)); 571 572 typeReq = req->request | req->requesttype << 8; 573 574 switch (typeReq) { 575 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 576 switch (le16_to_cpu(req->value) >> 8) { 577 case USB_DT_DEVICE: 578 debug("USB_DT_DEVICE request\n"); 579 srcptr = &descriptor.device; 580 srclen = 0x12; 581 break; 582 case USB_DT_CONFIG: 583 debug("USB_DT_CONFIG config\n"); 584 srcptr = &descriptor.config; 585 srclen = 0x19; 586 break; 587 case USB_DT_STRING: 588 debug("USB_DT_STRING config\n"); 589 switch (le16_to_cpu(req->value) & 0xff) { 590 case 0: /* Language */ 591 srcptr = "\4\3\1\0"; 592 srclen = 4; 593 break; 594 case 1: /* Vendor */ 595 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 596 srclen = 14; 597 break; 598 case 2: /* Product */ 599 srcptr = "\52\3E\0H\0C\0I\0 " 600 "\0H\0o\0s\0t\0 " 601 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 602 srclen = 42; 603 break; 604 default: 605 debug("unknown value DT_STRING %x\n", 606 le16_to_cpu(req->value)); 607 goto unknown; 608 } 609 break; 610 default: 611 debug("unknown value %x\n", le16_to_cpu(req->value)); 612 goto unknown; 613 } 614 break; 615 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 616 switch (le16_to_cpu(req->value) >> 8) { 617 case USB_DT_HUB: 618 debug("USB_DT_HUB config\n"); 619 srcptr = &descriptor.hub; 620 srclen = 0x8; 621 break; 622 default: 623 debug("unknown value %x\n", le16_to_cpu(req->value)); 624 goto unknown; 625 } 626 break; 627 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 628 debug("USB_REQ_SET_ADDRESS\n"); 629 rootdev = le16_to_cpu(req->value); 630 break; 631 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 632 debug("USB_REQ_SET_CONFIGURATION\n"); 633 /* Nothing to do */ 634 break; 635 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 636 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 637 tmpbuf[1] = 0; 638 srcptr = tmpbuf; 639 srclen = 2; 640 break; 641 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 642 memset(tmpbuf, 0, 4); 643 reg = ehci_readl(status_reg); 644 if (reg & EHCI_PS_CS) 645 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 646 if (reg & EHCI_PS_PE) 647 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 648 if (reg & EHCI_PS_SUSP) 649 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 650 if (reg & EHCI_PS_OCA) 651 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 652 if (reg & EHCI_PS_PR) 653 tmpbuf[0] |= USB_PORT_STAT_RESET; 654 if (reg & EHCI_PS_PP) 655 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 656 657 if (ehci_is_TDI()) { 658 switch ((reg >> 26) & 3) { 659 case 0: 660 break; 661 case 1: 662 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 663 break; 664 case 2: 665 default: 666 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 667 break; 668 } 669 } else { 670 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 671 } 672 673 if (reg & EHCI_PS_CSC) 674 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 675 if (reg & EHCI_PS_PEC) 676 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 677 if (reg & EHCI_PS_OCC) 678 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 679 if (portreset & (1 << le16_to_cpu(req->index))) 680 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 681 682 srcptr = tmpbuf; 683 srclen = 4; 684 break; 685 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 686 reg = ehci_readl(status_reg); 687 reg &= ~EHCI_PS_CLEAR; 688 switch (le16_to_cpu(req->value)) { 689 case USB_PORT_FEAT_ENABLE: 690 reg |= EHCI_PS_PE; 691 ehci_writel(status_reg, reg); 692 break; 693 case USB_PORT_FEAT_POWER: 694 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) { 695 reg |= EHCI_PS_PP; 696 ehci_writel(status_reg, reg); 697 } 698 break; 699 case USB_PORT_FEAT_RESET: 700 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 701 !ehci_is_TDI() && 702 EHCI_PS_IS_LOWSPEED(reg)) { 703 /* Low speed device, give up ownership. */ 704 debug("port %d low speed --> companion\n", 705 req->index - 1); 706 reg |= EHCI_PS_PO; 707 ehci_writel(status_reg, reg); 708 break; 709 } else { 710 int ret; 711 712 reg |= EHCI_PS_PR; 713 reg &= ~EHCI_PS_PE; 714 ehci_writel(status_reg, reg); 715 /* 716 * caller must wait, then call GetPortStatus 717 * usb 2.0 specification say 50 ms resets on 718 * root 719 */ 720 ehci_powerup_fixup(status_reg, ®); 721 722 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 723 /* 724 * A host controller must terminate the reset 725 * and stabilize the state of the port within 726 * 2 milliseconds 727 */ 728 ret = handshake(status_reg, EHCI_PS_PR, 0, 729 2 * 1000); 730 if (!ret) 731 portreset |= 732 1 << le16_to_cpu(req->index); 733 else 734 printf("port(%d) reset error\n", 735 le16_to_cpu(req->index) - 1); 736 } 737 break; 738 default: 739 debug("unknown feature %x\n", le16_to_cpu(req->value)); 740 goto unknown; 741 } 742 /* unblock posted writes */ 743 (void) ehci_readl(&hcor->or_usbcmd); 744 break; 745 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 746 reg = ehci_readl(status_reg); 747 switch (le16_to_cpu(req->value)) { 748 case USB_PORT_FEAT_ENABLE: 749 reg &= ~EHCI_PS_PE; 750 break; 751 case USB_PORT_FEAT_C_ENABLE: 752 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE; 753 break; 754 case USB_PORT_FEAT_POWER: 755 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) 756 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP); 757 case USB_PORT_FEAT_C_CONNECTION: 758 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC; 759 break; 760 case USB_PORT_FEAT_OVER_CURRENT: 761 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; 762 break; 763 case USB_PORT_FEAT_C_RESET: 764 portreset &= ~(1 << le16_to_cpu(req->index)); 765 break; 766 default: 767 debug("unknown feature %x\n", le16_to_cpu(req->value)); 768 goto unknown; 769 } 770 ehci_writel(status_reg, reg); 771 /* unblock posted write */ 772 (void) ehci_readl(&hcor->or_usbcmd); 773 break; 774 default: 775 debug("Unknown request\n"); 776 goto unknown; 777 } 778 779 mdelay(1); 780 len = min3(srclen, le16_to_cpu(req->length), length); 781 if (srcptr != NULL && len > 0) 782 memcpy(buffer, srcptr, len); 783 else 784 debug("Len is 0\n"); 785 786 dev->act_len = len; 787 dev->status = 0; 788 return 0; 789 790 unknown: 791 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 792 req->requesttype, req->request, le16_to_cpu(req->value), 793 le16_to_cpu(req->index), le16_to_cpu(req->length)); 794 795 dev->act_len = 0; 796 dev->status = USB_ST_STALLED; 797 return -1; 798 } 799 800 int usb_lowlevel_stop(void) 801 { 802 return ehci_hcd_stop(); 803 } 804 805 int usb_lowlevel_init(void) 806 { 807 uint32_t reg; 808 uint32_t cmd; 809 810 if (ehci_hcd_init() != 0) 811 return -1; 812 813 /* EHCI spec section 4.1 */ 814 if (ehci_reset() != 0) 815 return -1; 816 817 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 818 if (ehci_hcd_init() != 0) 819 return -1; 820 #endif 821 822 /* Set head of reclaim list */ 823 memset(&qh_list, 0, sizeof(qh_list)); 824 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 825 qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); 826 qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); 827 qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 828 qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 829 qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40); 830 831 /* Set async. queue head pointer. */ 832 ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list); 833 834 reg = ehci_readl(&hccr->cr_hcsparams); 835 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 836 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 837 /* Port Indicators */ 838 if (HCS_INDICATOR(reg)) 839 descriptor.hub.wHubCharacteristics |= 0x80; 840 /* Port Power Control */ 841 if (HCS_PPC(reg)) 842 descriptor.hub.wHubCharacteristics |= 0x01; 843 844 /* Start the host controller. */ 845 cmd = ehci_readl(&hcor->or_usbcmd); 846 /* 847 * Philips, Intel, and maybe others need CMD_RUN before the 848 * root hub will detect new devices (why?); NEC doesn't 849 */ 850 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 851 cmd |= CMD_RUN; 852 ehci_writel(&hcor->or_usbcmd, cmd); 853 854 /* take control over the ports */ 855 cmd = ehci_readl(&hcor->or_configflag); 856 cmd |= FLAG_CF; 857 ehci_writel(&hcor->or_configflag, cmd); 858 /* unblock posted write */ 859 cmd = ehci_readl(&hcor->or_usbcmd); 860 mdelay(5); 861 reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); 862 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 863 864 rootdev = 0; 865 866 return 0; 867 } 868 869 int 870 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 871 int length) 872 { 873 874 if (usb_pipetype(pipe) != PIPE_BULK) { 875 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 876 return -1; 877 } 878 return ehci_submit_async(dev, pipe, buffer, length, NULL); 879 } 880 881 int 882 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 883 int length, struct devrequest *setup) 884 { 885 886 if (usb_pipetype(pipe) != PIPE_CONTROL) { 887 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 888 return -1; 889 } 890 891 if (usb_pipedevice(pipe) == rootdev) { 892 if (rootdev == 0) 893 dev->speed = USB_SPEED_HIGH; 894 return ehci_submit_root(dev, pipe, buffer, length, setup); 895 } 896 return ehci_submit_async(dev, pipe, buffer, length, setup); 897 } 898 899 int 900 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 901 int length, int interval) 902 { 903 904 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 905 dev, pipe, buffer, length, interval); 906 return ehci_submit_async(dev, pipe, buffer, length, NULL); 907 } 908 909