1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <asm/byteorder.h> 25 #include <usb.h> 26 #include <asm/io.h> 27 #include <malloc.h> 28 #include <watchdog.h> 29 30 #include "ehci.h" 31 32 int rootdev; 33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ 34 volatile struct ehci_hcor *hcor; 35 36 static uint16_t portreset; 37 static struct QH qh_list __attribute__((aligned(32))); 38 39 static struct descriptor { 40 struct usb_hub_descriptor hub; 41 struct usb_device_descriptor device; 42 struct usb_linux_config_descriptor config; 43 struct usb_linux_interface_descriptor interface; 44 struct usb_endpoint_descriptor endpoint; 45 } __attribute__ ((packed)) descriptor = { 46 { 47 0x8, /* bDescLength */ 48 0x29, /* bDescriptorType: hub descriptor */ 49 2, /* bNrPorts -- runtime modified */ 50 0, /* wHubCharacteristics */ 51 0xff, /* bPwrOn2PwrGood */ 52 0, /* bHubCntrCurrent */ 53 {}, /* Device removable */ 54 {} /* at most 7 ports! XXX */ 55 }, 56 { 57 0x12, /* bLength */ 58 1, /* bDescriptorType: UDESC_DEVICE */ 59 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 60 9, /* bDeviceClass: UDCLASS_HUB */ 61 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 62 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 63 64, /* bMaxPacketSize: 64 bytes */ 64 0x0000, /* idVendor */ 65 0x0000, /* idProduct */ 66 cpu_to_le16(0x0100), /* bcdDevice */ 67 1, /* iManufacturer */ 68 2, /* iProduct */ 69 0, /* iSerialNumber */ 70 1 /* bNumConfigurations: 1 */ 71 }, 72 { 73 0x9, 74 2, /* bDescriptorType: UDESC_CONFIG */ 75 cpu_to_le16(0x19), 76 1, /* bNumInterface */ 77 1, /* bConfigurationValue */ 78 0, /* iConfiguration */ 79 0x40, /* bmAttributes: UC_SELF_POWER */ 80 0 /* bMaxPower */ 81 }, 82 { 83 0x9, /* bLength */ 84 4, /* bDescriptorType: UDESC_INTERFACE */ 85 0, /* bInterfaceNumber */ 86 0, /* bAlternateSetting */ 87 1, /* bNumEndpoints */ 88 9, /* bInterfaceClass: UICLASS_HUB */ 89 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 90 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 91 0 /* iInterface */ 92 }, 93 { 94 0x7, /* bLength */ 95 5, /* bDescriptorType: UDESC_ENDPOINT */ 96 0x81, /* bEndpointAddress: 97 * UE_DIR_IN | EHCI_INTR_ENDPT 98 */ 99 3, /* bmAttributes: UE_INTERRUPT */ 100 8, /* wMaxPacketSize */ 101 255 /* bInterval */ 102 }, 103 }; 104 105 #if defined(CONFIG_EHCI_IS_TDI) 106 #define ehci_is_TDI() (1) 107 #else 108 #define ehci_is_TDI() (0) 109 #endif 110 111 #if defined(CONFIG_EHCI_DCACHE) 112 /* 113 * Routines to handle (flush/invalidate) the dcache for the QH and qTD 114 * structures and data buffers. This is needed on platforms using this 115 * EHCI support with dcache enabled. 116 */ 117 static void flush_invalidate(u32 addr, int size, int flush) 118 { 119 if (flush) 120 flush_dcache_range(addr, addr + size); 121 else 122 invalidate_dcache_range(addr, addr + size); 123 } 124 125 static void cache_qtd(struct qTD *qtd, int flush) 126 { 127 u32 *ptr = (u32 *)qtd->qt_buffer[0]; 128 int len = (qtd->qt_token & 0x7fff0000) >> 16; 129 130 flush_invalidate((u32)qtd, sizeof(struct qTD), flush); 131 if (ptr && len) 132 flush_invalidate((u32)ptr, len, flush); 133 } 134 135 136 static inline struct QH *qh_addr(struct QH *qh) 137 { 138 return (struct QH *)((u32)qh & 0xffffffe0); 139 } 140 141 static void cache_qh(struct QH *qh, int flush) 142 { 143 struct qTD *qtd; 144 struct qTD *next; 145 static struct qTD *first_qtd; 146 147 /* 148 * Walk the QH list and flush/invalidate all entries 149 */ 150 while (1) { 151 flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush); 152 if ((u32)qh & QH_LINK_TYPE_QH) 153 break; 154 qh = qh_addr(qh); 155 qh = (struct QH *)qh->qh_link; 156 } 157 qh = qh_addr(qh); 158 159 /* 160 * Save first qTD pointer, needed for invalidating pass on this QH 161 */ 162 if (flush) 163 first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay & 164 0xffffffe0); 165 else 166 qtd = first_qtd; 167 168 /* 169 * Walk the qTD list and flush/invalidate all entries 170 */ 171 while (1) { 172 if (qtd == NULL) 173 break; 174 cache_qtd(qtd, flush); 175 next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0); 176 if (next == qtd) 177 break; 178 qtd = next; 179 } 180 } 181 182 static inline void ehci_flush_dcache(struct QH *qh) 183 { 184 cache_qh(qh, 1); 185 } 186 187 static inline void ehci_invalidate_dcache(struct QH *qh) 188 { 189 cache_qh(qh, 0); 190 } 191 #else /* CONFIG_EHCI_DCACHE */ 192 /* 193 * 194 */ 195 static inline void ehci_flush_dcache(struct QH *qh) 196 { 197 } 198 199 static inline void ehci_invalidate_dcache(struct QH *qh) 200 { 201 } 202 #endif /* CONFIG_EHCI_DCACHE */ 203 204 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 205 { 206 uint32_t result; 207 do { 208 result = ehci_readl(ptr); 209 udelay(5); 210 if (result == ~(uint32_t)0) 211 return -1; 212 result &= mask; 213 if (result == done) 214 return 0; 215 usec--; 216 } while (usec > 0); 217 return -1; 218 } 219 220 static void ehci_free(void *p, size_t sz) 221 { 222 223 } 224 225 static int ehci_reset(void) 226 { 227 uint32_t cmd; 228 uint32_t tmp; 229 uint32_t *reg_ptr; 230 int ret = 0; 231 232 cmd = ehci_readl(&hcor->or_usbcmd); 233 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 234 ehci_writel(&hcor->or_usbcmd, cmd); 235 ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000); 236 if (ret < 0) { 237 printf("EHCI fail to reset\n"); 238 goto out; 239 } 240 241 if (ehci_is_TDI()) { 242 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE); 243 tmp = ehci_readl(reg_ptr); 244 tmp |= USBMODE_CM_HC; 245 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 246 tmp |= USBMODE_BE; 247 #endif 248 ehci_writel(reg_ptr, tmp); 249 } 250 out: 251 return ret; 252 } 253 254 static void *ehci_alloc(size_t sz, size_t align) 255 { 256 static struct QH qh __attribute__((aligned(32))); 257 static struct qTD td[3] __attribute__((aligned (32))); 258 static int ntds; 259 void *p; 260 261 switch (sz) { 262 case sizeof(struct QH): 263 p = &qh; 264 ntds = 0; 265 break; 266 case sizeof(struct qTD): 267 if (ntds == 3) { 268 debug("out of TDs\n"); 269 return NULL; 270 } 271 p = &td[ntds]; 272 ntds++; 273 break; 274 default: 275 debug("unknown allocation size\n"); 276 return NULL; 277 } 278 279 memset(p, 0, sz); 280 return p; 281 } 282 283 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 284 { 285 uint32_t addr, delta, next; 286 int idx; 287 288 addr = (uint32_t) buf; 289 idx = 0; 290 while (idx < 5) { 291 td->qt_buffer[idx] = cpu_to_hc32(addr); 292 td->qt_buffer_hi[idx] = 0; 293 next = (addr + 4096) & ~4095; 294 delta = next - addr; 295 if (delta >= sz) 296 break; 297 sz -= delta; 298 addr = next; 299 idx++; 300 } 301 302 if (idx == 5) { 303 debug("out of buffer pointers (%u bytes left)\n", sz); 304 return -1; 305 } 306 307 return 0; 308 } 309 310 static int 311 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 312 int length, struct devrequest *req) 313 { 314 struct QH *qh; 315 struct qTD *td; 316 volatile struct qTD *vtd; 317 unsigned long ts; 318 uint32_t *tdp; 319 uint32_t endpt, token, usbsts; 320 uint32_t c, toggle; 321 uint32_t cmd; 322 int timeout; 323 int ret = 0; 324 325 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 326 buffer, length, req); 327 if (req != NULL) 328 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 329 req->request, req->request, 330 req->requesttype, req->requesttype, 331 le16_to_cpu(req->value), le16_to_cpu(req->value), 332 le16_to_cpu(req->index)); 333 334 qh = ehci_alloc(sizeof(struct QH), 32); 335 if (qh == NULL) { 336 debug("unable to allocate QH\n"); 337 return -1; 338 } 339 qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 340 c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && 341 usb_pipeendpoint(pipe) == 0) ? 1 : 0; 342 endpt = (8 << 28) | 343 (c << 27) | 344 (usb_maxpacket(dev, pipe) << 16) | 345 (0 << 15) | 346 (1 << 14) | 347 (usb_pipespeed(pipe) << 12) | 348 (usb_pipeendpoint(pipe) << 8) | 349 (0 << 7) | (usb_pipedevice(pipe) << 0); 350 qh->qh_endpt1 = cpu_to_hc32(endpt); 351 endpt = (1 << 30) | 352 (dev->portnr << 23) | 353 (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); 354 qh->qh_endpt2 = cpu_to_hc32(endpt); 355 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 356 357 td = NULL; 358 tdp = &qh->qh_overlay.qt_next; 359 360 toggle = 361 usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 362 363 if (req != NULL) { 364 td = ehci_alloc(sizeof(struct qTD), 32); 365 if (td == NULL) { 366 debug("unable to allocate SETUP td\n"); 367 goto fail; 368 } 369 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 370 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 371 token = (0 << 31) | 372 (sizeof(*req) << 16) | 373 (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); 374 td->qt_token = cpu_to_hc32(token); 375 if (ehci_td_buffer(td, req, sizeof(*req)) != 0) { 376 debug("unable construct SETUP td\n"); 377 ehci_free(td, sizeof(*td)); 378 goto fail; 379 } 380 *tdp = cpu_to_hc32((uint32_t) td); 381 tdp = &td->qt_next; 382 toggle = 1; 383 } 384 385 if (length > 0 || req == NULL) { 386 td = ehci_alloc(sizeof(struct qTD), 32); 387 if (td == NULL) { 388 debug("unable to allocate DATA td\n"); 389 goto fail; 390 } 391 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 392 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 393 token = (toggle << 31) | 394 (length << 16) | 395 ((req == NULL ? 1 : 0) << 15) | 396 (0 << 12) | 397 (3 << 10) | 398 ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); 399 td->qt_token = cpu_to_hc32(token); 400 if (ehci_td_buffer(td, buffer, length) != 0) { 401 debug("unable construct DATA td\n"); 402 ehci_free(td, sizeof(*td)); 403 goto fail; 404 } 405 *tdp = cpu_to_hc32((uint32_t) td); 406 tdp = &td->qt_next; 407 } 408 409 if (req != NULL) { 410 td = ehci_alloc(sizeof(struct qTD), 32); 411 if (td == NULL) { 412 debug("unable to allocate ACK td\n"); 413 goto fail; 414 } 415 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 416 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 417 token = (toggle << 31) | 418 (0 << 16) | 419 (1 << 15) | 420 (0 << 12) | 421 (3 << 10) | 422 ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); 423 td->qt_token = cpu_to_hc32(token); 424 *tdp = cpu_to_hc32((uint32_t) td); 425 tdp = &td->qt_next; 426 } 427 428 qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH); 429 430 /* Flush dcache */ 431 ehci_flush_dcache(&qh_list); 432 433 usbsts = ehci_readl(&hcor->or_usbsts); 434 ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); 435 436 /* Enable async. schedule. */ 437 cmd = ehci_readl(&hcor->or_usbcmd); 438 cmd |= CMD_ASE; 439 ehci_writel(&hcor->or_usbcmd, cmd); 440 441 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS, 442 100 * 1000); 443 if (ret < 0) { 444 printf("EHCI fail timeout STD_ASS set\n"); 445 goto fail; 446 } 447 448 /* Wait for TDs to be processed. */ 449 ts = get_timer(0); 450 vtd = td; 451 timeout = USB_TIMEOUT_MS(pipe); 452 do { 453 /* Invalidate dcache */ 454 ehci_invalidate_dcache(&qh_list); 455 token = hc32_to_cpu(vtd->qt_token); 456 if (!(token & 0x80)) 457 break; 458 WATCHDOG_RESET(); 459 } while (get_timer(ts) < timeout); 460 461 /* Check that the TD processing happened */ 462 if (token & 0x80) { 463 printf("EHCI timed out on TD - token=%#x\n", token); 464 } 465 466 /* Disable async schedule. */ 467 cmd = ehci_readl(&hcor->or_usbcmd); 468 cmd &= ~CMD_ASE; 469 ehci_writel(&hcor->or_usbcmd, cmd); 470 471 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0, 472 100 * 1000); 473 if (ret < 0) { 474 printf("EHCI fail timeout STD_ASS reset\n"); 475 goto fail; 476 } 477 478 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 479 480 token = hc32_to_cpu(qh->qh_overlay.qt_token); 481 if (!(token & 0x80)) { 482 debug("TOKEN=%#x\n", token); 483 switch (token & 0xfc) { 484 case 0: 485 toggle = token >> 31; 486 usb_settoggle(dev, usb_pipeendpoint(pipe), 487 usb_pipeout(pipe), toggle); 488 dev->status = 0; 489 break; 490 case 0x40: 491 dev->status = USB_ST_STALLED; 492 break; 493 case 0xa0: 494 case 0x20: 495 dev->status = USB_ST_BUF_ERR; 496 break; 497 case 0x50: 498 case 0x10: 499 dev->status = USB_ST_BABBLE_DET; 500 break; 501 default: 502 dev->status = USB_ST_CRC_ERR; 503 if ((token & 0x40) == 0x40) 504 dev->status |= USB_ST_STALLED; 505 break; 506 } 507 dev->act_len = length - ((token >> 16) & 0x7fff); 508 } else { 509 dev->act_len = 0; 510 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 511 dev->devnum, ehci_readl(&hcor->or_usbsts), 512 ehci_readl(&hcor->or_portsc[0]), 513 ehci_readl(&hcor->or_portsc[1])); 514 } 515 516 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 517 518 fail: 519 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 520 while (td != (void *)QT_NEXT_TERMINATE) { 521 qh->qh_overlay.qt_next = td->qt_next; 522 ehci_free(td, sizeof(*td)); 523 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); 524 } 525 ehci_free(qh, sizeof(*qh)); 526 return -1; 527 } 528 529 static inline int min3(int a, int b, int c) 530 { 531 532 if (b < a) 533 a = b; 534 if (c < a) 535 a = c; 536 return a; 537 } 538 539 int 540 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, 541 int length, struct devrequest *req) 542 { 543 uint8_t tmpbuf[4]; 544 u16 typeReq; 545 void *srcptr = NULL; 546 int len, srclen; 547 uint32_t reg; 548 uint32_t *status_reg; 549 550 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 551 printf("The request port(%d) is not configured\n", 552 le16_to_cpu(req->index) - 1); 553 return -1; 554 } 555 status_reg = (uint32_t *)&hcor->or_portsc[ 556 le16_to_cpu(req->index) - 1]; 557 srclen = 0; 558 559 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 560 req->request, req->request, 561 req->requesttype, req->requesttype, 562 le16_to_cpu(req->value), le16_to_cpu(req->index)); 563 564 typeReq = req->request | req->requesttype << 8; 565 566 switch (typeReq) { 567 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 568 switch (le16_to_cpu(req->value) >> 8) { 569 case USB_DT_DEVICE: 570 debug("USB_DT_DEVICE request\n"); 571 srcptr = &descriptor.device; 572 srclen = 0x12; 573 break; 574 case USB_DT_CONFIG: 575 debug("USB_DT_CONFIG config\n"); 576 srcptr = &descriptor.config; 577 srclen = 0x19; 578 break; 579 case USB_DT_STRING: 580 debug("USB_DT_STRING config\n"); 581 switch (le16_to_cpu(req->value) & 0xff) { 582 case 0: /* Language */ 583 srcptr = "\4\3\1\0"; 584 srclen = 4; 585 break; 586 case 1: /* Vendor */ 587 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 588 srclen = 14; 589 break; 590 case 2: /* Product */ 591 srcptr = "\52\3E\0H\0C\0I\0 " 592 "\0H\0o\0s\0t\0 " 593 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 594 srclen = 42; 595 break; 596 default: 597 debug("unknown value DT_STRING %x\n", 598 le16_to_cpu(req->value)); 599 goto unknown; 600 } 601 break; 602 default: 603 debug("unknown value %x\n", le16_to_cpu(req->value)); 604 goto unknown; 605 } 606 break; 607 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 608 switch (le16_to_cpu(req->value) >> 8) { 609 case USB_DT_HUB: 610 debug("USB_DT_HUB config\n"); 611 srcptr = &descriptor.hub; 612 srclen = 0x8; 613 break; 614 default: 615 debug("unknown value %x\n", le16_to_cpu(req->value)); 616 goto unknown; 617 } 618 break; 619 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 620 debug("USB_REQ_SET_ADDRESS\n"); 621 rootdev = le16_to_cpu(req->value); 622 break; 623 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 624 debug("USB_REQ_SET_CONFIGURATION\n"); 625 /* Nothing to do */ 626 break; 627 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 628 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 629 tmpbuf[1] = 0; 630 srcptr = tmpbuf; 631 srclen = 2; 632 break; 633 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 634 memset(tmpbuf, 0, 4); 635 reg = ehci_readl(status_reg); 636 if (reg & EHCI_PS_CS) 637 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 638 if (reg & EHCI_PS_PE) 639 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 640 if (reg & EHCI_PS_SUSP) 641 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 642 if (reg & EHCI_PS_OCA) 643 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 644 if (reg & EHCI_PS_PR) 645 tmpbuf[0] |= USB_PORT_STAT_RESET; 646 if (reg & EHCI_PS_PP) 647 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 648 649 if (ehci_is_TDI()) { 650 switch ((reg >> 26) & 3) { 651 case 0: 652 break; 653 case 1: 654 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 655 break; 656 case 2: 657 default: 658 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 659 break; 660 } 661 } else { 662 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 663 } 664 665 if (reg & EHCI_PS_CSC) 666 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 667 if (reg & EHCI_PS_PEC) 668 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 669 if (reg & EHCI_PS_OCC) 670 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 671 if (portreset & (1 << le16_to_cpu(req->index))) 672 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 673 674 srcptr = tmpbuf; 675 srclen = 4; 676 break; 677 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 678 reg = ehci_readl(status_reg); 679 reg &= ~EHCI_PS_CLEAR; 680 switch (le16_to_cpu(req->value)) { 681 case USB_PORT_FEAT_ENABLE: 682 reg |= EHCI_PS_PE; 683 ehci_writel(status_reg, reg); 684 break; 685 case USB_PORT_FEAT_POWER: 686 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) { 687 reg |= EHCI_PS_PP; 688 ehci_writel(status_reg, reg); 689 } 690 break; 691 case USB_PORT_FEAT_RESET: 692 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 693 !ehci_is_TDI() && 694 EHCI_PS_IS_LOWSPEED(reg)) { 695 /* Low speed device, give up ownership. */ 696 debug("port %d low speed --> companion\n", 697 req->index - 1); 698 reg |= EHCI_PS_PO; 699 ehci_writel(status_reg, reg); 700 break; 701 } else { 702 int ret; 703 704 reg |= EHCI_PS_PR; 705 reg &= ~EHCI_PS_PE; 706 ehci_writel(status_reg, reg); 707 /* 708 * caller must wait, then call GetPortStatus 709 * usb 2.0 specification say 50 ms resets on 710 * root 711 */ 712 wait_ms(50); 713 /* terminate the reset */ 714 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 715 /* 716 * A host controller must terminate the reset 717 * and stabilize the state of the port within 718 * 2 milliseconds 719 */ 720 ret = handshake(status_reg, EHCI_PS_PR, 0, 721 2 * 1000); 722 if (!ret) 723 portreset |= 724 1 << le16_to_cpu(req->index); 725 else 726 printf("port(%d) reset error\n", 727 le16_to_cpu(req->index) - 1); 728 } 729 break; 730 default: 731 debug("unknown feature %x\n", le16_to_cpu(req->value)); 732 goto unknown; 733 } 734 /* unblock posted writes */ 735 (void) ehci_readl(&hcor->or_usbcmd); 736 break; 737 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 738 reg = ehci_readl(status_reg); 739 switch (le16_to_cpu(req->value)) { 740 case USB_PORT_FEAT_ENABLE: 741 reg &= ~EHCI_PS_PE; 742 break; 743 case USB_PORT_FEAT_C_ENABLE: 744 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE; 745 break; 746 case USB_PORT_FEAT_POWER: 747 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) 748 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP); 749 case USB_PORT_FEAT_C_CONNECTION: 750 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC; 751 break; 752 case USB_PORT_FEAT_OVER_CURRENT: 753 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; 754 break; 755 case USB_PORT_FEAT_C_RESET: 756 portreset &= ~(1 << le16_to_cpu(req->index)); 757 break; 758 default: 759 debug("unknown feature %x\n", le16_to_cpu(req->value)); 760 goto unknown; 761 } 762 ehci_writel(status_reg, reg); 763 /* unblock posted write */ 764 (void) ehci_readl(&hcor->or_usbcmd); 765 break; 766 default: 767 debug("Unknown request\n"); 768 goto unknown; 769 } 770 771 wait_ms(1); 772 len = min3(srclen, le16_to_cpu(req->length), length); 773 if (srcptr != NULL && len > 0) 774 memcpy(buffer, srcptr, len); 775 else 776 debug("Len is 0\n"); 777 778 dev->act_len = len; 779 dev->status = 0; 780 return 0; 781 782 unknown: 783 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 784 req->requesttype, req->request, le16_to_cpu(req->value), 785 le16_to_cpu(req->index), le16_to_cpu(req->length)); 786 787 dev->act_len = 0; 788 dev->status = USB_ST_STALLED; 789 return -1; 790 } 791 792 int usb_lowlevel_stop(void) 793 { 794 return ehci_hcd_stop(); 795 } 796 797 int usb_lowlevel_init(void) 798 { 799 uint32_t reg; 800 uint32_t cmd; 801 802 if (ehci_hcd_init() != 0) 803 return -1; 804 805 /* EHCI spec section 4.1 */ 806 if (ehci_reset() != 0) 807 return -1; 808 809 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 810 if (ehci_hcd_init() != 0) 811 return -1; 812 #endif 813 814 /* Set head of reclaim list */ 815 memset(&qh_list, 0, sizeof(qh_list)); 816 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); 817 qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); 818 qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); 819 qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 820 qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 821 qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40); 822 823 /* Set async. queue head pointer. */ 824 ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list); 825 826 reg = ehci_readl(&hccr->cr_hcsparams); 827 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 828 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 829 /* Port Indicators */ 830 if (HCS_INDICATOR(reg)) 831 descriptor.hub.wHubCharacteristics |= 0x80; 832 /* Port Power Control */ 833 if (HCS_PPC(reg)) 834 descriptor.hub.wHubCharacteristics |= 0x01; 835 836 /* Start the host controller. */ 837 cmd = ehci_readl(&hcor->or_usbcmd); 838 /* 839 * Philips, Intel, and maybe others need CMD_RUN before the 840 * root hub will detect new devices (why?); NEC doesn't 841 */ 842 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 843 cmd |= CMD_RUN; 844 ehci_writel(&hcor->or_usbcmd, cmd); 845 846 /* take control over the ports */ 847 cmd = ehci_readl(&hcor->or_configflag); 848 cmd |= FLAG_CF; 849 ehci_writel(&hcor->or_configflag, cmd); 850 /* unblock posted write */ 851 cmd = ehci_readl(&hcor->or_usbcmd); 852 wait_ms(5); 853 reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); 854 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 855 856 rootdev = 0; 857 858 return 0; 859 } 860 861 int 862 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 863 int length) 864 { 865 866 if (usb_pipetype(pipe) != PIPE_BULK) { 867 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 868 return -1; 869 } 870 return ehci_submit_async(dev, pipe, buffer, length, NULL); 871 } 872 873 int 874 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 875 int length, struct devrequest *setup) 876 { 877 878 if (usb_pipetype(pipe) != PIPE_CONTROL) { 879 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 880 return -1; 881 } 882 883 if (usb_pipedevice(pipe) == rootdev) { 884 if (rootdev == 0) 885 dev->speed = USB_SPEED_HIGH; 886 return ehci_submit_root(dev, pipe, buffer, length, setup); 887 } 888 return ehci_submit_async(dev, pipe, buffer, length, setup); 889 } 890 891 int 892 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 893 int length, int interval) 894 { 895 896 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 897 dev, pipe, buffer, length, interval); 898 return -1; 899 } 900