1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <errno.h> 25 #include <asm/byteorder.h> 26 #include <asm/unaligned.h> 27 #include <usb.h> 28 #include <asm/io.h> 29 #include <malloc.h> 30 #include <watchdog.h> 31 #include <linux/compiler.h> 32 33 #include "ehci.h" 34 35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 37 #endif 38 39 /* 40 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. 41 * Let's time out after 8 to have a little safety margin on top of that. 42 */ 43 #define HCHALT_TIMEOUT (8 * 1000) 44 45 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; 46 47 #define ALIGN_END_ADDR(type, ptr, size) \ 48 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) 49 50 static struct descriptor { 51 struct usb_hub_descriptor hub; 52 struct usb_device_descriptor device; 53 struct usb_linux_config_descriptor config; 54 struct usb_linux_interface_descriptor interface; 55 struct usb_endpoint_descriptor endpoint; 56 } __attribute__ ((packed)) descriptor = { 57 { 58 0x8, /* bDescLength */ 59 0x29, /* bDescriptorType: hub descriptor */ 60 2, /* bNrPorts -- runtime modified */ 61 0, /* wHubCharacteristics */ 62 10, /* bPwrOn2PwrGood */ 63 0, /* bHubCntrCurrent */ 64 {}, /* Device removable */ 65 {} /* at most 7 ports! XXX */ 66 }, 67 { 68 0x12, /* bLength */ 69 1, /* bDescriptorType: UDESC_DEVICE */ 70 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 71 9, /* bDeviceClass: UDCLASS_HUB */ 72 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 73 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 74 64, /* bMaxPacketSize: 64 bytes */ 75 0x0000, /* idVendor */ 76 0x0000, /* idProduct */ 77 cpu_to_le16(0x0100), /* bcdDevice */ 78 1, /* iManufacturer */ 79 2, /* iProduct */ 80 0, /* iSerialNumber */ 81 1 /* bNumConfigurations: 1 */ 82 }, 83 { 84 0x9, 85 2, /* bDescriptorType: UDESC_CONFIG */ 86 cpu_to_le16(0x19), 87 1, /* bNumInterface */ 88 1, /* bConfigurationValue */ 89 0, /* iConfiguration */ 90 0x40, /* bmAttributes: UC_SELF_POWER */ 91 0 /* bMaxPower */ 92 }, 93 { 94 0x9, /* bLength */ 95 4, /* bDescriptorType: UDESC_INTERFACE */ 96 0, /* bInterfaceNumber */ 97 0, /* bAlternateSetting */ 98 1, /* bNumEndpoints */ 99 9, /* bInterfaceClass: UICLASS_HUB */ 100 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 101 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 102 0 /* iInterface */ 103 }, 104 { 105 0x7, /* bLength */ 106 5, /* bDescriptorType: UDESC_ENDPOINT */ 107 0x81, /* bEndpointAddress: 108 * UE_DIR_IN | EHCI_INTR_ENDPT 109 */ 110 3, /* bmAttributes: UE_INTERRUPT */ 111 8, /* wMaxPacketSize */ 112 255 /* bInterval */ 113 }, 114 }; 115 116 #if defined(CONFIG_EHCI_IS_TDI) 117 #define ehci_is_TDI() (1) 118 #else 119 #define ehci_is_TDI() (0) 120 #endif 121 122 int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) 123 { 124 return PORTSC_PSPD(reg); 125 } 126 127 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) 128 __attribute__((weak, alias("__ehci_get_port_speed"))); 129 130 void __ehci_set_usbmode(int index) 131 { 132 uint32_t tmp; 133 uint32_t *reg_ptr; 134 135 reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE); 136 tmp = ehci_readl(reg_ptr); 137 tmp |= USBMODE_CM_HC; 138 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 139 tmp |= USBMODE_BE; 140 #endif 141 ehci_writel(reg_ptr, tmp); 142 } 143 144 void ehci_set_usbmode(int index) 145 __attribute__((weak, alias("__ehci_set_usbmode"))); 146 147 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 148 { 149 mdelay(50); 150 } 151 152 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 153 __attribute__((weak, alias("__ehci_powerup_fixup"))); 154 155 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 156 { 157 uint32_t result; 158 do { 159 result = ehci_readl(ptr); 160 udelay(5); 161 if (result == ~(uint32_t)0) 162 return -1; 163 result &= mask; 164 if (result == done) 165 return 0; 166 usec--; 167 } while (usec > 0); 168 return -1; 169 } 170 171 static int ehci_reset(int index) 172 { 173 uint32_t cmd; 174 int ret = 0; 175 176 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd); 177 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 178 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd); 179 ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd, 180 CMD_RESET, 0, 250 * 1000); 181 if (ret < 0) { 182 printf("EHCI fail to reset\n"); 183 goto out; 184 } 185 186 if (ehci_is_TDI()) 187 ehci_set_usbmode(index); 188 189 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH 190 cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning); 191 cmd &= ~TXFIFO_THRESH_MASK; 192 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); 193 ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd); 194 #endif 195 out: 196 return ret; 197 } 198 199 static int ehci_shutdown(struct ehci_ctrl *ctrl) 200 { 201 int i, ret = 0; 202 uint32_t cmd, reg; 203 204 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 205 cmd &= ~(CMD_PSE | CMD_ASE); 206 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 207 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0, 208 100 * 1000); 209 210 if (!ret) { 211 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) { 212 reg = ehci_readl(&ctrl->hcor->or_portsc[i]); 213 reg |= EHCI_PS_SUSP; 214 ehci_writel(&ctrl->hcor->or_portsc[i], reg); 215 } 216 217 cmd &= ~CMD_RUN; 218 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 219 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT, 220 HCHALT_TIMEOUT); 221 } 222 223 if (ret) 224 puts("EHCI failed to shut down host controller.\n"); 225 226 return ret; 227 } 228 229 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 230 { 231 uint32_t delta, next; 232 uint32_t addr = (uint32_t)buf; 233 int idx; 234 235 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) 236 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); 237 238 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); 239 240 idx = 0; 241 while (idx < QT_BUFFER_CNT) { 242 td->qt_buffer[idx] = cpu_to_hc32(addr); 243 td->qt_buffer_hi[idx] = 0; 244 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); 245 delta = next - addr; 246 if (delta >= sz) 247 break; 248 sz -= delta; 249 addr = next; 250 idx++; 251 } 252 253 if (idx == QT_BUFFER_CNT) { 254 printf("out of buffer pointers (%u bytes left)\n", sz); 255 return -1; 256 } 257 258 return 0; 259 } 260 261 static inline u8 ehci_encode_speed(enum usb_device_speed speed) 262 { 263 #define QH_HIGH_SPEED 2 264 #define QH_FULL_SPEED 0 265 #define QH_LOW_SPEED 1 266 if (speed == USB_SPEED_HIGH) 267 return QH_HIGH_SPEED; 268 if (speed == USB_SPEED_LOW) 269 return QH_LOW_SPEED; 270 return QH_FULL_SPEED; 271 } 272 273 static int 274 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 275 int length, struct devrequest *req) 276 { 277 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); 278 struct qTD *qtd; 279 int qtd_count = 0; 280 int qtd_counter = 0; 281 volatile struct qTD *vtd; 282 unsigned long ts; 283 uint32_t *tdp; 284 uint32_t endpt, maxpacket, token, usbsts; 285 uint32_t c, toggle; 286 uint32_t cmd; 287 int timeout; 288 int ret = 0; 289 struct ehci_ctrl *ctrl = dev->controller; 290 291 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 292 buffer, length, req); 293 if (req != NULL) 294 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 295 req->request, req->request, 296 req->requesttype, req->requesttype, 297 le16_to_cpu(req->value), le16_to_cpu(req->value), 298 le16_to_cpu(req->index)); 299 300 #define PKT_ALIGN 512 301 /* 302 * The USB transfer is split into qTD transfers. Eeach qTD transfer is 303 * described by a transfer descriptor (the qTD). The qTDs form a linked 304 * list with a queue head (QH). 305 * 306 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot 307 * have its beginning in a qTD transfer and its end in the following 308 * one, so the qTD transfer lengths have to be chosen accordingly. 309 * 310 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to 311 * single pages. The first data buffer can start at any offset within a 312 * page (not considering the cache-line alignment issues), while the 313 * following buffers must be page-aligned. There is no alignment 314 * constraint on the size of a qTD transfer. 315 */ 316 if (req != NULL) 317 /* 1 qTD will be needed for SETUP, and 1 for ACK. */ 318 qtd_count += 1 + 1; 319 if (length > 0 || req == NULL) { 320 /* 321 * Determine the qTD transfer size that will be used for the 322 * data payload (not considering the first qTD transfer, which 323 * may be longer or shorter, and the final one, which may be 324 * shorter). 325 * 326 * In order to keep each packet within a qTD transfer, the qTD 327 * transfer size is aligned to PKT_ALIGN, which is a multiple of 328 * wMaxPacketSize (except in some cases for interrupt transfers, 329 * see comment in submit_int_msg()). 330 * 331 * By default, i.e. if the input buffer is aligned to PKT_ALIGN, 332 * QT_BUFFER_CNT full pages will be used. 333 */ 334 int xfr_sz = QT_BUFFER_CNT; 335 /* 336 * However, if the input buffer is not aligned to PKT_ALIGN, the 337 * qTD transfer size will be one page shorter, and the first qTD 338 * data buffer of each transfer will be page-unaligned. 339 */ 340 if ((uint32_t)buffer & (PKT_ALIGN - 1)) 341 xfr_sz--; 342 /* Convert the qTD transfer size to bytes. */ 343 xfr_sz *= EHCI_PAGE_SIZE; 344 /* 345 * Approximate by excess the number of qTDs that will be 346 * required for the data payload. The exact formula is way more 347 * complicated and saves at most 2 qTDs, i.e. a total of 128 348 * bytes. 349 */ 350 qtd_count += 2 + length / xfr_sz; 351 } 352 /* 353 * Threshold value based on the worst-case total size of the allocated qTDs for 354 * a mass-storage transfer of 65535 blocks of 512 bytes. 355 */ 356 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024 357 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI 358 #endif 359 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); 360 if (qtd == NULL) { 361 printf("unable to allocate TDs\n"); 362 return -1; 363 } 364 365 memset(qh, 0, sizeof(struct QH)); 366 memset(qtd, 0, qtd_count * sizeof(*qtd)); 367 368 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 369 370 /* 371 * Setup QH (3.6 in ehci-r10.pdf) 372 * 373 * qh_link ................. 03-00 H 374 * qh_endpt1 ............... 07-04 H 375 * qh_endpt2 ............... 0B-08 H 376 * - qh_curtd 377 * qh_overlay.qt_next ...... 13-10 H 378 * - qh_overlay.qt_altnext 379 */ 380 qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH); 381 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe); 382 maxpacket = usb_maxpacket(dev, pipe); 383 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | 384 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | 385 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | 386 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 387 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | 388 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); 389 qh->qh_endpt1 = cpu_to_hc32(endpt); 390 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) | 391 QH_ENDPT2_HUBADDR(dev->parent->devnum) | 392 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); 393 qh->qh_endpt2 = cpu_to_hc32(endpt); 394 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 395 396 tdp = &qh->qh_overlay.qt_next; 397 398 if (req != NULL) { 399 /* 400 * Setup request qTD (3.5 in ehci-r10.pdf) 401 * 402 * qt_next ................ 03-00 H 403 * qt_altnext ............. 07-04 H 404 * qt_token ............... 0B-08 H 405 * 406 * [ buffer, buffer_hi ] loaded with "req". 407 */ 408 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 409 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 410 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) | 411 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 412 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) | 413 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 414 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 415 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) { 416 printf("unable to construct SETUP TD\n"); 417 goto fail; 418 } 419 /* Update previous qTD! */ 420 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 421 tdp = &qtd[qtd_counter++].qt_next; 422 toggle = 1; 423 } 424 425 if (length > 0 || req == NULL) { 426 uint8_t *buf_ptr = buffer; 427 int left_length = length; 428 429 do { 430 /* 431 * Determine the size of this qTD transfer. By default, 432 * QT_BUFFER_CNT full pages can be used. 433 */ 434 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE; 435 /* 436 * However, if the input buffer is not page-aligned, the 437 * portion of the first page before the buffer start 438 * offset within that page is unusable. 439 */ 440 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1); 441 /* 442 * In order to keep each packet within a qTD transfer, 443 * align the qTD transfer size to PKT_ALIGN. 444 */ 445 xfr_bytes &= ~(PKT_ALIGN - 1); 446 /* 447 * This transfer may be shorter than the available qTD 448 * transfer size that has just been computed. 449 */ 450 xfr_bytes = min(xfr_bytes, left_length); 451 452 /* 453 * Setup request qTD (3.5 in ehci-r10.pdf) 454 * 455 * qt_next ................ 03-00 H 456 * qt_altnext ............. 07-04 H 457 * qt_token ............... 0B-08 H 458 * 459 * [ buffer, buffer_hi ] loaded with "buffer". 460 */ 461 qtd[qtd_counter].qt_next = 462 cpu_to_hc32(QT_NEXT_TERMINATE); 463 qtd[qtd_counter].qt_altnext = 464 cpu_to_hc32(QT_NEXT_TERMINATE); 465 token = QT_TOKEN_DT(toggle) | 466 QT_TOKEN_TOTALBYTES(xfr_bytes) | 467 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) | 468 QT_TOKEN_CERR(3) | 469 QT_TOKEN_PID(usb_pipein(pipe) ? 470 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) | 471 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 472 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 473 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr, 474 xfr_bytes)) { 475 printf("unable to construct DATA TD\n"); 476 goto fail; 477 } 478 /* Update previous qTD! */ 479 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 480 tdp = &qtd[qtd_counter++].qt_next; 481 /* 482 * Data toggle has to be adjusted since the qTD transfer 483 * size is not always an even multiple of 484 * wMaxPacketSize. 485 */ 486 if ((xfr_bytes / maxpacket) & 1) 487 toggle ^= 1; 488 buf_ptr += xfr_bytes; 489 left_length -= xfr_bytes; 490 } while (left_length > 0); 491 } 492 493 if (req != NULL) { 494 /* 495 * Setup request qTD (3.5 in ehci-r10.pdf) 496 * 497 * qt_next ................ 03-00 H 498 * qt_altnext ............. 07-04 H 499 * qt_token ............... 0B-08 H 500 */ 501 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 502 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 503 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) | 504 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 505 QT_TOKEN_PID(usb_pipein(pipe) ? 506 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) | 507 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 508 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 509 /* Update previous qTD! */ 510 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 511 tdp = &qtd[qtd_counter++].qt_next; 512 } 513 514 ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH); 515 516 /* Flush dcache */ 517 flush_dcache_range((uint32_t)&ctrl->qh_list, 518 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 519 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); 520 flush_dcache_range((uint32_t)qtd, 521 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 522 523 /* Set async. queue head pointer. */ 524 ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list); 525 526 usbsts = ehci_readl(&ctrl->hcor->or_usbsts); 527 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); 528 529 /* Enable async. schedule. */ 530 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 531 cmd |= CMD_ASE; 532 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 533 534 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, 535 100 * 1000); 536 if (ret < 0) { 537 printf("EHCI fail timeout STS_ASS set\n"); 538 goto fail; 539 } 540 541 /* Wait for TDs to be processed. */ 542 ts = get_timer(0); 543 vtd = &qtd[qtd_counter - 1]; 544 timeout = USB_TIMEOUT_MS(pipe); 545 do { 546 /* Invalidate dcache */ 547 invalidate_dcache_range((uint32_t)&ctrl->qh_list, 548 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 549 invalidate_dcache_range((uint32_t)qh, 550 ALIGN_END_ADDR(struct QH, qh, 1)); 551 invalidate_dcache_range((uint32_t)qtd, 552 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 553 554 token = hc32_to_cpu(vtd->qt_token); 555 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) 556 break; 557 WATCHDOG_RESET(); 558 } while (get_timer(ts) < timeout); 559 560 /* 561 * Invalidate the memory area occupied by buffer 562 * Don't try to fix the buffer alignment, if it isn't properly 563 * aligned it's upper layer's fault so let invalidate_dcache_range() 564 * vow about it. But we have to fix the length as it's actual 565 * transfer length and can be unaligned. This is potentially 566 * dangerous operation, it's responsibility of the calling 567 * code to make sure enough space is reserved. 568 */ 569 invalidate_dcache_range((uint32_t)buffer, 570 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN)); 571 572 /* Check that the TD processing happened */ 573 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) 574 printf("EHCI timed out on TD - token=%#x\n", token); 575 576 /* Disable async schedule. */ 577 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 578 cmd &= ~CMD_ASE; 579 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 580 581 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0, 582 100 * 1000); 583 if (ret < 0) { 584 printf("EHCI fail timeout STS_ASS reset\n"); 585 goto fail; 586 } 587 588 token = hc32_to_cpu(qh->qh_overlay.qt_token); 589 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) { 590 debug("TOKEN=%#x\n", token); 591 switch (QT_TOKEN_GET_STATUS(token) & 592 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { 593 case 0: 594 toggle = QT_TOKEN_GET_DT(token); 595 usb_settoggle(dev, usb_pipeendpoint(pipe), 596 usb_pipeout(pipe), toggle); 597 dev->status = 0; 598 break; 599 case QT_TOKEN_STATUS_HALTED: 600 dev->status = USB_ST_STALLED; 601 break; 602 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: 603 case QT_TOKEN_STATUS_DATBUFERR: 604 dev->status = USB_ST_BUF_ERR; 605 break; 606 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: 607 case QT_TOKEN_STATUS_BABBLEDET: 608 dev->status = USB_ST_BABBLE_DET; 609 break; 610 default: 611 dev->status = USB_ST_CRC_ERR; 612 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED) 613 dev->status |= USB_ST_STALLED; 614 break; 615 } 616 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token); 617 } else { 618 dev->act_len = 0; 619 #ifndef CONFIG_USB_EHCI_FARADAY 620 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 621 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), 622 ehci_readl(&ctrl->hcor->or_portsc[0]), 623 ehci_readl(&ctrl->hcor->or_portsc[1])); 624 #endif 625 } 626 627 free(qtd); 628 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 629 630 fail: 631 free(qtd); 632 return -1; 633 } 634 635 __weak uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port) 636 { 637 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 638 /* Printing the message would cause a scan failure! */ 639 debug("The request port(%u) is not configured\n", port); 640 return NULL; 641 } 642 643 return (uint32_t *)&hcor->or_portsc[port]; 644 } 645 646 int 647 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, 648 int length, struct devrequest *req) 649 { 650 uint8_t tmpbuf[4]; 651 u16 typeReq; 652 void *srcptr = NULL; 653 int len, srclen; 654 uint32_t reg; 655 uint32_t *status_reg; 656 int port = le16_to_cpu(req->index) & 0xff; 657 struct ehci_ctrl *ctrl = dev->controller; 658 659 srclen = 0; 660 661 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 662 req->request, req->request, 663 req->requesttype, req->requesttype, 664 le16_to_cpu(req->value), le16_to_cpu(req->index)); 665 666 typeReq = req->request | req->requesttype << 8; 667 668 switch (typeReq) { 669 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 670 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 671 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 672 status_reg = ehci_get_portsc_register(ctrl->hcor, port - 1); 673 if (!status_reg) 674 return -1; 675 break; 676 default: 677 status_reg = NULL; 678 break; 679 } 680 681 switch (typeReq) { 682 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 683 switch (le16_to_cpu(req->value) >> 8) { 684 case USB_DT_DEVICE: 685 debug("USB_DT_DEVICE request\n"); 686 srcptr = &descriptor.device; 687 srclen = descriptor.device.bLength; 688 break; 689 case USB_DT_CONFIG: 690 debug("USB_DT_CONFIG config\n"); 691 srcptr = &descriptor.config; 692 srclen = descriptor.config.bLength + 693 descriptor.interface.bLength + 694 descriptor.endpoint.bLength; 695 break; 696 case USB_DT_STRING: 697 debug("USB_DT_STRING config\n"); 698 switch (le16_to_cpu(req->value) & 0xff) { 699 case 0: /* Language */ 700 srcptr = "\4\3\1\0"; 701 srclen = 4; 702 break; 703 case 1: /* Vendor */ 704 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 705 srclen = 14; 706 break; 707 case 2: /* Product */ 708 srcptr = "\52\3E\0H\0C\0I\0 " 709 "\0H\0o\0s\0t\0 " 710 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 711 srclen = 42; 712 break; 713 default: 714 debug("unknown value DT_STRING %x\n", 715 le16_to_cpu(req->value)); 716 goto unknown; 717 } 718 break; 719 default: 720 debug("unknown value %x\n", le16_to_cpu(req->value)); 721 goto unknown; 722 } 723 break; 724 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 725 switch (le16_to_cpu(req->value) >> 8) { 726 case USB_DT_HUB: 727 debug("USB_DT_HUB config\n"); 728 srcptr = &descriptor.hub; 729 srclen = descriptor.hub.bLength; 730 break; 731 default: 732 debug("unknown value %x\n", le16_to_cpu(req->value)); 733 goto unknown; 734 } 735 break; 736 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 737 debug("USB_REQ_SET_ADDRESS\n"); 738 ctrl->rootdev = le16_to_cpu(req->value); 739 break; 740 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 741 debug("USB_REQ_SET_CONFIGURATION\n"); 742 /* Nothing to do */ 743 break; 744 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 745 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 746 tmpbuf[1] = 0; 747 srcptr = tmpbuf; 748 srclen = 2; 749 break; 750 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 751 memset(tmpbuf, 0, 4); 752 reg = ehci_readl(status_reg); 753 if (reg & EHCI_PS_CS) 754 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 755 if (reg & EHCI_PS_PE) 756 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 757 if (reg & EHCI_PS_SUSP) 758 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 759 if (reg & EHCI_PS_OCA) 760 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 761 if (reg & EHCI_PS_PR) 762 tmpbuf[0] |= USB_PORT_STAT_RESET; 763 if (reg & EHCI_PS_PP) 764 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 765 766 if (ehci_is_TDI()) { 767 switch (ehci_get_port_speed(ctrl->hcor, reg)) { 768 case PORTSC_PSPD_FS: 769 break; 770 case PORTSC_PSPD_LS: 771 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 772 break; 773 case PORTSC_PSPD_HS: 774 default: 775 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 776 break; 777 } 778 } else { 779 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 780 } 781 782 if (reg & EHCI_PS_CSC) 783 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 784 if (reg & EHCI_PS_PEC) 785 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 786 if (reg & EHCI_PS_OCC) 787 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 788 if (ctrl->portreset & (1 << port)) 789 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 790 791 srcptr = tmpbuf; 792 srclen = 4; 793 break; 794 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 795 reg = ehci_readl(status_reg); 796 reg &= ~EHCI_PS_CLEAR; 797 switch (le16_to_cpu(req->value)) { 798 case USB_PORT_FEAT_ENABLE: 799 reg |= EHCI_PS_PE; 800 ehci_writel(status_reg, reg); 801 break; 802 case USB_PORT_FEAT_POWER: 803 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) { 804 reg |= EHCI_PS_PP; 805 ehci_writel(status_reg, reg); 806 } 807 break; 808 case USB_PORT_FEAT_RESET: 809 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 810 !ehci_is_TDI() && 811 EHCI_PS_IS_LOWSPEED(reg)) { 812 /* Low speed device, give up ownership. */ 813 debug("port %d low speed --> companion\n", 814 port - 1); 815 reg |= EHCI_PS_PO; 816 ehci_writel(status_reg, reg); 817 break; 818 } else { 819 int ret; 820 821 reg |= EHCI_PS_PR; 822 reg &= ~EHCI_PS_PE; 823 ehci_writel(status_reg, reg); 824 /* 825 * caller must wait, then call GetPortStatus 826 * usb 2.0 specification say 50 ms resets on 827 * root 828 */ 829 ehci_powerup_fixup(status_reg, ®); 830 831 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 832 /* 833 * A host controller must terminate the reset 834 * and stabilize the state of the port within 835 * 2 milliseconds 836 */ 837 ret = handshake(status_reg, EHCI_PS_PR, 0, 838 2 * 1000); 839 if (!ret) 840 ctrl->portreset |= 1 << port; 841 else 842 printf("port(%d) reset error\n", 843 port - 1); 844 } 845 break; 846 case USB_PORT_FEAT_TEST: 847 ehci_shutdown(ctrl); 848 reg &= ~(0xf << 16); 849 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16; 850 ehci_writel(status_reg, reg); 851 break; 852 default: 853 debug("unknown feature %x\n", le16_to_cpu(req->value)); 854 goto unknown; 855 } 856 /* unblock posted writes */ 857 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 858 break; 859 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 860 reg = ehci_readl(status_reg); 861 reg &= ~EHCI_PS_CLEAR; 862 switch (le16_to_cpu(req->value)) { 863 case USB_PORT_FEAT_ENABLE: 864 reg &= ~EHCI_PS_PE; 865 break; 866 case USB_PORT_FEAT_C_ENABLE: 867 reg |= EHCI_PS_PE; 868 break; 869 case USB_PORT_FEAT_POWER: 870 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) 871 reg &= ~EHCI_PS_PP; 872 break; 873 case USB_PORT_FEAT_C_CONNECTION: 874 reg |= EHCI_PS_CSC; 875 break; 876 case USB_PORT_FEAT_OVER_CURRENT: 877 reg |= EHCI_PS_OCC; 878 break; 879 case USB_PORT_FEAT_C_RESET: 880 ctrl->portreset &= ~(1 << port); 881 break; 882 default: 883 debug("unknown feature %x\n", le16_to_cpu(req->value)); 884 goto unknown; 885 } 886 ehci_writel(status_reg, reg); 887 /* unblock posted write */ 888 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 889 break; 890 default: 891 debug("Unknown request\n"); 892 goto unknown; 893 } 894 895 mdelay(1); 896 len = min3(srclen, le16_to_cpu(req->length), length); 897 if (srcptr != NULL && len > 0) 898 memcpy(buffer, srcptr, len); 899 else 900 debug("Len is 0\n"); 901 902 dev->act_len = len; 903 dev->status = 0; 904 return 0; 905 906 unknown: 907 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 908 req->requesttype, req->request, le16_to_cpu(req->value), 909 le16_to_cpu(req->index), le16_to_cpu(req->length)); 910 911 dev->act_len = 0; 912 dev->status = USB_ST_STALLED; 913 return -1; 914 } 915 916 int usb_lowlevel_stop(int index) 917 { 918 ehci_shutdown(&ehcic[index]); 919 return ehci_hcd_stop(index); 920 } 921 922 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 923 { 924 uint32_t reg; 925 uint32_t cmd; 926 struct QH *qh_list; 927 struct QH *periodic; 928 int i; 929 int rc; 930 931 rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor); 932 if (rc) 933 return rc; 934 if (init == USB_INIT_DEVICE) 935 goto done; 936 937 /* EHCI spec section 4.1 */ 938 if (ehci_reset(index)) 939 return -1; 940 941 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 942 rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor); 943 if (rc) 944 return rc; 945 #endif 946 /* Set the high address word (aka segment) for 64-bit controller */ 947 if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1) 948 ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0); 949 950 qh_list = &ehcic[index].qh_list; 951 952 /* Set head of reclaim list */ 953 memset(qh_list, 0, sizeof(*qh_list)); 954 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); 955 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | 956 QH_ENDPT1_EPS(USB_SPEED_HIGH)); 957 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); 958 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 959 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 960 qh_list->qh_overlay.qt_token = 961 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); 962 963 flush_dcache_range((uint32_t)qh_list, 964 ALIGN_END_ADDR(struct QH, qh_list, 1)); 965 966 /* Set async. queue head pointer. */ 967 ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list); 968 969 /* 970 * Set up periodic list 971 * Step 1: Parent QH for all periodic transfers. 972 */ 973 periodic = &ehcic[index].periodic_queue; 974 memset(periodic, 0, sizeof(*periodic)); 975 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 976 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 977 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 978 979 flush_dcache_range((uint32_t)periodic, 980 ALIGN_END_ADDR(struct QH, periodic, 1)); 981 982 /* 983 * Step 2: Setup frame-list: Every microframe, USB tries the same list. 984 * In particular, device specifications on polling frequency 985 * are disregarded. Keyboards seem to send NAK/NYet reliably 986 * when polled with an empty buffer. 987 * 988 * Split Transactions will be spread across microframes using 989 * S-mask and C-mask. 990 */ 991 if (ehcic[index].periodic_list == NULL) 992 ehcic[index].periodic_list = memalign(4096, 1024 * 4); 993 994 if (!ehcic[index].periodic_list) 995 return -ENOMEM; 996 for (i = 0; i < 1024; i++) { 997 ehcic[index].periodic_list[i] = (uint32_t)periodic 998 | QH_LINK_TYPE_QH; 999 } 1000 1001 flush_dcache_range((uint32_t)ehcic[index].periodic_list, 1002 ALIGN_END_ADDR(uint32_t, ehcic[index].periodic_list, 1003 1024)); 1004 1005 /* Set periodic list base address */ 1006 ehci_writel(&ehcic[index].hcor->or_periodiclistbase, 1007 (uint32_t)ehcic[index].periodic_list); 1008 1009 reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams); 1010 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 1011 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 1012 /* Port Indicators */ 1013 if (HCS_INDICATOR(reg)) 1014 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1015 | 0x80, &descriptor.hub.wHubCharacteristics); 1016 /* Port Power Control */ 1017 if (HCS_PPC(reg)) 1018 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1019 | 0x01, &descriptor.hub.wHubCharacteristics); 1020 1021 /* Start the host controller. */ 1022 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd); 1023 /* 1024 * Philips, Intel, and maybe others need CMD_RUN before the 1025 * root hub will detect new devices (why?); NEC doesn't 1026 */ 1027 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 1028 cmd |= CMD_RUN; 1029 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd); 1030 1031 #ifndef CONFIG_USB_EHCI_FARADAY 1032 /* take control over the ports */ 1033 cmd = ehci_readl(&ehcic[index].hcor->or_configflag); 1034 cmd |= FLAG_CF; 1035 ehci_writel(&ehcic[index].hcor->or_configflag, cmd); 1036 #endif 1037 1038 /* unblock posted write */ 1039 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd); 1040 mdelay(5); 1041 reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase)); 1042 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 1043 1044 ehcic[index].rootdev = 0; 1045 done: 1046 *controller = &ehcic[index]; 1047 return 0; 1048 } 1049 1050 int 1051 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1052 int length) 1053 { 1054 1055 if (usb_pipetype(pipe) != PIPE_BULK) { 1056 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 1057 return -1; 1058 } 1059 return ehci_submit_async(dev, pipe, buffer, length, NULL); 1060 } 1061 1062 int 1063 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1064 int length, struct devrequest *setup) 1065 { 1066 struct ehci_ctrl *ctrl = dev->controller; 1067 1068 if (usb_pipetype(pipe) != PIPE_CONTROL) { 1069 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 1070 return -1; 1071 } 1072 1073 if (usb_pipedevice(pipe) == ctrl->rootdev) { 1074 if (!ctrl->rootdev) 1075 dev->speed = USB_SPEED_HIGH; 1076 return ehci_submit_root(dev, pipe, buffer, length, setup); 1077 } 1078 return ehci_submit_async(dev, pipe, buffer, length, setup); 1079 } 1080 1081 struct int_queue { 1082 struct QH *first; 1083 struct QH *current; 1084 struct QH *last; 1085 struct qTD *tds; 1086 }; 1087 1088 #define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f) 1089 1090 static int 1091 enable_periodic(struct ehci_ctrl *ctrl) 1092 { 1093 uint32_t cmd; 1094 struct ehci_hcor *hcor = ctrl->hcor; 1095 int ret; 1096 1097 cmd = ehci_readl(&hcor->or_usbcmd); 1098 cmd |= CMD_PSE; 1099 ehci_writel(&hcor->or_usbcmd, cmd); 1100 1101 ret = handshake((uint32_t *)&hcor->or_usbsts, 1102 STS_PSS, STS_PSS, 100 * 1000); 1103 if (ret < 0) { 1104 printf("EHCI failed: timeout when enabling periodic list\n"); 1105 return -ETIMEDOUT; 1106 } 1107 udelay(1000); 1108 return 0; 1109 } 1110 1111 static int 1112 disable_periodic(struct ehci_ctrl *ctrl) 1113 { 1114 uint32_t cmd; 1115 struct ehci_hcor *hcor = ctrl->hcor; 1116 int ret; 1117 1118 cmd = ehci_readl(&hcor->or_usbcmd); 1119 cmd &= ~CMD_PSE; 1120 ehci_writel(&hcor->or_usbcmd, cmd); 1121 1122 ret = handshake((uint32_t *)&hcor->or_usbsts, 1123 STS_PSS, 0, 100 * 1000); 1124 if (ret < 0) { 1125 printf("EHCI failed: timeout when disabling periodic list\n"); 1126 return -ETIMEDOUT; 1127 } 1128 return 0; 1129 } 1130 1131 static int periodic_schedules; 1132 1133 struct int_queue * 1134 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, 1135 int elementsize, void *buffer) 1136 { 1137 struct ehci_ctrl *ctrl = dev->controller; 1138 struct int_queue *result = NULL; 1139 int i; 1140 1141 debug("Enter create_int_queue\n"); 1142 if (usb_pipetype(pipe) != PIPE_INTERRUPT) { 1143 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); 1144 return NULL; 1145 } 1146 1147 /* limit to 4 full pages worth of data - 1148 * we can safely fit them in a single TD, 1149 * no matter the alignment 1150 */ 1151 if (elementsize >= 16384) { 1152 debug("too large elements for interrupt transfers\n"); 1153 return NULL; 1154 } 1155 1156 result = malloc(sizeof(*result)); 1157 if (!result) { 1158 debug("ehci intr queue: out of memory\n"); 1159 goto fail1; 1160 } 1161 result->first = memalign(32, sizeof(struct QH) * queuesize); 1162 if (!result->first) { 1163 debug("ehci intr queue: out of memory\n"); 1164 goto fail2; 1165 } 1166 result->current = result->first; 1167 result->last = result->first + queuesize - 1; 1168 result->tds = memalign(32, sizeof(struct qTD) * queuesize); 1169 if (!result->tds) { 1170 debug("ehci intr queue: out of memory\n"); 1171 goto fail3; 1172 } 1173 memset(result->first, 0, sizeof(struct QH) * queuesize); 1174 memset(result->tds, 0, sizeof(struct qTD) * queuesize); 1175 1176 for (i = 0; i < queuesize; i++) { 1177 struct QH *qh = result->first + i; 1178 struct qTD *td = result->tds + i; 1179 void **buf = &qh->buffer; 1180 1181 qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH; 1182 if (i == queuesize - 1) 1183 qh->qh_link = QH_LINK_TERMINATE; 1184 1185 qh->qh_overlay.qt_next = (uint32_t)td; 1186 qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */ 1187 (usb_maxpacket(dev, pipe) << 16) | /* MPS */ 1188 (1 << 14) | 1189 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 1190 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ 1191 (usb_pipedevice(pipe) << 0); 1192 qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */ 1193 (1 << 0); /* S-mask: microframe 0 */ 1194 if (dev->speed == USB_SPEED_LOW || 1195 dev->speed == USB_SPEED_FULL) { 1196 debug("TT: port: %d, hub address: %d\n", 1197 dev->portnr, dev->parent->devnum); 1198 qh->qh_endpt2 |= (dev->portnr << 23) | 1199 (dev->parent->devnum << 16) | 1200 (0x1c << 8); /* C-mask: microframes 2-4 */ 1201 } 1202 1203 td->qt_next = QT_NEXT_TERMINATE; 1204 td->qt_altnext = QT_NEXT_TERMINATE; 1205 debug("communication direction is '%s'\n", 1206 usb_pipein(pipe) ? "in" : "out"); 1207 td->qt_token = (elementsize << 16) | 1208 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ 1209 0x80; /* active */ 1210 td->qt_buffer[0] = (uint32_t)buffer + i * elementsize; 1211 td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff; 1212 td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff; 1213 td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff; 1214 td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff; 1215 1216 *buf = buffer + i * elementsize; 1217 } 1218 1219 flush_dcache_range((uint32_t)buffer, 1220 ALIGN_END_ADDR(char, buffer, 1221 queuesize * elementsize)); 1222 flush_dcache_range((uint32_t)result->first, 1223 ALIGN_END_ADDR(struct QH, result->first, 1224 queuesize)); 1225 flush_dcache_range((uint32_t)result->tds, 1226 ALIGN_END_ADDR(struct qTD, result->tds, 1227 queuesize)); 1228 1229 if (disable_periodic(ctrl) < 0) { 1230 debug("FATAL: periodic should never fail, but did"); 1231 goto fail3; 1232 } 1233 1234 /* hook up to periodic list */ 1235 struct QH *list = &ctrl->periodic_queue; 1236 result->last->qh_link = list->qh_link; 1237 list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH; 1238 1239 flush_dcache_range((uint32_t)result->last, 1240 ALIGN_END_ADDR(struct QH, result->last, 1)); 1241 flush_dcache_range((uint32_t)list, 1242 ALIGN_END_ADDR(struct QH, list, 1)); 1243 1244 if (enable_periodic(ctrl) < 0) { 1245 debug("FATAL: periodic should never fail, but did"); 1246 goto fail3; 1247 } 1248 periodic_schedules++; 1249 1250 debug("Exit create_int_queue\n"); 1251 return result; 1252 fail3: 1253 if (result->tds) 1254 free(result->tds); 1255 fail2: 1256 if (result->first) 1257 free(result->first); 1258 if (result) 1259 free(result); 1260 fail1: 1261 return NULL; 1262 } 1263 1264 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) 1265 { 1266 struct QH *cur = queue->current; 1267 1268 /* depleted queue */ 1269 if (cur == NULL) { 1270 debug("Exit poll_int_queue with completed queue\n"); 1271 return NULL; 1272 } 1273 /* still active */ 1274 invalidate_dcache_range((uint32_t)cur, 1275 ALIGN_END_ADDR(struct QH, cur, 1)); 1276 if (cur->qh_overlay.qt_token & 0x80) { 1277 debug("Exit poll_int_queue with no completed intr transfer. " 1278 "token is %x\n", cur->qh_overlay.qt_token); 1279 return NULL; 1280 } 1281 if (!(cur->qh_link & QH_LINK_TERMINATE)) 1282 queue->current++; 1283 else 1284 queue->current = NULL; 1285 debug("Exit poll_int_queue with completed intr transfer. " 1286 "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token, 1287 &cur->qh_overlay.qt_token, queue->first); 1288 return cur->buffer; 1289 } 1290 1291 /* Do not free buffers associated with QHs, they're owned by someone else */ 1292 int 1293 destroy_int_queue(struct usb_device *dev, struct int_queue *queue) 1294 { 1295 struct ehci_ctrl *ctrl = dev->controller; 1296 int result = -1; 1297 unsigned long timeout; 1298 1299 if (disable_periodic(ctrl) < 0) { 1300 debug("FATAL: periodic should never fail, but did"); 1301 goto out; 1302 } 1303 periodic_schedules--; 1304 1305 struct QH *cur = &ctrl->periodic_queue; 1306 timeout = get_timer(0) + 500; /* abort after 500ms */ 1307 while (!(cur->qh_link & QH_LINK_TERMINATE)) { 1308 debug("considering %p, with qh_link %x\n", cur, cur->qh_link); 1309 if (NEXT_QH(cur) == queue->first) { 1310 debug("found candidate. removing from chain\n"); 1311 cur->qh_link = queue->last->qh_link; 1312 result = 0; 1313 break; 1314 } 1315 cur = NEXT_QH(cur); 1316 if (get_timer(0) > timeout) { 1317 printf("Timeout destroying interrupt endpoint queue\n"); 1318 result = -1; 1319 goto out; 1320 } 1321 } 1322 1323 if (periodic_schedules > 0) { 1324 result = enable_periodic(ctrl); 1325 if (result < 0) 1326 debug("FATAL: periodic should never fail, but did"); 1327 } 1328 1329 out: 1330 free(queue->tds); 1331 free(queue->first); 1332 free(queue); 1333 1334 return result; 1335 } 1336 1337 int 1338 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1339 int length, int interval) 1340 { 1341 void *backbuffer; 1342 struct int_queue *queue; 1343 unsigned long timeout; 1344 int result = 0, ret; 1345 1346 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 1347 dev, pipe, buffer, length, interval); 1348 1349 /* 1350 * Interrupt transfers requiring several transactions are not supported 1351 * because bInterval is ignored. 1352 * 1353 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 1354 * <= PKT_ALIGN if several qTDs are required, while the USB 1355 * specification does not constrain this for interrupt transfers. That 1356 * means that ehci_submit_async() would support interrupt transfers 1357 * requiring several transactions only as long as the transfer size does 1358 * not require more than a single qTD. 1359 */ 1360 if (length > usb_maxpacket(dev, pipe)) { 1361 printf("%s: Interrupt transfers requiring several " 1362 "transactions are not supported.\n", __func__); 1363 return -1; 1364 } 1365 1366 queue = create_int_queue(dev, pipe, 1, length, buffer); 1367 1368 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1369 while ((backbuffer = poll_int_queue(dev, queue)) == NULL) 1370 if (get_timer(0) > timeout) { 1371 printf("Timeout poll on interrupt endpoint\n"); 1372 result = -ETIMEDOUT; 1373 break; 1374 } 1375 1376 if (backbuffer != buffer) { 1377 debug("got wrong buffer back (%x instead of %x)\n", 1378 (uint32_t)backbuffer, (uint32_t)buffer); 1379 return -EINVAL; 1380 } 1381 1382 invalidate_dcache_range((uint32_t)buffer, 1383 ALIGN_END_ADDR(char, buffer, length)); 1384 1385 ret = destroy_int_queue(dev, queue); 1386 if (ret < 0) 1387 return ret; 1388 1389 /* everything worked out fine */ 1390 return result; 1391 } 1392