1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <asm/byteorder.h> 27 #include <asm/unaligned.h> 28 #include <usb.h> 29 #include <asm/io.h> 30 #include <malloc.h> 31 #include <watchdog.h> 32 #include <linux/compiler.h> 33 34 #include "ehci.h" 35 36 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 37 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 38 #endif 39 40 /* 41 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. 42 * Let's time out after 8 to have a little safety margin on top of that. 43 */ 44 #define HCHALT_TIMEOUT (8 * 1000) 45 46 #ifndef CONFIG_DM_USB 47 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; 48 #endif 49 50 #define ALIGN_END_ADDR(type, ptr, size) \ 51 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) 52 53 static struct descriptor { 54 struct usb_hub_descriptor hub; 55 struct usb_device_descriptor device; 56 struct usb_linux_config_descriptor config; 57 struct usb_linux_interface_descriptor interface; 58 struct usb_endpoint_descriptor endpoint; 59 } __attribute__ ((packed)) descriptor = { 60 { 61 0x8, /* bDescLength */ 62 0x29, /* bDescriptorType: hub descriptor */ 63 2, /* bNrPorts -- runtime modified */ 64 0, /* wHubCharacteristics */ 65 10, /* bPwrOn2PwrGood */ 66 0, /* bHubCntrCurrent */ 67 {}, /* Device removable */ 68 {} /* at most 7 ports! XXX */ 69 }, 70 { 71 0x12, /* bLength */ 72 1, /* bDescriptorType: UDESC_DEVICE */ 73 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 74 9, /* bDeviceClass: UDCLASS_HUB */ 75 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 76 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 77 64, /* bMaxPacketSize: 64 bytes */ 78 0x0000, /* idVendor */ 79 0x0000, /* idProduct */ 80 cpu_to_le16(0x0100), /* bcdDevice */ 81 1, /* iManufacturer */ 82 2, /* iProduct */ 83 0, /* iSerialNumber */ 84 1 /* bNumConfigurations: 1 */ 85 }, 86 { 87 0x9, 88 2, /* bDescriptorType: UDESC_CONFIG */ 89 cpu_to_le16(0x19), 90 1, /* bNumInterface */ 91 1, /* bConfigurationValue */ 92 0, /* iConfiguration */ 93 0x40, /* bmAttributes: UC_SELF_POWER */ 94 0 /* bMaxPower */ 95 }, 96 { 97 0x9, /* bLength */ 98 4, /* bDescriptorType: UDESC_INTERFACE */ 99 0, /* bInterfaceNumber */ 100 0, /* bAlternateSetting */ 101 1, /* bNumEndpoints */ 102 9, /* bInterfaceClass: UICLASS_HUB */ 103 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 104 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 105 0 /* iInterface */ 106 }, 107 { 108 0x7, /* bLength */ 109 5, /* bDescriptorType: UDESC_ENDPOINT */ 110 0x81, /* bEndpointAddress: 111 * UE_DIR_IN | EHCI_INTR_ENDPT 112 */ 113 3, /* bmAttributes: UE_INTERRUPT */ 114 8, /* wMaxPacketSize */ 115 255 /* bInterval */ 116 }, 117 }; 118 119 #if defined(CONFIG_EHCI_IS_TDI) 120 #define ehci_is_TDI() (1) 121 #else 122 #define ehci_is_TDI() (0) 123 #endif 124 125 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev) 126 { 127 #ifdef CONFIG_DM_USB 128 return dev_get_priv(usb_get_bus(udev->dev)); 129 #else 130 return udev->controller; 131 #endif 132 } 133 134 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 135 { 136 return PORTSC_PSPD(reg); 137 } 138 139 static void ehci_set_usbmode(struct ehci_ctrl *ctrl) 140 { 141 uint32_t tmp; 142 uint32_t *reg_ptr; 143 144 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE); 145 tmp = ehci_readl(reg_ptr); 146 tmp |= USBMODE_CM_HC; 147 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 148 tmp |= USBMODE_BE; 149 #endif 150 ehci_writel(reg_ptr, tmp); 151 } 152 153 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, 154 uint32_t *reg) 155 { 156 mdelay(50); 157 } 158 159 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) 160 { 161 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 162 /* Printing the message would cause a scan failure! */ 163 debug("The request port(%u) is not configured\n", port); 164 return NULL; 165 } 166 167 return (uint32_t *)&ctrl->hcor->or_portsc[port]; 168 } 169 170 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 171 { 172 uint32_t result; 173 do { 174 result = ehci_readl(ptr); 175 udelay(5); 176 if (result == ~(uint32_t)0) 177 return -1; 178 result &= mask; 179 if (result == done) 180 return 0; 181 usec--; 182 } while (usec > 0); 183 return -1; 184 } 185 186 static int ehci_reset(struct ehci_ctrl *ctrl) 187 { 188 uint32_t cmd; 189 int ret = 0; 190 191 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 192 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 193 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 194 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd, 195 CMD_RESET, 0, 250 * 1000); 196 if (ret < 0) { 197 printf("EHCI fail to reset\n"); 198 goto out; 199 } 200 201 if (ehci_is_TDI()) 202 ctrl->ops.set_usb_mode(ctrl); 203 204 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH 205 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning); 206 cmd &= ~TXFIFO_THRESH_MASK; 207 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); 208 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd); 209 #endif 210 out: 211 return ret; 212 } 213 214 static int ehci_shutdown(struct ehci_ctrl *ctrl) 215 { 216 int i, ret = 0; 217 uint32_t cmd, reg; 218 219 if (!ctrl || !ctrl->hcor) 220 return -EINVAL; 221 222 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 223 cmd &= ~(CMD_PSE | CMD_ASE); 224 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 225 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0, 226 100 * 1000); 227 228 if (!ret) { 229 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) { 230 reg = ehci_readl(&ctrl->hcor->or_portsc[i]); 231 reg |= EHCI_PS_SUSP; 232 ehci_writel(&ctrl->hcor->or_portsc[i], reg); 233 } 234 235 cmd &= ~CMD_RUN; 236 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 237 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT, 238 HCHALT_TIMEOUT); 239 } 240 241 if (ret) 242 puts("EHCI failed to shut down host controller.\n"); 243 244 return ret; 245 } 246 247 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 248 { 249 uint32_t delta, next; 250 uint32_t addr = (unsigned long)buf; 251 int idx; 252 253 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) 254 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); 255 256 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); 257 258 idx = 0; 259 while (idx < QT_BUFFER_CNT) { 260 td->qt_buffer[idx] = cpu_to_hc32(addr); 261 td->qt_buffer_hi[idx] = 0; 262 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); 263 delta = next - addr; 264 if (delta >= sz) 265 break; 266 sz -= delta; 267 addr = next; 268 idx++; 269 } 270 271 if (idx == QT_BUFFER_CNT) { 272 printf("out of buffer pointers (%zu bytes left)\n", sz); 273 return -1; 274 } 275 276 return 0; 277 } 278 279 static inline u8 ehci_encode_speed(enum usb_device_speed speed) 280 { 281 #define QH_HIGH_SPEED 2 282 #define QH_FULL_SPEED 0 283 #define QH_LOW_SPEED 1 284 if (speed == USB_SPEED_HIGH) 285 return QH_HIGH_SPEED; 286 if (speed == USB_SPEED_LOW) 287 return QH_LOW_SPEED; 288 return QH_FULL_SPEED; 289 } 290 291 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, 292 struct QH *qh) 293 { 294 struct usb_device *ttdev; 295 int parent_devnum; 296 297 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL) 298 return; 299 300 /* 301 * For full / low speed devices we need to get the devnum and portnr of 302 * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs 303 * in the tree before that one! 304 */ 305 #ifdef CONFIG_DM_USB 306 /* 307 * When called from usb-uclass.c: usb_scan_device() udev->dev points 308 * to the parent udevice, not the actual udevice belonging to the 309 * udev as the device is not instantiated yet. So when searching 310 * for the first usb-2 parent start with udev->dev not 311 * udev->dev->parent . 312 */ 313 struct udevice *parent; 314 struct usb_device *uparent; 315 316 ttdev = udev; 317 parent = udev->dev; 318 uparent = dev_get_parentdata(parent); 319 320 while (uparent->speed != USB_SPEED_HIGH) { 321 struct udevice *dev = parent; 322 323 if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { 324 printf("ehci: Error cannot find high speed parent of usb-1 device\n"); 325 return; 326 } 327 328 ttdev = dev_get_parentdata(dev); 329 parent = dev->parent; 330 uparent = dev_get_parentdata(parent); 331 } 332 parent_devnum = uparent->devnum; 333 #else 334 ttdev = udev; 335 while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH) 336 ttdev = ttdev->parent; 337 if (!ttdev->parent) 338 return; 339 parent_devnum = ttdev->parent->devnum; 340 #endif 341 342 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) | 343 QH_ENDPT2_HUBADDR(parent_devnum)); 344 } 345 346 static int 347 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 348 int length, struct devrequest *req) 349 { 350 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); 351 struct qTD *qtd; 352 int qtd_count = 0; 353 int qtd_counter = 0; 354 volatile struct qTD *vtd; 355 unsigned long ts; 356 uint32_t *tdp; 357 uint32_t endpt, maxpacket, token, usbsts; 358 uint32_t c, toggle; 359 uint32_t cmd; 360 int timeout; 361 int ret = 0; 362 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 363 364 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 365 buffer, length, req); 366 if (req != NULL) 367 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 368 req->request, req->request, 369 req->requesttype, req->requesttype, 370 le16_to_cpu(req->value), le16_to_cpu(req->value), 371 le16_to_cpu(req->index)); 372 373 #define PKT_ALIGN 512 374 /* 375 * The USB transfer is split into qTD transfers. Eeach qTD transfer is 376 * described by a transfer descriptor (the qTD). The qTDs form a linked 377 * list with a queue head (QH). 378 * 379 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot 380 * have its beginning in a qTD transfer and its end in the following 381 * one, so the qTD transfer lengths have to be chosen accordingly. 382 * 383 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to 384 * single pages. The first data buffer can start at any offset within a 385 * page (not considering the cache-line alignment issues), while the 386 * following buffers must be page-aligned. There is no alignment 387 * constraint on the size of a qTD transfer. 388 */ 389 if (req != NULL) 390 /* 1 qTD will be needed for SETUP, and 1 for ACK. */ 391 qtd_count += 1 + 1; 392 if (length > 0 || req == NULL) { 393 /* 394 * Determine the qTD transfer size that will be used for the 395 * data payload (not considering the first qTD transfer, which 396 * may be longer or shorter, and the final one, which may be 397 * shorter). 398 * 399 * In order to keep each packet within a qTD transfer, the qTD 400 * transfer size is aligned to PKT_ALIGN, which is a multiple of 401 * wMaxPacketSize (except in some cases for interrupt transfers, 402 * see comment in submit_int_msg()). 403 * 404 * By default, i.e. if the input buffer is aligned to PKT_ALIGN, 405 * QT_BUFFER_CNT full pages will be used. 406 */ 407 int xfr_sz = QT_BUFFER_CNT; 408 /* 409 * However, if the input buffer is not aligned to PKT_ALIGN, the 410 * qTD transfer size will be one page shorter, and the first qTD 411 * data buffer of each transfer will be page-unaligned. 412 */ 413 if ((unsigned long)buffer & (PKT_ALIGN - 1)) 414 xfr_sz--; 415 /* Convert the qTD transfer size to bytes. */ 416 xfr_sz *= EHCI_PAGE_SIZE; 417 /* 418 * Approximate by excess the number of qTDs that will be 419 * required for the data payload. The exact formula is way more 420 * complicated and saves at most 2 qTDs, i.e. a total of 128 421 * bytes. 422 */ 423 qtd_count += 2 + length / xfr_sz; 424 } 425 /* 426 * Threshold value based on the worst-case total size of the allocated qTDs for 427 * a mass-storage transfer of 65535 blocks of 512 bytes. 428 */ 429 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024 430 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI 431 #endif 432 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); 433 if (qtd == NULL) { 434 printf("unable to allocate TDs\n"); 435 return -1; 436 } 437 438 memset(qh, 0, sizeof(struct QH)); 439 memset(qtd, 0, qtd_count * sizeof(*qtd)); 440 441 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 442 443 /* 444 * Setup QH (3.6 in ehci-r10.pdf) 445 * 446 * qh_link ................. 03-00 H 447 * qh_endpt1 ............... 07-04 H 448 * qh_endpt2 ............... 0B-08 H 449 * - qh_curtd 450 * qh_overlay.qt_next ...... 13-10 H 451 * - qh_overlay.qt_altnext 452 */ 453 qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH); 454 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe); 455 maxpacket = usb_maxpacket(dev, pipe); 456 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | 457 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | 458 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | 459 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 460 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | 461 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); 462 qh->qh_endpt1 = cpu_to_hc32(endpt); 463 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); 464 qh->qh_endpt2 = cpu_to_hc32(endpt); 465 ehci_update_endpt2_dev_n_port(dev, qh); 466 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 467 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 468 469 tdp = &qh->qh_overlay.qt_next; 470 471 if (req != NULL) { 472 /* 473 * Setup request qTD (3.5 in ehci-r10.pdf) 474 * 475 * qt_next ................ 03-00 H 476 * qt_altnext ............. 07-04 H 477 * qt_token ............... 0B-08 H 478 * 479 * [ buffer, buffer_hi ] loaded with "req". 480 */ 481 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 482 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 483 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) | 484 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 485 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) | 486 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 487 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 488 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) { 489 printf("unable to construct SETUP TD\n"); 490 goto fail; 491 } 492 /* Update previous qTD! */ 493 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]); 494 tdp = &qtd[qtd_counter++].qt_next; 495 toggle = 1; 496 } 497 498 if (length > 0 || req == NULL) { 499 uint8_t *buf_ptr = buffer; 500 int left_length = length; 501 502 do { 503 /* 504 * Determine the size of this qTD transfer. By default, 505 * QT_BUFFER_CNT full pages can be used. 506 */ 507 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE; 508 /* 509 * However, if the input buffer is not page-aligned, the 510 * portion of the first page before the buffer start 511 * offset within that page is unusable. 512 */ 513 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1); 514 /* 515 * In order to keep each packet within a qTD transfer, 516 * align the qTD transfer size to PKT_ALIGN. 517 */ 518 xfr_bytes &= ~(PKT_ALIGN - 1); 519 /* 520 * This transfer may be shorter than the available qTD 521 * transfer size that has just been computed. 522 */ 523 xfr_bytes = min(xfr_bytes, left_length); 524 525 /* 526 * Setup request qTD (3.5 in ehci-r10.pdf) 527 * 528 * qt_next ................ 03-00 H 529 * qt_altnext ............. 07-04 H 530 * qt_token ............... 0B-08 H 531 * 532 * [ buffer, buffer_hi ] loaded with "buffer". 533 */ 534 qtd[qtd_counter].qt_next = 535 cpu_to_hc32(QT_NEXT_TERMINATE); 536 qtd[qtd_counter].qt_altnext = 537 cpu_to_hc32(QT_NEXT_TERMINATE); 538 token = QT_TOKEN_DT(toggle) | 539 QT_TOKEN_TOTALBYTES(xfr_bytes) | 540 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) | 541 QT_TOKEN_CERR(3) | 542 QT_TOKEN_PID(usb_pipein(pipe) ? 543 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) | 544 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 545 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 546 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr, 547 xfr_bytes)) { 548 printf("unable to construct DATA TD\n"); 549 goto fail; 550 } 551 /* Update previous qTD! */ 552 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]); 553 tdp = &qtd[qtd_counter++].qt_next; 554 /* 555 * Data toggle has to be adjusted since the qTD transfer 556 * size is not always an even multiple of 557 * wMaxPacketSize. 558 */ 559 if ((xfr_bytes / maxpacket) & 1) 560 toggle ^= 1; 561 buf_ptr += xfr_bytes; 562 left_length -= xfr_bytes; 563 } while (left_length > 0); 564 } 565 566 if (req != NULL) { 567 /* 568 * Setup request qTD (3.5 in ehci-r10.pdf) 569 * 570 * qt_next ................ 03-00 H 571 * qt_altnext ............. 07-04 H 572 * qt_token ............... 0B-08 H 573 */ 574 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 575 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 576 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) | 577 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 578 QT_TOKEN_PID(usb_pipein(pipe) ? 579 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) | 580 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 581 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 582 /* Update previous qTD! */ 583 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]); 584 tdp = &qtd[qtd_counter++].qt_next; 585 } 586 587 ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH); 588 589 /* Flush dcache */ 590 flush_dcache_range((unsigned long)&ctrl->qh_list, 591 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 592 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1)); 593 flush_dcache_range((unsigned long)qtd, 594 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 595 596 /* Set async. queue head pointer. */ 597 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list); 598 599 usbsts = ehci_readl(&ctrl->hcor->or_usbsts); 600 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); 601 602 /* Enable async. schedule. */ 603 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 604 cmd |= CMD_ASE; 605 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 606 607 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, 608 100 * 1000); 609 if (ret < 0) { 610 printf("EHCI fail timeout STS_ASS set\n"); 611 goto fail; 612 } 613 614 /* Wait for TDs to be processed. */ 615 ts = get_timer(0); 616 vtd = &qtd[qtd_counter - 1]; 617 timeout = USB_TIMEOUT_MS(pipe); 618 do { 619 /* Invalidate dcache */ 620 invalidate_dcache_range((unsigned long)&ctrl->qh_list, 621 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 622 invalidate_dcache_range((unsigned long)qh, 623 ALIGN_END_ADDR(struct QH, qh, 1)); 624 invalidate_dcache_range((unsigned long)qtd, 625 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 626 627 token = hc32_to_cpu(vtd->qt_token); 628 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) 629 break; 630 WATCHDOG_RESET(); 631 } while (get_timer(ts) < timeout); 632 633 /* 634 * Invalidate the memory area occupied by buffer 635 * Don't try to fix the buffer alignment, if it isn't properly 636 * aligned it's upper layer's fault so let invalidate_dcache_range() 637 * vow about it. But we have to fix the length as it's actual 638 * transfer length and can be unaligned. This is potentially 639 * dangerous operation, it's responsibility of the calling 640 * code to make sure enough space is reserved. 641 */ 642 invalidate_dcache_range((unsigned long)buffer, 643 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN)); 644 645 /* Check that the TD processing happened */ 646 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) 647 printf("EHCI timed out on TD - token=%#x\n", token); 648 649 /* Disable async schedule. */ 650 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 651 cmd &= ~CMD_ASE; 652 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 653 654 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0, 655 100 * 1000); 656 if (ret < 0) { 657 printf("EHCI fail timeout STS_ASS reset\n"); 658 goto fail; 659 } 660 661 token = hc32_to_cpu(qh->qh_overlay.qt_token); 662 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) { 663 debug("TOKEN=%#x\n", token); 664 switch (QT_TOKEN_GET_STATUS(token) & 665 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { 666 case 0: 667 toggle = QT_TOKEN_GET_DT(token); 668 usb_settoggle(dev, usb_pipeendpoint(pipe), 669 usb_pipeout(pipe), toggle); 670 dev->status = 0; 671 break; 672 case QT_TOKEN_STATUS_HALTED: 673 dev->status = USB_ST_STALLED; 674 break; 675 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: 676 case QT_TOKEN_STATUS_DATBUFERR: 677 dev->status = USB_ST_BUF_ERR; 678 break; 679 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: 680 case QT_TOKEN_STATUS_BABBLEDET: 681 dev->status = USB_ST_BABBLE_DET; 682 break; 683 default: 684 dev->status = USB_ST_CRC_ERR; 685 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED) 686 dev->status |= USB_ST_STALLED; 687 break; 688 } 689 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token); 690 } else { 691 dev->act_len = 0; 692 #ifndef CONFIG_USB_EHCI_FARADAY 693 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 694 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), 695 ehci_readl(&ctrl->hcor->or_portsc[0]), 696 ehci_readl(&ctrl->hcor->or_portsc[1])); 697 #endif 698 } 699 700 free(qtd); 701 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 702 703 fail: 704 free(qtd); 705 return -1; 706 } 707 708 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, 709 void *buffer, int length, struct devrequest *req) 710 { 711 uint8_t tmpbuf[4]; 712 u16 typeReq; 713 void *srcptr = NULL; 714 int len, srclen; 715 uint32_t reg; 716 uint32_t *status_reg; 717 int port = le16_to_cpu(req->index) & 0xff; 718 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 719 720 srclen = 0; 721 722 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 723 req->request, req->request, 724 req->requesttype, req->requesttype, 725 le16_to_cpu(req->value), le16_to_cpu(req->index)); 726 727 typeReq = req->request | req->requesttype << 8; 728 729 switch (typeReq) { 730 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 731 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 732 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 733 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1); 734 if (!status_reg) 735 return -1; 736 break; 737 default: 738 status_reg = NULL; 739 break; 740 } 741 742 switch (typeReq) { 743 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 744 switch (le16_to_cpu(req->value) >> 8) { 745 case USB_DT_DEVICE: 746 debug("USB_DT_DEVICE request\n"); 747 srcptr = &descriptor.device; 748 srclen = descriptor.device.bLength; 749 break; 750 case USB_DT_CONFIG: 751 debug("USB_DT_CONFIG config\n"); 752 srcptr = &descriptor.config; 753 srclen = descriptor.config.bLength + 754 descriptor.interface.bLength + 755 descriptor.endpoint.bLength; 756 break; 757 case USB_DT_STRING: 758 debug("USB_DT_STRING config\n"); 759 switch (le16_to_cpu(req->value) & 0xff) { 760 case 0: /* Language */ 761 srcptr = "\4\3\1\0"; 762 srclen = 4; 763 break; 764 case 1: /* Vendor */ 765 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 766 srclen = 14; 767 break; 768 case 2: /* Product */ 769 srcptr = "\52\3E\0H\0C\0I\0 " 770 "\0H\0o\0s\0t\0 " 771 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 772 srclen = 42; 773 break; 774 default: 775 debug("unknown value DT_STRING %x\n", 776 le16_to_cpu(req->value)); 777 goto unknown; 778 } 779 break; 780 default: 781 debug("unknown value %x\n", le16_to_cpu(req->value)); 782 goto unknown; 783 } 784 break; 785 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 786 switch (le16_to_cpu(req->value) >> 8) { 787 case USB_DT_HUB: 788 debug("USB_DT_HUB config\n"); 789 srcptr = &descriptor.hub; 790 srclen = descriptor.hub.bLength; 791 break; 792 default: 793 debug("unknown value %x\n", le16_to_cpu(req->value)); 794 goto unknown; 795 } 796 break; 797 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 798 debug("USB_REQ_SET_ADDRESS\n"); 799 ctrl->rootdev = le16_to_cpu(req->value); 800 break; 801 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 802 debug("USB_REQ_SET_CONFIGURATION\n"); 803 /* Nothing to do */ 804 break; 805 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 806 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 807 tmpbuf[1] = 0; 808 srcptr = tmpbuf; 809 srclen = 2; 810 break; 811 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 812 memset(tmpbuf, 0, 4); 813 reg = ehci_readl(status_reg); 814 if (reg & EHCI_PS_CS) 815 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 816 if (reg & EHCI_PS_PE) 817 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 818 if (reg & EHCI_PS_SUSP) 819 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 820 if (reg & EHCI_PS_OCA) 821 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 822 if (reg & EHCI_PS_PR) 823 tmpbuf[0] |= USB_PORT_STAT_RESET; 824 if (reg & EHCI_PS_PP) 825 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 826 827 if (ehci_is_TDI()) { 828 switch (ctrl->ops.get_port_speed(ctrl, reg)) { 829 case PORTSC_PSPD_FS: 830 break; 831 case PORTSC_PSPD_LS: 832 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 833 break; 834 case PORTSC_PSPD_HS: 835 default: 836 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 837 break; 838 } 839 } else { 840 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 841 } 842 843 if (reg & EHCI_PS_CSC) 844 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 845 if (reg & EHCI_PS_PEC) 846 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 847 if (reg & EHCI_PS_OCC) 848 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 849 if (ctrl->portreset & (1 << port)) 850 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 851 852 srcptr = tmpbuf; 853 srclen = 4; 854 break; 855 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 856 reg = ehci_readl(status_reg); 857 reg &= ~EHCI_PS_CLEAR; 858 switch (le16_to_cpu(req->value)) { 859 case USB_PORT_FEAT_ENABLE: 860 reg |= EHCI_PS_PE; 861 ehci_writel(status_reg, reg); 862 break; 863 case USB_PORT_FEAT_POWER: 864 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) { 865 reg |= EHCI_PS_PP; 866 ehci_writel(status_reg, reg); 867 } 868 break; 869 case USB_PORT_FEAT_RESET: 870 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 871 !ehci_is_TDI() && 872 EHCI_PS_IS_LOWSPEED(reg)) { 873 /* Low speed device, give up ownership. */ 874 debug("port %d low speed --> companion\n", 875 port - 1); 876 reg |= EHCI_PS_PO; 877 ehci_writel(status_reg, reg); 878 return -ENXIO; 879 } else { 880 int ret; 881 882 reg |= EHCI_PS_PR; 883 reg &= ~EHCI_PS_PE; 884 ehci_writel(status_reg, reg); 885 /* 886 * caller must wait, then call GetPortStatus 887 * usb 2.0 specification say 50 ms resets on 888 * root 889 */ 890 ctrl->ops.powerup_fixup(ctrl, status_reg, ®); 891 892 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 893 /* 894 * A host controller must terminate the reset 895 * and stabilize the state of the port within 896 * 2 milliseconds 897 */ 898 ret = handshake(status_reg, EHCI_PS_PR, 0, 899 2 * 1000); 900 if (!ret) { 901 reg = ehci_readl(status_reg); 902 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) 903 == EHCI_PS_CS && !ehci_is_TDI()) { 904 debug("port %d full speed --> companion\n", port - 1); 905 reg &= ~EHCI_PS_CLEAR; 906 reg |= EHCI_PS_PO; 907 ehci_writel(status_reg, reg); 908 return -ENXIO; 909 } else { 910 ctrl->portreset |= 1 << port; 911 } 912 } else { 913 printf("port(%d) reset error\n", 914 port - 1); 915 } 916 } 917 break; 918 case USB_PORT_FEAT_TEST: 919 ehci_shutdown(ctrl); 920 reg &= ~(0xf << 16); 921 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16; 922 ehci_writel(status_reg, reg); 923 break; 924 default: 925 debug("unknown feature %x\n", le16_to_cpu(req->value)); 926 goto unknown; 927 } 928 /* unblock posted writes */ 929 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 930 break; 931 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 932 reg = ehci_readl(status_reg); 933 reg &= ~EHCI_PS_CLEAR; 934 switch (le16_to_cpu(req->value)) { 935 case USB_PORT_FEAT_ENABLE: 936 reg &= ~EHCI_PS_PE; 937 break; 938 case USB_PORT_FEAT_C_ENABLE: 939 reg |= EHCI_PS_PE; 940 break; 941 case USB_PORT_FEAT_POWER: 942 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) 943 reg &= ~EHCI_PS_PP; 944 break; 945 case USB_PORT_FEAT_C_CONNECTION: 946 reg |= EHCI_PS_CSC; 947 break; 948 case USB_PORT_FEAT_OVER_CURRENT: 949 reg |= EHCI_PS_OCC; 950 break; 951 case USB_PORT_FEAT_C_RESET: 952 ctrl->portreset &= ~(1 << port); 953 break; 954 default: 955 debug("unknown feature %x\n", le16_to_cpu(req->value)); 956 goto unknown; 957 } 958 ehci_writel(status_reg, reg); 959 /* unblock posted write */ 960 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 961 break; 962 default: 963 debug("Unknown request\n"); 964 goto unknown; 965 } 966 967 mdelay(1); 968 len = min3(srclen, (int)le16_to_cpu(req->length), length); 969 if (srcptr != NULL && len > 0) 970 memcpy(buffer, srcptr, len); 971 else 972 debug("Len is 0\n"); 973 974 dev->act_len = len; 975 dev->status = 0; 976 return 0; 977 978 unknown: 979 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 980 req->requesttype, req->request, le16_to_cpu(req->value), 981 le16_to_cpu(req->index), le16_to_cpu(req->length)); 982 983 dev->act_len = 0; 984 dev->status = USB_ST_STALLED; 985 return -1; 986 } 987 988 const struct ehci_ops default_ehci_ops = { 989 .set_usb_mode = ehci_set_usbmode, 990 .get_port_speed = ehci_get_port_speed, 991 .powerup_fixup = ehci_powerup_fixup, 992 .get_portsc_register = ehci_get_portsc_register, 993 }; 994 995 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops) 996 { 997 if (!ops) { 998 ctrl->ops = default_ehci_ops; 999 } else { 1000 ctrl->ops = *ops; 1001 if (!ctrl->ops.set_usb_mode) 1002 ctrl->ops.set_usb_mode = ehci_set_usbmode; 1003 if (!ctrl->ops.get_port_speed) 1004 ctrl->ops.get_port_speed = ehci_get_port_speed; 1005 if (!ctrl->ops.powerup_fixup) 1006 ctrl->ops.powerup_fixup = ehci_powerup_fixup; 1007 if (!ctrl->ops.get_portsc_register) 1008 ctrl->ops.get_portsc_register = 1009 ehci_get_portsc_register; 1010 } 1011 } 1012 1013 #ifndef CONFIG_DM_USB 1014 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops) 1015 { 1016 struct ehci_ctrl *ctrl = &ehcic[index]; 1017 1018 ctrl->priv = priv; 1019 ehci_setup_ops(ctrl, ops); 1020 } 1021 1022 void *ehci_get_controller_priv(int index) 1023 { 1024 return ehcic[index].priv; 1025 } 1026 #endif 1027 1028 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks) 1029 { 1030 struct QH *qh_list; 1031 struct QH *periodic; 1032 uint32_t reg; 1033 uint32_t cmd; 1034 int i; 1035 1036 /* Set the high address word (aka segment) for 64-bit controller */ 1037 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1) 1038 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0); 1039 1040 qh_list = &ctrl->qh_list; 1041 1042 /* Set head of reclaim list */ 1043 memset(qh_list, 0, sizeof(*qh_list)); 1044 qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH); 1045 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | 1046 QH_ENDPT1_EPS(USB_SPEED_HIGH)); 1047 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 1048 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1049 qh_list->qh_overlay.qt_token = 1050 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); 1051 1052 flush_dcache_range((unsigned long)qh_list, 1053 ALIGN_END_ADDR(struct QH, qh_list, 1)); 1054 1055 /* Set async. queue head pointer. */ 1056 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list); 1057 1058 /* 1059 * Set up periodic list 1060 * Step 1: Parent QH for all periodic transfers. 1061 */ 1062 ctrl->periodic_schedules = 0; 1063 periodic = &ctrl->periodic_queue; 1064 memset(periodic, 0, sizeof(*periodic)); 1065 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 1066 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 1067 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1068 1069 flush_dcache_range((unsigned long)periodic, 1070 ALIGN_END_ADDR(struct QH, periodic, 1)); 1071 1072 /* 1073 * Step 2: Setup frame-list: Every microframe, USB tries the same list. 1074 * In particular, device specifications on polling frequency 1075 * are disregarded. Keyboards seem to send NAK/NYet reliably 1076 * when polled with an empty buffer. 1077 * 1078 * Split Transactions will be spread across microframes using 1079 * S-mask and C-mask. 1080 */ 1081 if (ctrl->periodic_list == NULL) 1082 ctrl->periodic_list = memalign(4096, 1024 * 4); 1083 1084 if (!ctrl->periodic_list) 1085 return -ENOMEM; 1086 for (i = 0; i < 1024; i++) { 1087 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic 1088 | QH_LINK_TYPE_QH); 1089 } 1090 1091 flush_dcache_range((unsigned long)ctrl->periodic_list, 1092 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list, 1093 1024)); 1094 1095 /* Set periodic list base address */ 1096 ehci_writel(&ctrl->hcor->or_periodiclistbase, 1097 (unsigned long)ctrl->periodic_list); 1098 1099 reg = ehci_readl(&ctrl->hccr->cr_hcsparams); 1100 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 1101 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 1102 /* Port Indicators */ 1103 if (HCS_INDICATOR(reg)) 1104 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1105 | 0x80, &descriptor.hub.wHubCharacteristics); 1106 /* Port Power Control */ 1107 if (HCS_PPC(reg)) 1108 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1109 | 0x01, &descriptor.hub.wHubCharacteristics); 1110 1111 /* Start the host controller. */ 1112 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 1113 /* 1114 * Philips, Intel, and maybe others need CMD_RUN before the 1115 * root hub will detect new devices (why?); NEC doesn't 1116 */ 1117 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 1118 cmd |= CMD_RUN; 1119 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 1120 1121 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) { 1122 /* take control over the ports */ 1123 cmd = ehci_readl(&ctrl->hcor->or_configflag); 1124 cmd |= FLAG_CF; 1125 ehci_writel(&ctrl->hcor->or_configflag, cmd); 1126 } 1127 1128 /* unblock posted write */ 1129 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 1130 mdelay(5); 1131 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase)); 1132 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 1133 1134 return 0; 1135 } 1136 1137 #ifndef CONFIG_DM_USB 1138 int usb_lowlevel_stop(int index) 1139 { 1140 ehci_shutdown(&ehcic[index]); 1141 return ehci_hcd_stop(index); 1142 } 1143 1144 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1145 { 1146 struct ehci_ctrl *ctrl = &ehcic[index]; 1147 uint tweaks = 0; 1148 int rc; 1149 1150 /** 1151 * Set ops to default_ehci_ops, ehci_hcd_init should call 1152 * ehci_set_controller_priv to change any of these function pointers. 1153 */ 1154 ctrl->ops = default_ehci_ops; 1155 1156 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); 1157 if (rc) 1158 return rc; 1159 if (init == USB_INIT_DEVICE) 1160 goto done; 1161 1162 /* EHCI spec section 4.1 */ 1163 if (ehci_reset(ctrl)) 1164 return -1; 1165 1166 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 1167 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); 1168 if (rc) 1169 return rc; 1170 #endif 1171 #ifdef CONFIG_USB_EHCI_FARADAY 1172 tweaks |= EHCI_TWEAK_NO_INIT_CF; 1173 #endif 1174 rc = ehci_common_init(ctrl, tweaks); 1175 if (rc) 1176 return rc; 1177 1178 ctrl->rootdev = 0; 1179 done: 1180 *controller = &ehcic[index]; 1181 return 0; 1182 } 1183 #endif 1184 1185 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 1186 void *buffer, int length) 1187 { 1188 1189 if (usb_pipetype(pipe) != PIPE_BULK) { 1190 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 1191 return -1; 1192 } 1193 return ehci_submit_async(dev, pipe, buffer, length, NULL); 1194 } 1195 1196 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe, 1197 void *buffer, int length, 1198 struct devrequest *setup) 1199 { 1200 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1201 1202 if (usb_pipetype(pipe) != PIPE_CONTROL) { 1203 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 1204 return -1; 1205 } 1206 1207 if (usb_pipedevice(pipe) == ctrl->rootdev) { 1208 if (!ctrl->rootdev) 1209 dev->speed = USB_SPEED_HIGH; 1210 return ehci_submit_root(dev, pipe, buffer, length, setup); 1211 } 1212 return ehci_submit_async(dev, pipe, buffer, length, setup); 1213 } 1214 1215 struct int_queue { 1216 int elementsize; 1217 struct QH *first; 1218 struct QH *current; 1219 struct QH *last; 1220 struct qTD *tds; 1221 }; 1222 1223 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f) 1224 1225 static int 1226 enable_periodic(struct ehci_ctrl *ctrl) 1227 { 1228 uint32_t cmd; 1229 struct ehci_hcor *hcor = ctrl->hcor; 1230 int ret; 1231 1232 cmd = ehci_readl(&hcor->or_usbcmd); 1233 cmd |= CMD_PSE; 1234 ehci_writel(&hcor->or_usbcmd, cmd); 1235 1236 ret = handshake((uint32_t *)&hcor->or_usbsts, 1237 STS_PSS, STS_PSS, 100 * 1000); 1238 if (ret < 0) { 1239 printf("EHCI failed: timeout when enabling periodic list\n"); 1240 return -ETIMEDOUT; 1241 } 1242 udelay(1000); 1243 return 0; 1244 } 1245 1246 static int 1247 disable_periodic(struct ehci_ctrl *ctrl) 1248 { 1249 uint32_t cmd; 1250 struct ehci_hcor *hcor = ctrl->hcor; 1251 int ret; 1252 1253 cmd = ehci_readl(&hcor->or_usbcmd); 1254 cmd &= ~CMD_PSE; 1255 ehci_writel(&hcor->or_usbcmd, cmd); 1256 1257 ret = handshake((uint32_t *)&hcor->or_usbsts, 1258 STS_PSS, 0, 100 * 1000); 1259 if (ret < 0) { 1260 printf("EHCI failed: timeout when disabling periodic list\n"); 1261 return -ETIMEDOUT; 1262 } 1263 return 0; 1264 } 1265 1266 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev, 1267 unsigned long pipe, int queuesize, int elementsize, 1268 void *buffer, int interval) 1269 { 1270 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1271 struct int_queue *result = NULL; 1272 int i; 1273 1274 /* 1275 * Interrupt transfers requiring several transactions are not supported 1276 * because bInterval is ignored. 1277 * 1278 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 1279 * <= PKT_ALIGN if several qTDs are required, while the USB 1280 * specification does not constrain this for interrupt transfers. That 1281 * means that ehci_submit_async() would support interrupt transfers 1282 * requiring several transactions only as long as the transfer size does 1283 * not require more than a single qTD. 1284 */ 1285 if (elementsize > usb_maxpacket(dev, pipe)) { 1286 printf("%s: xfers requiring several transactions are not supported.\n", 1287 __func__); 1288 return NULL; 1289 } 1290 1291 debug("Enter create_int_queue\n"); 1292 if (usb_pipetype(pipe) != PIPE_INTERRUPT) { 1293 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); 1294 return NULL; 1295 } 1296 1297 /* limit to 4 full pages worth of data - 1298 * we can safely fit them in a single TD, 1299 * no matter the alignment 1300 */ 1301 if (elementsize >= 16384) { 1302 debug("too large elements for interrupt transfers\n"); 1303 return NULL; 1304 } 1305 1306 result = malloc(sizeof(*result)); 1307 if (!result) { 1308 debug("ehci intr queue: out of memory\n"); 1309 goto fail1; 1310 } 1311 result->elementsize = elementsize; 1312 result->first = memalign(USB_DMA_MINALIGN, 1313 sizeof(struct QH) * queuesize); 1314 if (!result->first) { 1315 debug("ehci intr queue: out of memory\n"); 1316 goto fail2; 1317 } 1318 result->current = result->first; 1319 result->last = result->first + queuesize - 1; 1320 result->tds = memalign(USB_DMA_MINALIGN, 1321 sizeof(struct qTD) * queuesize); 1322 if (!result->tds) { 1323 debug("ehci intr queue: out of memory\n"); 1324 goto fail3; 1325 } 1326 memset(result->first, 0, sizeof(struct QH) * queuesize); 1327 memset(result->tds, 0, sizeof(struct qTD) * queuesize); 1328 1329 for (i = 0; i < queuesize; i++) { 1330 struct QH *qh = result->first + i; 1331 struct qTD *td = result->tds + i; 1332 void **buf = &qh->buffer; 1333 1334 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH); 1335 if (i == queuesize - 1) 1336 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 1337 1338 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td); 1339 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1340 qh->qh_endpt1 = 1341 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ 1342 (usb_maxpacket(dev, pipe) << 16) | /* MPS */ 1343 (1 << 14) | 1344 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 1345 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ 1346 (usb_pipedevice(pipe) << 0)); 1347 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ 1348 (1 << 0)); /* S-mask: microframe 0 */ 1349 if (dev->speed == USB_SPEED_LOW || 1350 dev->speed == USB_SPEED_FULL) { 1351 /* C-mask: microframes 2-4 */ 1352 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8)); 1353 } 1354 ehci_update_endpt2_dev_n_port(dev, qh); 1355 1356 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 1357 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1358 debug("communication direction is '%s'\n", 1359 usb_pipein(pipe) ? "in" : "out"); 1360 td->qt_token = cpu_to_hc32((elementsize << 16) | 1361 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ 1362 0x80); /* active */ 1363 td->qt_buffer[0] = 1364 cpu_to_hc32((unsigned long)buffer + i * elementsize); 1365 td->qt_buffer[1] = 1366 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff); 1367 td->qt_buffer[2] = 1368 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff); 1369 td->qt_buffer[3] = 1370 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff); 1371 td->qt_buffer[4] = 1372 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); 1373 1374 *buf = buffer + i * elementsize; 1375 } 1376 1377 flush_dcache_range((unsigned long)buffer, 1378 ALIGN_END_ADDR(char, buffer, 1379 queuesize * elementsize)); 1380 flush_dcache_range((unsigned long)result->first, 1381 ALIGN_END_ADDR(struct QH, result->first, 1382 queuesize)); 1383 flush_dcache_range((unsigned long)result->tds, 1384 ALIGN_END_ADDR(struct qTD, result->tds, 1385 queuesize)); 1386 1387 if (ctrl->periodic_schedules > 0) { 1388 if (disable_periodic(ctrl) < 0) { 1389 debug("FATAL: periodic should never fail, but did"); 1390 goto fail3; 1391 } 1392 } 1393 1394 /* hook up to periodic list */ 1395 struct QH *list = &ctrl->periodic_queue; 1396 result->last->qh_link = list->qh_link; 1397 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH); 1398 1399 flush_dcache_range((unsigned long)result->last, 1400 ALIGN_END_ADDR(struct QH, result->last, 1)); 1401 flush_dcache_range((unsigned long)list, 1402 ALIGN_END_ADDR(struct QH, list, 1)); 1403 1404 if (enable_periodic(ctrl) < 0) { 1405 debug("FATAL: periodic should never fail, but did"); 1406 goto fail3; 1407 } 1408 ctrl->periodic_schedules++; 1409 1410 debug("Exit create_int_queue\n"); 1411 return result; 1412 fail3: 1413 if (result->tds) 1414 free(result->tds); 1415 fail2: 1416 if (result->first) 1417 free(result->first); 1418 if (result) 1419 free(result); 1420 fail1: 1421 return NULL; 1422 } 1423 1424 static void *_ehci_poll_int_queue(struct usb_device *dev, 1425 struct int_queue *queue) 1426 { 1427 struct QH *cur = queue->current; 1428 struct qTD *cur_td; 1429 1430 /* depleted queue */ 1431 if (cur == NULL) { 1432 debug("Exit poll_int_queue with completed queue\n"); 1433 return NULL; 1434 } 1435 /* still active */ 1436 cur_td = &queue->tds[queue->current - queue->first]; 1437 invalidate_dcache_range((unsigned long)cur_td, 1438 ALIGN_END_ADDR(struct qTD, cur_td, 1)); 1439 if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) & 1440 QT_TOKEN_STATUS_ACTIVE) { 1441 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", 1442 hc32_to_cpu(cur_td->qt_token)); 1443 return NULL; 1444 } 1445 if (!(cur->qh_link & QH_LINK_TERMINATE)) 1446 queue->current++; 1447 else 1448 queue->current = NULL; 1449 1450 invalidate_dcache_range((unsigned long)cur->buffer, 1451 ALIGN_END_ADDR(char, cur->buffer, 1452 queue->elementsize)); 1453 1454 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n", 1455 hc32_to_cpu(cur_td->qt_token), cur, queue->first); 1456 return cur->buffer; 1457 } 1458 1459 /* Do not free buffers associated with QHs, they're owned by someone else */ 1460 static int _ehci_destroy_int_queue(struct usb_device *dev, 1461 struct int_queue *queue) 1462 { 1463 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1464 int result = -1; 1465 unsigned long timeout; 1466 1467 if (disable_periodic(ctrl) < 0) { 1468 debug("FATAL: periodic should never fail, but did"); 1469 goto out; 1470 } 1471 ctrl->periodic_schedules--; 1472 1473 struct QH *cur = &ctrl->periodic_queue; 1474 timeout = get_timer(0) + 500; /* abort after 500ms */ 1475 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { 1476 debug("considering %p, with qh_link %x\n", cur, cur->qh_link); 1477 if (NEXT_QH(cur) == queue->first) { 1478 debug("found candidate. removing from chain\n"); 1479 cur->qh_link = queue->last->qh_link; 1480 flush_dcache_range((unsigned long)cur, 1481 ALIGN_END_ADDR(struct QH, cur, 1)); 1482 result = 0; 1483 break; 1484 } 1485 cur = NEXT_QH(cur); 1486 if (get_timer(0) > timeout) { 1487 printf("Timeout destroying interrupt endpoint queue\n"); 1488 result = -1; 1489 goto out; 1490 } 1491 } 1492 1493 if (ctrl->periodic_schedules > 0) { 1494 result = enable_periodic(ctrl); 1495 if (result < 0) 1496 debug("FATAL: periodic should never fail, but did"); 1497 } 1498 1499 out: 1500 free(queue->tds); 1501 free(queue->first); 1502 free(queue); 1503 1504 return result; 1505 } 1506 1507 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, 1508 void *buffer, int length, int interval) 1509 { 1510 void *backbuffer; 1511 struct int_queue *queue; 1512 unsigned long timeout; 1513 int result = 0, ret; 1514 1515 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 1516 dev, pipe, buffer, length, interval); 1517 1518 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval); 1519 if (!queue) 1520 return -1; 1521 1522 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1523 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL) 1524 if (get_timer(0) > timeout) { 1525 printf("Timeout poll on interrupt endpoint\n"); 1526 result = -ETIMEDOUT; 1527 break; 1528 } 1529 1530 if (backbuffer != buffer) { 1531 debug("got wrong buffer back (%p instead of %p)\n", 1532 backbuffer, buffer); 1533 return -EINVAL; 1534 } 1535 1536 ret = _ehci_destroy_int_queue(dev, queue); 1537 if (ret < 0) 1538 return ret; 1539 1540 /* everything worked out fine */ 1541 return result; 1542 } 1543 1544 #ifndef CONFIG_DM_USB 1545 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 1546 void *buffer, int length) 1547 { 1548 return _ehci_submit_bulk_msg(dev, pipe, buffer, length); 1549 } 1550 1551 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1552 int length, struct devrequest *setup) 1553 { 1554 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup); 1555 } 1556 1557 int submit_int_msg(struct usb_device *dev, unsigned long pipe, 1558 void *buffer, int length, int interval) 1559 { 1560 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval); 1561 } 1562 1563 struct int_queue *create_int_queue(struct usb_device *dev, 1564 unsigned long pipe, int queuesize, int elementsize, 1565 void *buffer, int interval) 1566 { 1567 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize, 1568 buffer, interval); 1569 } 1570 1571 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) 1572 { 1573 return _ehci_poll_int_queue(dev, queue); 1574 } 1575 1576 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) 1577 { 1578 return _ehci_destroy_int_queue(dev, queue); 1579 } 1580 #endif 1581 1582 #ifdef CONFIG_DM_USB 1583 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1584 unsigned long pipe, void *buffer, int length, 1585 struct devrequest *setup) 1586 { 1587 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1588 dev->name, udev, udev->dev->name, udev->portnr); 1589 1590 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup); 1591 } 1592 1593 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1594 unsigned long pipe, void *buffer, int length) 1595 { 1596 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1597 return _ehci_submit_bulk_msg(udev, pipe, buffer, length); 1598 } 1599 1600 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1601 unsigned long pipe, void *buffer, int length, 1602 int interval) 1603 { 1604 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1605 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval); 1606 } 1607 1608 static struct int_queue *ehci_create_int_queue(struct udevice *dev, 1609 struct usb_device *udev, unsigned long pipe, int queuesize, 1610 int elementsize, void *buffer, int interval) 1611 { 1612 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1613 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize, 1614 buffer, interval); 1615 } 1616 1617 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev, 1618 struct int_queue *queue) 1619 { 1620 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1621 return _ehci_poll_int_queue(udev, queue); 1622 } 1623 1624 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, 1625 struct int_queue *queue) 1626 { 1627 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1628 return _ehci_destroy_int_queue(udev, queue); 1629 } 1630 1631 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, 1632 struct ehci_hcor *hcor, const struct ehci_ops *ops, 1633 uint tweaks, enum usb_init_type init) 1634 { 1635 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 1636 struct ehci_ctrl *ctrl = dev_get_priv(dev); 1637 int ret; 1638 1639 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__, 1640 dev->name, ctrl, hccr, hcor, init); 1641 1642 priv->desc_before_addr = true; 1643 1644 ehci_setup_ops(ctrl, ops); 1645 ctrl->hccr = hccr; 1646 ctrl->hcor = hcor; 1647 ctrl->priv = ctrl; 1648 1649 if (init == USB_INIT_DEVICE) 1650 goto done; 1651 ret = ehci_reset(ctrl); 1652 if (ret) 1653 goto err; 1654 1655 ret = ehci_common_init(ctrl, tweaks); 1656 if (ret) 1657 goto err; 1658 done: 1659 return 0; 1660 err: 1661 free(ctrl); 1662 debug("%s: failed, ret=%d\n", __func__, ret); 1663 return ret; 1664 } 1665 1666 int ehci_deregister(struct udevice *dev) 1667 { 1668 struct ehci_ctrl *ctrl = dev_get_priv(dev); 1669 1670 ehci_shutdown(ctrl); 1671 1672 return 0; 1673 } 1674 1675 struct dm_usb_ops ehci_usb_ops = { 1676 .control = ehci_submit_control_msg, 1677 .bulk = ehci_submit_bulk_msg, 1678 .interrupt = ehci_submit_int_msg, 1679 .create_int_queue = ehci_create_int_queue, 1680 .poll_int_queue = ehci_poll_int_queue, 1681 .destroy_int_queue = ehci_destroy_int_queue, 1682 }; 1683 1684 #endif 1685