1 /* 2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB 5 * 6 * Author: Tor Krill tor@excito.com 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <pci.h> 13 #include <usb.h> 14 #include <asm/io.h> 15 #include <usb/ehci-ci.h> 16 #include <hwconfig.h> 17 #include <fsl_usb.h> 18 #include <fdt_support.h> 19 20 #include "ehci.h" 21 22 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 23 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 24 #endif 25 26 static void set_txfifothresh(struct usb_ehci *, u32); 27 28 /* Check USB PHY clock valid */ 29 static int usb_phy_clk_valid(struct usb_ehci *ehci) 30 { 31 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) || 32 in_be32(&ehci->prictrl))) { 33 printf("USB PHY clock invalid!\n"); 34 return 0; 35 } else { 36 return 1; 37 } 38 } 39 40 /* 41 * Create the appropriate control structures to manage 42 * a new EHCI host controller. 43 * 44 * Excerpts from linux ehci fsl driver. 45 */ 46 int ehci_hcd_init(int index, enum usb_init_type init, 47 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 48 { 49 struct usb_ehci *ehci = NULL; 50 const char *phy_type = NULL; 51 size_t len; 52 char current_usb_controller[5]; 53 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 54 char usb_phy[5]; 55 56 usb_phy[0] = '\0'; 57 #endif 58 if (has_erratum_a007075()) { 59 /* 60 * A 5ms delay is needed after applying soft-reset to the 61 * controller to let external ULPI phy come out of reset. 62 * This delay needs to be added before re-initializing 63 * the controller after soft-resetting completes 64 */ 65 mdelay(5); 66 } 67 memset(current_usb_controller, '\0', 5); 68 snprintf(current_usb_controller, 4, "usb%d", index+1); 69 70 switch (index) { 71 case 0: 72 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; 73 break; 74 case 1: 75 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; 76 break; 77 default: 78 printf("ERROR: wrong controller index!!\n"); 79 return -EINVAL; 80 }; 81 82 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 83 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 84 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 85 86 /* Set to Host mode */ 87 setbits_le32(&ehci->usbmode, CM_HOST); 88 89 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB); 90 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); 91 92 /* Init phy */ 93 if (hwconfig_sub(current_usb_controller, "phy_type")) 94 phy_type = hwconfig_subarg(current_usb_controller, 95 "phy_type", &len); 96 else 97 phy_type = getenv("usb_phy_type"); 98 99 if (!phy_type) { 100 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 101 /* if none specified assume internal UTMI */ 102 strcpy(usb_phy, "utmi"); 103 phy_type = usb_phy; 104 #else 105 printf("WARNING: USB phy type not defined !!\n"); 106 return -1; 107 #endif 108 } 109 110 if (!strncmp(phy_type, "utmi", 4)) { 111 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) 112 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 113 PHY_CLK_SEL_UTMI); 114 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 115 UTMI_PHY_EN); 116 udelay(1000); /* delay required for PHY Clk to appear */ 117 #endif 118 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); 119 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 120 USB_EN); 121 } else { 122 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 123 PHY_CLK_SEL_ULPI); 124 clrsetbits_be32(&ehci->control, UTMI_PHY_EN | 125 CONTROL_REGISTER_W1C_MASK, USB_EN); 126 udelay(1000); /* delay required for PHY Clk to appear */ 127 if (!usb_phy_clk_valid(ehci)) 128 return -EINVAL; 129 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); 130 } 131 132 out_be32(&ehci->prictrl, 0x0000000c); 133 out_be32(&ehci->age_cnt_limit, 0x00000040); 134 out_be32(&ehci->sictrl, 0x00000001); 135 136 in_le32(&ehci->usbmode); 137 138 if (has_erratum_a007798()) 139 set_txfifothresh(ehci, TXFIFOTHRESH); 140 141 if (has_erratum_a004477()) { 142 /* 143 * When reset is issued while any ULPI transaction is ongoing 144 * then it may result to corruption of ULPI Function Control 145 * Register which eventually causes phy clock to enter low 146 * power mode which stops the clock. Thus delay is required 147 * before reset to let ongoing ULPI transaction complete. 148 */ 149 udelay(1); 150 } 151 return 0; 152 } 153 154 /* 155 * Destroy the appropriate control structures corresponding 156 * the the EHCI host controller. 157 */ 158 int ehci_hcd_stop(int index) 159 { 160 return 0; 161 } 162 163 /* 164 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register 165 * to counter DDR latencies in writing data into Tx buffer. 166 * This prevents Tx buffer from getting underrun 167 */ 168 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) 169 { 170 u32 cmd; 171 cmd = ehci_readl(&ehci->txfilltuning); 172 cmd &= ~TXFIFO_THRESH_MASK; 173 cmd |= TXFIFO_THRESH(txfifo_thresh); 174 ehci_writel(&ehci->txfilltuning, cmd); 175 } 176