1 /* 2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB 5 * 6 * Author: Tor Krill tor@excito.com 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <pci.h> 13 #include <usb.h> 14 #include <asm/io.h> 15 #include <usb/ehci-fsl.h> 16 #include <hwconfig.h> 17 #include <asm/fsl_errata.h> 18 19 #include "ehci.h" 20 21 static void set_txfifothresh(struct usb_ehci *, u32); 22 23 /* Check USB PHY clock valid */ 24 static int usb_phy_clk_valid(struct usb_ehci *ehci) 25 { 26 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) || 27 in_be32(&ehci->prictrl))) { 28 printf("USB PHY clock invalid!\n"); 29 return 0; 30 } else { 31 return 1; 32 } 33 } 34 35 /* 36 * Create the appropriate control structures to manage 37 * a new EHCI host controller. 38 * 39 * Excerpts from linux ehci fsl driver. 40 */ 41 int ehci_hcd_init(int index, enum usb_init_type init, 42 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 43 { 44 struct usb_ehci *ehci = NULL; 45 const char *phy_type = NULL; 46 size_t len; 47 char current_usb_controller[5]; 48 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 49 char usb_phy[5]; 50 51 usb_phy[0] = '\0'; 52 #endif 53 if (has_erratum_a007075()) { 54 /* 55 * A 5ms delay is needed after applying soft-reset to the 56 * controller to let external ULPI phy come out of reset. 57 * This delay needs to be added before re-initializing 58 * the controller after soft-resetting completes 59 */ 60 mdelay(5); 61 } 62 memset(current_usb_controller, '\0', 5); 63 snprintf(current_usb_controller, 4, "usb%d", index+1); 64 65 switch (index) { 66 case 0: 67 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; 68 break; 69 case 1: 70 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; 71 break; 72 default: 73 printf("ERROR: wrong controller index!!\n"); 74 break; 75 }; 76 77 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 78 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 79 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 80 81 /* Set to Host mode */ 82 setbits_le32(&ehci->usbmode, CM_HOST); 83 84 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB); 85 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); 86 87 /* Init phy */ 88 if (hwconfig_sub(current_usb_controller, "phy_type")) 89 phy_type = hwconfig_subarg(current_usb_controller, 90 "phy_type", &len); 91 else 92 phy_type = getenv("usb_phy_type"); 93 94 if (!phy_type) { 95 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 96 /* if none specified assume internal UTMI */ 97 strcpy(usb_phy, "utmi"); 98 phy_type = usb_phy; 99 #else 100 printf("WARNING: USB phy type not defined !!\n"); 101 return -1; 102 #endif 103 } 104 105 if (!strncmp(phy_type, "utmi", 4)) { 106 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) 107 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 108 PHY_CLK_SEL_UTMI); 109 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 110 UTMI_PHY_EN); 111 udelay(1000); /* delay required for PHY Clk to appear */ 112 #endif 113 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); 114 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 115 USB_EN); 116 } else { 117 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 118 PHY_CLK_SEL_ULPI); 119 clrsetbits_be32(&ehci->control, UTMI_PHY_EN | 120 CONTROL_REGISTER_W1C_MASK, USB_EN); 121 udelay(1000); /* delay required for PHY Clk to appear */ 122 if (!usb_phy_clk_valid(ehci)) 123 return -EINVAL; 124 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); 125 } 126 127 out_be32(&ehci->prictrl, 0x0000000c); 128 out_be32(&ehci->age_cnt_limit, 0x00000040); 129 out_be32(&ehci->sictrl, 0x00000001); 130 131 in_le32(&ehci->usbmode); 132 133 if (SVR_SOC_VER(get_svr()) == SVR_T4240 && 134 IS_SVR_REV(get_svr(), 2, 0)) 135 set_txfifothresh(ehci, TXFIFOTHRESH); 136 137 return 0; 138 } 139 140 /* 141 * Destroy the appropriate control structures corresponding 142 * the the EHCI host controller. 143 */ 144 int ehci_hcd_stop(int index) 145 { 146 return 0; 147 } 148 149 /* 150 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register 151 * to counter DDR latencies in writing data into Tx buffer. 152 * This prevents Tx buffer from getting underrun 153 */ 154 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) 155 { 156 u32 cmd; 157 cmd = ehci_readl(&ehci->txfilltuning); 158 cmd &= ~TXFIFO_THRESH_MASK; 159 cmd |= TXFIFO_THRESH(txfifo_thresh); 160 ehci_writel(&ehci->txfilltuning, cmd); 161 } 162