1 /* 2 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB 3 * 4 * Author: Tor Krill tor@excito.com 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include <common.h> 23 #include <pci.h> 24 #include <usb.h> 25 #include <mpc83xx.h> 26 #include <asm/io.h> 27 #include <asm/bitops.h> 28 29 #include "ehci.h" 30 #include "ehci-fsl.h" 31 #include "ehci-core.h" 32 33 /* 34 * Create the appropriate control structures to manage 35 * a new EHCI host controller. 36 * 37 * Excerpts from linux ehci fsl driver. 38 */ 39 int ehci_hcd_init(void) 40 { 41 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 42 uint32_t addr, temp; 43 44 addr = (uint32_t)&(im->usb[0]); 45 hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI); 46 hcor = (struct ehci_hcor *)((uint32_t) hccr + 47 HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 48 49 /* Configure clock */ 50 clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK, 51 MPC83XX_SCCR_USB_DRCM_11); 52 53 /* Confgure interface. */ 54 temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); 55 out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp 56 | REFSEL_16MHZ | UTMI_PHY_EN); 57 58 /* Wait for clock to stabilize */ 59 do { 60 temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); 61 udelay(1000); 62 } while (!(temp & PHY_CLK_VALID)); 63 64 /* Set to Host mode */ 65 temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE)); 66 out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST); 67 68 out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB); 69 out_be32((void *)(addr + FSL_SOC_USB_SNOOP2), 70 0x80000000 | SNOOP_SIZE_2GB); 71 72 /* Init phy */ 73 /* TODO: handle different phys? */ 74 out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); 75 76 /* Enable interface. */ 77 temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); 78 out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN); 79 80 out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c); 81 out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040); 82 out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001); 83 84 /* Enable interface. */ 85 temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); 86 out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN); 87 88 temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE)); 89 90 return 0; 91 } 92 93 /* 94 * Destroy the appropriate control structures corresponding 95 * the the EHCI host controller. 96 */ 97 int ehci_hcd_stop(void) 98 { 99 return 0; 100 } 101