1 /* 2 * SAMSUNG EXYNOS USB HOST EHCI Controller 3 * 4 * Copyright (C) 2012 Samsung Electronics Co.Ltd 5 * Vivek Gautam <gautam.vivek@samsung.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <fdtdec.h> 12 #include <libfdt.h> 13 #include <malloc.h> 14 #include <usb.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/ehci.h> 17 #include <asm/arch/system.h> 18 #include <asm/arch/power.h> 19 #include <asm/gpio.h> 20 #include <asm-generic/errno.h> 21 #include <linux/compat.h> 22 #include "ehci.h" 23 24 /* Declare global data pointer */ 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /** 28 * Contains pointers to register base addresses 29 * for the usb controller. 30 */ 31 struct exynos_ehci { 32 struct exynos_usb_phy *usb; 33 struct ehci_hccr *hcd; 34 struct gpio_desc vbus_gpio; 35 }; 36 37 static struct exynos_ehci exynos; 38 39 #ifdef CONFIG_OF_CONTROL 40 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) 41 { 42 fdt_addr_t addr; 43 unsigned int node; 44 int depth; 45 46 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI); 47 if (node <= 0) { 48 debug("EHCI: Can't get device node for ehci\n"); 49 return -ENODEV; 50 } 51 52 /* 53 * Get the base address for EHCI controller from the device node 54 */ 55 addr = fdtdec_get_addr(blob, node, "reg"); 56 if (addr == FDT_ADDR_T_NONE) { 57 debug("Can't get the EHCI register address\n"); 58 return -ENXIO; 59 } 60 61 exynos->hcd = (struct ehci_hccr *)addr; 62 63 /* Vbus gpio */ 64 gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0, 65 &exynos->vbus_gpio, GPIOD_IS_OUT); 66 67 depth = 0; 68 node = fdtdec_next_compatible_subnode(blob, node, 69 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth); 70 if (node <= 0) { 71 debug("EHCI: Can't get device node for usb-phy controller\n"); 72 return -ENODEV; 73 } 74 75 /* 76 * Get the base address for usbphy from the device node 77 */ 78 exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node, 79 "reg"); 80 if (exynos->usb == NULL) { 81 debug("Can't get the usbphy register address\n"); 82 return -ENXIO; 83 } 84 85 return 0; 86 } 87 #endif 88 89 static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb) 90 { 91 u32 hsic_ctrl; 92 93 clrbits_le32(&usb->usbphyctrl0, 94 HOST_CTRL0_FSEL_MASK | 95 HOST_CTRL0_COMMONON_N | 96 /* HOST Phy setting */ 97 HOST_CTRL0_PHYSWRST | 98 HOST_CTRL0_PHYSWRSTALL | 99 HOST_CTRL0_SIDDQ | 100 HOST_CTRL0_FORCESUSPEND | 101 HOST_CTRL0_FORCESLEEP); 102 103 setbits_le32(&usb->usbphyctrl0, 104 /* Setting up the ref freq */ 105 (CLK_24MHZ << 16) | 106 /* HOST Phy setting */ 107 HOST_CTRL0_LINKSWRST | 108 HOST_CTRL0_UTMISWRST); 109 udelay(10); 110 clrbits_le32(&usb->usbphyctrl0, 111 HOST_CTRL0_LINKSWRST | 112 HOST_CTRL0_UTMISWRST); 113 114 /* HSIC Phy Setting */ 115 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | 116 HSIC_CTRL_FORCESLEEP | 117 HSIC_CTRL_SIDDQ); 118 119 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); 120 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); 121 122 hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK) 123 << HSIC_CTRL_REFCLKDIV_SHIFT) 124 | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK) 125 << HSIC_CTRL_REFCLKSEL_SHIFT) 126 | HSIC_CTRL_UTMISWRST); 127 128 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); 129 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); 130 131 udelay(10); 132 133 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | 134 HSIC_CTRL_UTMISWRST); 135 136 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | 137 HSIC_CTRL_UTMISWRST); 138 139 udelay(20); 140 141 /* EHCI Ctrl setting */ 142 setbits_le32(&usb->ehcictrl, 143 EHCICTRL_ENAINCRXALIGN | 144 EHCICTRL_ENAINCR4 | 145 EHCICTRL_ENAINCR8 | 146 EHCICTRL_ENAINCR16); 147 } 148 149 static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb) 150 { 151 writel(CLK_24MHZ, &usb->usbphyclk); 152 153 clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | 154 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 | 155 PHYPWR_NORMAL_MASK_PHY0)); 156 157 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); 158 udelay(10); 159 clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); 160 } 161 162 static void setup_usb_phy(struct exynos_usb_phy *usb) 163 { 164 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); 165 166 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); 167 168 if (cpu_is_exynos5()) 169 exynos5_setup_usb_phy(usb); 170 else if (cpu_is_exynos4()) 171 if (proid_is_exynos4412()) 172 exynos4412_setup_usb_phy((struct exynos4412_usb_phy *) 173 usb); 174 } 175 176 static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb) 177 { 178 u32 hsic_ctrl; 179 180 /* HOST_PHY reset */ 181 setbits_le32(&usb->usbphyctrl0, 182 HOST_CTRL0_PHYSWRST | 183 HOST_CTRL0_PHYSWRSTALL | 184 HOST_CTRL0_SIDDQ | 185 HOST_CTRL0_FORCESUSPEND | 186 HOST_CTRL0_FORCESLEEP); 187 188 /* HSIC Phy reset */ 189 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | 190 HSIC_CTRL_FORCESLEEP | 191 HSIC_CTRL_SIDDQ | 192 HSIC_CTRL_PHYSWRST); 193 194 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); 195 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); 196 } 197 198 static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb) 199 { 200 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | 201 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 | 202 PHYPWR_NORMAL_MASK_PHY0)); 203 } 204 205 /* Reset the EHCI host controller. */ 206 static void reset_usb_phy(struct exynos_usb_phy *usb) 207 { 208 if (cpu_is_exynos5()) 209 exynos5_reset_usb_phy(usb); 210 else if (cpu_is_exynos4()) 211 if (proid_is_exynos4412()) 212 exynos4412_reset_usb_phy((struct exynos4412_usb_phy *) 213 usb); 214 215 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); 216 } 217 218 /* 219 * EHCI-initialization 220 * Create the appropriate control structures to manage 221 * a new EHCI host controller. 222 */ 223 int ehci_hcd_init(int index, enum usb_init_type init, 224 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 225 { 226 struct exynos_ehci *ctx = &exynos; 227 228 #ifdef CONFIG_OF_CONTROL 229 if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) { 230 debug("Unable to parse device tree for ehci-exynos\n"); 231 return -ENODEV; 232 } 233 #else 234 ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); 235 ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci(); 236 #endif 237 238 #ifdef CONFIG_OF_CONTROL 239 /* setup the Vbus gpio here */ 240 if (dm_gpio_is_valid(&ctx->vbus_gpio)) 241 dm_gpio_set_value(&ctx->vbus_gpio, 1); 242 #endif 243 244 setup_usb_phy(ctx->usb); 245 246 board_usb_init(index, init); 247 248 *hccr = ctx->hcd; 249 *hcor = (struct ehci_hcor *)((uint32_t) *hccr 250 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 251 252 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", 253 (uint32_t)*hccr, (uint32_t)*hcor, 254 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 255 256 return 0; 257 } 258 259 /* 260 * Destroy the appropriate control structures corresponding 261 * the EHCI host controller. 262 */ 263 int ehci_hcd_stop(int index) 264 { 265 struct exynos_ehci *ctx = &exynos; 266 267 reset_usb_phy(ctx->usb); 268 269 return 0; 270 } 271