1 /* 2 * SAMSUNG EXYNOS USB HOST EHCI Controller 3 * 4 * Copyright (C) 2012 Samsung Electronics Co.Ltd 5 * Vivek Gautam <gautam.vivek@samsung.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <fdtdec.h> 12 #include <libfdt.h> 13 #include <malloc.h> 14 #include <usb.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/ehci.h> 17 #include <asm/arch/system.h> 18 #include <asm/arch/power.h> 19 #include <asm/gpio.h> 20 #include <asm-generic/errno.h> 21 #include <linux/compat.h> 22 #include "ehci.h" 23 24 /* Declare global data pointer */ 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /** 28 * Contains pointers to register base addresses 29 * for the usb controller. 30 */ 31 struct exynos_ehci { 32 struct exynos_usb_phy *usb; 33 struct ehci_hccr *hcd; 34 struct fdt_gpio_state vbus_gpio; 35 }; 36 37 static struct exynos_ehci exynos; 38 39 #ifdef CONFIG_OF_CONTROL 40 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) 41 { 42 fdt_addr_t addr; 43 unsigned int node; 44 int depth; 45 46 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI); 47 if (node <= 0) { 48 debug("EHCI: Can't get device node for ehci\n"); 49 return -ENODEV; 50 } 51 52 /* 53 * Get the base address for EHCI controller from the device node 54 */ 55 addr = fdtdec_get_addr(blob, node, "reg"); 56 if (addr == FDT_ADDR_T_NONE) { 57 debug("Can't get the EHCI register address\n"); 58 return -ENXIO; 59 } 60 61 exynos->hcd = (struct ehci_hccr *)addr; 62 63 /* Vbus gpio */ 64 fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio); 65 66 depth = 0; 67 node = fdtdec_next_compatible_subnode(blob, node, 68 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth); 69 if (node <= 0) { 70 debug("EHCI: Can't get device node for usb-phy controller\n"); 71 return -ENODEV; 72 } 73 74 /* 75 * Get the base address for usbphy from the device node 76 */ 77 exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node, 78 "reg"); 79 if (exynos->usb == NULL) { 80 debug("Can't get the usbphy register address\n"); 81 return -ENXIO; 82 } 83 84 return 0; 85 } 86 #endif 87 88 /* Setup the EHCI host controller. */ 89 static void setup_usb_phy(struct exynos_usb_phy *usb) 90 { 91 u32 hsic_ctrl; 92 93 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); 94 95 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); 96 97 clrbits_le32(&usb->usbphyctrl0, 98 HOST_CTRL0_FSEL_MASK | 99 HOST_CTRL0_COMMONON_N | 100 /* HOST Phy setting */ 101 HOST_CTRL0_PHYSWRST | 102 HOST_CTRL0_PHYSWRSTALL | 103 HOST_CTRL0_SIDDQ | 104 HOST_CTRL0_FORCESUSPEND | 105 HOST_CTRL0_FORCESLEEP); 106 107 setbits_le32(&usb->usbphyctrl0, 108 /* Setting up the ref freq */ 109 (CLK_24MHZ << 16) | 110 /* HOST Phy setting */ 111 HOST_CTRL0_LINKSWRST | 112 HOST_CTRL0_UTMISWRST); 113 udelay(10); 114 clrbits_le32(&usb->usbphyctrl0, 115 HOST_CTRL0_LINKSWRST | 116 HOST_CTRL0_UTMISWRST); 117 118 /* HSIC Phy Setting */ 119 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | 120 HSIC_CTRL_FORCESLEEP | 121 HSIC_CTRL_SIDDQ); 122 123 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); 124 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); 125 126 hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK) 127 << HSIC_CTRL_REFCLKDIV_SHIFT) 128 | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK) 129 << HSIC_CTRL_REFCLKSEL_SHIFT) 130 | HSIC_CTRL_UTMISWRST); 131 132 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); 133 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); 134 135 udelay(10); 136 137 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | 138 HSIC_CTRL_UTMISWRST); 139 140 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | 141 HSIC_CTRL_UTMISWRST); 142 143 udelay(20); 144 145 /* EHCI Ctrl setting */ 146 setbits_le32(&usb->ehcictrl, 147 EHCICTRL_ENAINCRXALIGN | 148 EHCICTRL_ENAINCR4 | 149 EHCICTRL_ENAINCR8 | 150 EHCICTRL_ENAINCR16); 151 } 152 153 /* Reset the EHCI host controller. */ 154 static void reset_usb_phy(struct exynos_usb_phy *usb) 155 { 156 u32 hsic_ctrl; 157 158 /* HOST_PHY reset */ 159 setbits_le32(&usb->usbphyctrl0, 160 HOST_CTRL0_PHYSWRST | 161 HOST_CTRL0_PHYSWRSTALL | 162 HOST_CTRL0_SIDDQ | 163 HOST_CTRL0_FORCESUSPEND | 164 HOST_CTRL0_FORCESLEEP); 165 166 /* HSIC Phy reset */ 167 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | 168 HSIC_CTRL_FORCESLEEP | 169 HSIC_CTRL_SIDDQ | 170 HSIC_CTRL_PHYSWRST); 171 172 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); 173 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); 174 175 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); 176 } 177 178 /* 179 * EHCI-initialization 180 * Create the appropriate control structures to manage 181 * a new EHCI host controller. 182 */ 183 int ehci_hcd_init(int index, enum usb_init_type init, 184 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 185 { 186 struct exynos_ehci *ctx = &exynos; 187 188 #ifdef CONFIG_OF_CONTROL 189 if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) { 190 debug("Unable to parse device tree for ehci-exynos\n"); 191 return -ENODEV; 192 } 193 #else 194 ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); 195 ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci(); 196 #endif 197 198 #ifdef CONFIG_OF_CONTROL 199 /* setup the Vbus gpio here */ 200 if (!fdtdec_setup_gpio(&ctx->vbus_gpio)) 201 gpio_direction_output(ctx->vbus_gpio.gpio, 1); 202 #endif 203 204 setup_usb_phy(ctx->usb); 205 206 board_usb_init(index, init); 207 208 *hccr = ctx->hcd; 209 *hcor = (struct ehci_hcor *)((uint32_t) *hccr 210 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 211 212 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", 213 (uint32_t)*hccr, (uint32_t)*hcor, 214 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 215 216 return 0; 217 } 218 219 /* 220 * Destroy the appropriate control structures corresponding 221 * the EHCI host controller. 222 */ 223 int ehci_hcd_stop(int index) 224 { 225 struct exynos_ehci *ctx = &exynos; 226 227 reset_usb_phy(ctx->usb); 228 229 return 0; 230 } 231