1 /* 2 * (C) Copyright 2012 3 * Atmel Semiconductor <www.atmel.com> 4 * Written-by: Bo Shen <voice.shen@atmel.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <usb.h> 13 #include <asm/io.h> 14 #include <asm/arch/clk.h> 15 16 #include "ehci.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #ifndef CONFIG_DM_USB 21 22 int ehci_hcd_init(int index, enum usb_init_type init, 23 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 24 { 25 /* Enable UTMI PLL */ 26 if (at91_upll_clk_enable()) 27 return -1; 28 29 /* Enable USB Host clock */ 30 at91_periph_clk_enable(ATMEL_ID_UHPHS); 31 32 *hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI; 33 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 34 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 35 36 return 0; 37 } 38 39 int ehci_hcd_stop(int index) 40 { 41 /* Disable USB Host Clock */ 42 at91_periph_clk_disable(ATMEL_ID_UHPHS); 43 44 /* Disable UTMI PLL */ 45 if (at91_upll_clk_disable()) 46 return -1; 47 48 return 0; 49 } 50 51 #else 52 53 struct ehci_atmel_priv { 54 struct ehci_ctrl ehci; 55 }; 56 57 static int ehci_atmel_enable_clk(struct udevice *dev) 58 { 59 struct udevice *dev_clk; 60 struct clk clk; 61 int periph; 62 int ret; 63 64 ret = clk_get_by_index(dev, 0, &clk); 65 if (ret) 66 return ret; 67 68 ret = clk_enable(&clk); 69 if (ret) 70 return ret; 71 72 ret = clk_get_by_index(dev, 1, &clk); 73 if (ret) 74 return -EINVAL; 75 76 periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); 77 if (periph < 0) 78 return -EINVAL; 79 80 dev_clk = dev_get_parent(clk.dev); 81 if (!dev_clk) 82 return -ENODEV; 83 84 ret = clk_request(dev_clk, &clk); 85 if (ret) 86 return ret; 87 88 clk.id = periph; 89 ret = clk_enable(&clk); 90 if (ret) 91 return ret; 92 93 clk_free(&clk); 94 95 return 0; 96 } 97 98 static int ehci_atmel_probe(struct udevice *dev) 99 { 100 struct ehci_hccr *hccr; 101 struct ehci_hcor *hcor; 102 fdt_addr_t hcd_base; 103 int ret; 104 105 ret = ehci_atmel_enable_clk(dev); 106 if (ret) { 107 debug("Failed to enable USB Host clock\n"); 108 return ret; 109 } 110 111 /* 112 * Get the base address for EHCI controller from the device node 113 */ 114 hcd_base = dev_get_addr(dev); 115 if (hcd_base == FDT_ADDR_T_NONE) { 116 debug("Can't get the EHCI register base address\n"); 117 return -ENXIO; 118 } 119 120 hccr = (struct ehci_hccr *)hcd_base; 121 hcor = (struct ehci_hcor *) 122 ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 123 124 debug("echi-atmel: init hccr %x and hcor %x hc_length %d\n", 125 (u32)hccr, (u32)hcor, 126 (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 127 128 return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); 129 } 130 131 static const struct udevice_id ehci_usb_ids[] = { 132 { .compatible = "atmel,at91sam9g45-ehci", }, 133 { } 134 }; 135 136 U_BOOT_DRIVER(ehci_atmel) = { 137 .name = "ehci_atmel", 138 .id = UCLASS_USB, 139 .of_match = ehci_usb_ids, 140 .probe = ehci_atmel_probe, 141 .remove = ehci_deregister, 142 .ops = &ehci_usb_ops, 143 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 144 .priv_auto_alloc_size = sizeof(struct ehci_atmel_priv), 145 .flags = DM_FLAG_ALLOC_PRIV_DMA, 146 }; 147 148 #endif 149