1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <usb.h> 12 #include <malloc.h> 13 #include <phys2bus.h> 14 #include <usbroothubdes.h> 15 #include <asm/io.h> 16 17 #include "dwc2.h" 18 19 /* Use only HC channel 0. */ 20 #define DWC2_HC_CHANNEL 0 21 22 #define DWC2_STATUS_BUF_SIZE 64 23 #define DWC2_DATA_BUF_SIZE (64 * 1024) 24 25 #define MAX_DEVICE 16 26 #define MAX_ENDPOINT 16 27 28 struct dwc2_priv { 29 #ifdef CONFIG_DM_USB 30 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 31 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 32 #else 33 uint8_t *aligned_buffer; 34 uint8_t *status_buffer; 35 #endif 36 int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 37 struct dwc2_core_regs *regs; 38 int root_hub_devnum; 39 }; 40 41 #ifndef CONFIG_DM_USB 42 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 43 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 44 ARCH_DMA_MINALIGN); 45 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 46 ARCH_DMA_MINALIGN); 47 48 static struct dwc2_priv local; 49 #endif 50 51 /* 52 * DWC2 IP interface 53 */ 54 static int wait_for_bit(void *reg, const uint32_t mask, bool set) 55 { 56 unsigned int timeout = 1000000; 57 uint32_t val; 58 59 while (--timeout) { 60 val = readl(reg); 61 if (!set) 62 val = ~val; 63 64 if ((val & mask) == mask) 65 return 0; 66 67 udelay(1); 68 } 69 70 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 71 __func__, reg, mask, set); 72 73 return -ETIMEDOUT; 74 } 75 76 /* 77 * Initializes the FSLSPClkSel field of the HCFG register 78 * depending on the PHY type. 79 */ 80 static void init_fslspclksel(struct dwc2_core_regs *regs) 81 { 82 uint32_t phyclk; 83 84 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 85 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 86 #else 87 /* High speed PHY running at full speed or high speed */ 88 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 89 #endif 90 91 #ifdef CONFIG_DWC2_ULPI_FS_LS 92 uint32_t hwcfg2 = readl(®s->ghwcfg2); 93 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 94 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 95 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 96 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 97 98 if (hval == 2 && fval == 1) 99 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 100 #endif 101 102 clrsetbits_le32(®s->host_regs.hcfg, 103 DWC2_HCFG_FSLSPCLKSEL_MASK, 104 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 105 } 106 107 /* 108 * Flush a Tx FIFO. 109 * 110 * @param regs Programming view of DWC_otg controller. 111 * @param num Tx FIFO to flush. 112 */ 113 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 114 { 115 int ret; 116 117 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 118 ®s->grstctl); 119 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0); 120 if (ret) 121 printf("%s: Timeout!\n", __func__); 122 123 /* Wait for 3 PHY Clocks */ 124 udelay(1); 125 } 126 127 /* 128 * Flush Rx FIFO. 129 * 130 * @param regs Programming view of DWC_otg controller. 131 */ 132 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 133 { 134 int ret; 135 136 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 137 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0); 138 if (ret) 139 printf("%s: Timeout!\n", __func__); 140 141 /* Wait for 3 PHY Clocks */ 142 udelay(1); 143 } 144 145 /* 146 * Do core a soft reset of the core. Be careful with this because it 147 * resets all the internal state machines of the core. 148 */ 149 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 150 { 151 int ret; 152 153 /* Wait for AHB master IDLE state. */ 154 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1); 155 if (ret) 156 printf("%s: Timeout!\n", __func__); 157 158 /* Core Soft Reset */ 159 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 160 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0); 161 if (ret) 162 printf("%s: Timeout!\n", __func__); 163 164 /* 165 * Wait for core to come out of reset. 166 * NOTE: This long sleep is _very_ important, otherwise the core will 167 * not stay in host mode after a connector ID change! 168 */ 169 mdelay(100); 170 } 171 172 /* 173 * This function initializes the DWC_otg controller registers for 174 * host mode. 175 * 176 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 177 * request queues. Host channels are reset to ensure that they are ready for 178 * performing transfers. 179 * 180 * @param regs Programming view of DWC_otg controller 181 * 182 */ 183 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) 184 { 185 uint32_t nptxfifosize = 0; 186 uint32_t ptxfifosize = 0; 187 uint32_t hprt0 = 0; 188 int i, ret, num_channels; 189 190 /* Restart the Phy Clock */ 191 writel(0, ®s->pcgcctl); 192 193 /* Initialize Host Configuration Register */ 194 init_fslspclksel(regs); 195 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 196 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 197 #endif 198 199 /* Configure data FIFO sizes */ 200 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 201 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 202 /* Rx FIFO */ 203 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 204 205 /* Non-periodic Tx FIFO */ 206 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 207 DWC2_FIFOSIZE_DEPTH_OFFSET; 208 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 209 DWC2_FIFOSIZE_STARTADDR_OFFSET; 210 writel(nptxfifosize, ®s->gnptxfsiz); 211 212 /* Periodic Tx FIFO */ 213 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 214 DWC2_FIFOSIZE_DEPTH_OFFSET; 215 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 216 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 217 DWC2_FIFOSIZE_STARTADDR_OFFSET; 218 writel(ptxfifosize, ®s->hptxfsiz); 219 } 220 #endif 221 222 /* Clear Host Set HNP Enable in the OTG Control Register */ 223 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 224 225 /* Make sure the FIFOs are flushed. */ 226 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 227 dwc_otg_flush_rx_fifo(regs); 228 229 /* Flush out any leftover queued requests. */ 230 num_channels = readl(®s->ghwcfg2); 231 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 232 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 233 num_channels += 1; 234 235 for (i = 0; i < num_channels; i++) 236 clrsetbits_le32(®s->hc_regs[i].hcchar, 237 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 238 DWC2_HCCHAR_CHDIS); 239 240 /* Halt all channels to put them into a known state. */ 241 for (i = 0; i < num_channels; i++) { 242 clrsetbits_le32(®s->hc_regs[i].hcchar, 243 DWC2_HCCHAR_EPDIR, 244 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 245 ret = wait_for_bit(®s->hc_regs[i].hcchar, 246 DWC2_HCCHAR_CHEN, 0); 247 if (ret) 248 printf("%s: Timeout!\n", __func__); 249 } 250 251 /* Turn on the vbus power. */ 252 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 253 hprt0 = readl(®s->hprt0); 254 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 255 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 256 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 257 hprt0 |= DWC2_HPRT0_PRTPWR; 258 writel(hprt0, ®s->hprt0); 259 } 260 } 261 } 262 263 /* 264 * This function initializes the DWC_otg controller registers and 265 * prepares the core for device mode or host mode operation. 266 * 267 * @param regs Programming view of the DWC_otg controller 268 */ 269 static void dwc_otg_core_init(struct dwc2_core_regs *regs) 270 { 271 uint32_t ahbcfg = 0; 272 uint32_t usbcfg = 0; 273 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 274 275 /* Common Initialization */ 276 usbcfg = readl(®s->gusbcfg); 277 278 /* Program the ULPI External VBUS bit if needed */ 279 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 280 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 281 #else 282 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 283 #endif 284 285 /* Set external TS Dline pulsing */ 286 #ifdef CONFIG_DWC2_TS_DLINE 287 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 288 #else 289 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 290 #endif 291 writel(usbcfg, ®s->gusbcfg); 292 293 /* Reset the Controller */ 294 dwc_otg_core_reset(regs); 295 296 /* 297 * This programming sequence needs to happen in FS mode before 298 * any other programming occurs 299 */ 300 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 301 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 302 /* If FS mode with FS PHY */ 303 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 304 305 /* Reset after a PHY select */ 306 dwc_otg_core_reset(regs); 307 308 /* 309 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 310 * Also do this on HNP Dev/Host mode switches (done in dev_init 311 * and host_init). 312 */ 313 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 314 init_fslspclksel(regs); 315 316 #ifdef CONFIG_DWC2_I2C_ENABLE 317 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 318 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 319 320 /* Program GI2CCTL.I2CEn */ 321 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 322 DWC2_GI2CCTL_I2CDEVADDR_MASK, 323 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 324 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 325 #endif 326 327 #else 328 /* High speed PHY. */ 329 330 /* 331 * HS PHY parameters. These parameters are preserved during 332 * soft reset so only program the first time. Do a soft reset 333 * immediately after setting phyif. 334 */ 335 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 336 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 337 338 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 339 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 340 usbcfg |= DWC2_GUSBCFG_DDRSEL; 341 #else 342 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 343 #endif 344 } else { /* UTMI+ interface */ 345 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) 346 usbcfg |= DWC2_GUSBCFG_PHYIF; 347 #endif 348 } 349 350 writel(usbcfg, ®s->gusbcfg); 351 352 /* Reset after setting the PHY parameters */ 353 dwc_otg_core_reset(regs); 354 #endif 355 356 usbcfg = readl(®s->gusbcfg); 357 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 358 #ifdef CONFIG_DWC2_ULPI_FS_LS 359 uint32_t hwcfg2 = readl(®s->ghwcfg2); 360 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 361 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 362 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 363 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 364 if (hval == 2 && fval == 1) { 365 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 366 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 367 } 368 #endif 369 writel(usbcfg, ®s->gusbcfg); 370 371 /* Program the GAHBCFG Register. */ 372 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 373 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 374 break; 375 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 376 while (brst_sz > 1) { 377 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 378 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 379 brst_sz >>= 1; 380 } 381 382 #ifdef CONFIG_DWC2_DMA_ENABLE 383 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 384 #endif 385 break; 386 387 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 388 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 389 #ifdef CONFIG_DWC2_DMA_ENABLE 390 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 391 #endif 392 break; 393 } 394 395 writel(ahbcfg, ®s->gahbcfg); 396 397 /* Program the GUSBCFG register for HNP/SRP. */ 398 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); 399 400 #ifdef CONFIG_DWC2_IC_USB_CAP 401 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); 402 #endif 403 } 404 405 /* 406 * Prepares a host channel for transferring packets to/from a specific 407 * endpoint. The HCCHARn register is set up with the characteristics specified 408 * in _hc. Host channel interrupts that may need to be serviced while this 409 * transfer is in progress are enabled. 410 * 411 * @param regs Programming view of DWC_otg controller 412 * @param hc Information needed to initialize the host channel 413 */ 414 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 415 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 416 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 417 { 418 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 419 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 420 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 421 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 422 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 423 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 424 425 if (dev->speed == USB_SPEED_LOW) 426 hcchar |= DWC2_HCCHAR_LSPDDEV; 427 428 /* Clear old interrupt conditions for this host channel. */ 429 writel(0x3fff, &hc_regs->hcint); 430 431 /* 432 * Program the HCCHARn register with the endpoint characteristics 433 * for the current transfer. 434 */ 435 writel(hcchar, &hc_regs->hcchar); 436 437 /* Program the HCSPLIT register for SPLITs */ 438 writel(0, &hc_regs->hcsplt); 439 } 440 441 /* 442 * DWC2 to USB API interface 443 */ 444 /* Direction: In ; Request: Status */ 445 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 446 struct usb_device *dev, void *buffer, 447 int txlen, struct devrequest *cmd) 448 { 449 uint32_t hprt0 = 0; 450 uint32_t port_status = 0; 451 uint32_t port_change = 0; 452 int len = 0; 453 int stat = 0; 454 455 switch (cmd->requesttype & ~USB_DIR_IN) { 456 case 0: 457 *(uint16_t *)buffer = cpu_to_le16(1); 458 len = 2; 459 break; 460 case USB_RECIP_INTERFACE: 461 case USB_RECIP_ENDPOINT: 462 *(uint16_t *)buffer = cpu_to_le16(0); 463 len = 2; 464 break; 465 case USB_TYPE_CLASS: 466 *(uint32_t *)buffer = cpu_to_le32(0); 467 len = 4; 468 break; 469 case USB_RECIP_OTHER | USB_TYPE_CLASS: 470 hprt0 = readl(®s->hprt0); 471 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 472 port_status |= USB_PORT_STAT_CONNECTION; 473 if (hprt0 & DWC2_HPRT0_PRTENA) 474 port_status |= USB_PORT_STAT_ENABLE; 475 if (hprt0 & DWC2_HPRT0_PRTSUSP) 476 port_status |= USB_PORT_STAT_SUSPEND; 477 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 478 port_status |= USB_PORT_STAT_OVERCURRENT; 479 if (hprt0 & DWC2_HPRT0_PRTRST) 480 port_status |= USB_PORT_STAT_RESET; 481 if (hprt0 & DWC2_HPRT0_PRTPWR) 482 port_status |= USB_PORT_STAT_POWER; 483 484 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 485 port_status |= USB_PORT_STAT_LOW_SPEED; 486 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 487 DWC2_HPRT0_PRTSPD_HIGH) 488 port_status |= USB_PORT_STAT_HIGH_SPEED; 489 490 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 491 port_change |= USB_PORT_STAT_C_ENABLE; 492 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 493 port_change |= USB_PORT_STAT_C_CONNECTION; 494 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 495 port_change |= USB_PORT_STAT_C_OVERCURRENT; 496 497 *(uint32_t *)buffer = cpu_to_le32(port_status | 498 (port_change << 16)); 499 len = 4; 500 break; 501 default: 502 puts("unsupported root hub command\n"); 503 stat = USB_ST_STALLED; 504 } 505 506 dev->act_len = min(len, txlen); 507 dev->status = stat; 508 509 return stat; 510 } 511 512 /* Direction: In ; Request: Descriptor */ 513 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 514 void *buffer, int txlen, 515 struct devrequest *cmd) 516 { 517 unsigned char data[32]; 518 uint32_t dsc; 519 int len = 0; 520 int stat = 0; 521 uint16_t wValue = cpu_to_le16(cmd->value); 522 uint16_t wLength = cpu_to_le16(cmd->length); 523 524 switch (cmd->requesttype & ~USB_DIR_IN) { 525 case 0: 526 switch (wValue & 0xff00) { 527 case 0x0100: /* device descriptor */ 528 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 529 memcpy(buffer, root_hub_dev_des, len); 530 break; 531 case 0x0200: /* configuration descriptor */ 532 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 533 memcpy(buffer, root_hub_config_des, len); 534 break; 535 case 0x0300: /* string descriptors */ 536 switch (wValue & 0xff) { 537 case 0x00: 538 len = min3(txlen, (int)sizeof(root_hub_str_index0), 539 (int)wLength); 540 memcpy(buffer, root_hub_str_index0, len); 541 break; 542 case 0x01: 543 len = min3(txlen, (int)sizeof(root_hub_str_index1), 544 (int)wLength); 545 memcpy(buffer, root_hub_str_index1, len); 546 break; 547 } 548 break; 549 default: 550 stat = USB_ST_STALLED; 551 } 552 break; 553 554 case USB_TYPE_CLASS: 555 /* Root port config, set 1 port and nothing else. */ 556 dsc = 0x00000001; 557 558 data[0] = 9; /* min length; */ 559 data[1] = 0x29; 560 data[2] = dsc & RH_A_NDP; 561 data[3] = 0; 562 if (dsc & RH_A_PSM) 563 data[3] |= 0x1; 564 if (dsc & RH_A_NOCP) 565 data[3] |= 0x10; 566 else if (dsc & RH_A_OCPM) 567 data[3] |= 0x8; 568 569 /* corresponds to data[4-7] */ 570 data[5] = (dsc & RH_A_POTPGT) >> 24; 571 data[7] = dsc & RH_B_DR; 572 if (data[2] < 7) { 573 data[8] = 0xff; 574 } else { 575 data[0] += 2; 576 data[8] = (dsc & RH_B_DR) >> 8; 577 data[9] = 0xff; 578 data[10] = data[9]; 579 } 580 581 len = min3(txlen, (int)data[0], (int)wLength); 582 memcpy(buffer, data, len); 583 break; 584 default: 585 puts("unsupported root hub command\n"); 586 stat = USB_ST_STALLED; 587 } 588 589 dev->act_len = min(len, txlen); 590 dev->status = stat; 591 592 return stat; 593 } 594 595 /* Direction: In ; Request: Configuration */ 596 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 597 void *buffer, int txlen, 598 struct devrequest *cmd) 599 { 600 int len = 0; 601 int stat = 0; 602 603 switch (cmd->requesttype & ~USB_DIR_IN) { 604 case 0: 605 *(uint8_t *)buffer = 0x01; 606 len = 1; 607 break; 608 default: 609 puts("unsupported root hub command\n"); 610 stat = USB_ST_STALLED; 611 } 612 613 dev->act_len = min(len, txlen); 614 dev->status = stat; 615 616 return stat; 617 } 618 619 /* Direction: In */ 620 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 621 struct usb_device *dev, void *buffer, 622 int txlen, struct devrequest *cmd) 623 { 624 switch (cmd->request) { 625 case USB_REQ_GET_STATUS: 626 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 627 txlen, cmd); 628 case USB_REQ_GET_DESCRIPTOR: 629 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 630 txlen, cmd); 631 case USB_REQ_GET_CONFIGURATION: 632 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 633 txlen, cmd); 634 default: 635 puts("unsupported root hub command\n"); 636 return USB_ST_STALLED; 637 } 638 } 639 640 /* Direction: Out */ 641 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 642 struct usb_device *dev, 643 void *buffer, int txlen, 644 struct devrequest *cmd) 645 { 646 struct dwc2_core_regs *regs = priv->regs; 647 int len = 0; 648 int stat = 0; 649 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 650 uint16_t wValue = cpu_to_le16(cmd->value); 651 652 switch (bmrtype_breq & ~USB_DIR_IN) { 653 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 654 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 655 break; 656 657 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 658 switch (wValue) { 659 case USB_PORT_FEAT_C_CONNECTION: 660 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 661 break; 662 } 663 break; 664 665 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 666 switch (wValue) { 667 case USB_PORT_FEAT_SUSPEND: 668 break; 669 670 case USB_PORT_FEAT_RESET: 671 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 672 DWC2_HPRT0_PRTCONNDET | 673 DWC2_HPRT0_PRTENCHNG | 674 DWC2_HPRT0_PRTOVRCURRCHNG, 675 DWC2_HPRT0_PRTRST); 676 mdelay(50); 677 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 678 break; 679 680 case USB_PORT_FEAT_POWER: 681 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 682 DWC2_HPRT0_PRTCONNDET | 683 DWC2_HPRT0_PRTENCHNG | 684 DWC2_HPRT0_PRTOVRCURRCHNG, 685 DWC2_HPRT0_PRTRST); 686 break; 687 688 case USB_PORT_FEAT_ENABLE: 689 break; 690 } 691 break; 692 case (USB_REQ_SET_ADDRESS << 8): 693 priv->root_hub_devnum = wValue; 694 break; 695 case (USB_REQ_SET_CONFIGURATION << 8): 696 break; 697 default: 698 puts("unsupported root hub command\n"); 699 stat = USB_ST_STALLED; 700 } 701 702 len = min(len, txlen); 703 704 dev->act_len = len; 705 dev->status = stat; 706 707 return stat; 708 } 709 710 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 711 unsigned long pipe, void *buffer, int txlen, 712 struct devrequest *cmd) 713 { 714 int stat = 0; 715 716 if (usb_pipeint(pipe)) { 717 puts("Root-Hub submit IRQ: NOT implemented\n"); 718 return 0; 719 } 720 721 if (cmd->requesttype & USB_DIR_IN) 722 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 723 else 724 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 725 726 mdelay(1); 727 728 return stat; 729 } 730 731 int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle, 732 bool ignore_ack) 733 { 734 uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD; 735 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 736 int ret; 737 uint32_t hcint, hctsiz; 738 739 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true); 740 if (ret) 741 return ret; 742 743 hcint = readl(&hc_regs->hcint); 744 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 745 return -EAGAIN; 746 if (ignore_ack) 747 hcint &= ~DWC2_HCINT_ACK; 748 else 749 hcint_comp_hlt_ack |= DWC2_HCINT_ACK; 750 if (hcint != hcint_comp_hlt_ack) { 751 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 752 return -EINVAL; 753 } 754 755 hctsiz = readl(&hc_regs->hctsiz); 756 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 757 DWC2_HCTSIZ_XFERSIZE_OFFSET; 758 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 759 760 debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle); 761 762 return 0; 763 } 764 765 static int dwc2_eptype[] = { 766 DWC2_HCCHAR_EPTYPE_ISOC, 767 DWC2_HCCHAR_EPTYPE_INTR, 768 DWC2_HCCHAR_EPTYPE_CONTROL, 769 DWC2_HCCHAR_EPTYPE_BULK, 770 }; 771 772 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 773 unsigned long pipe, int *pid, int in, void *buffer, int len, 774 bool ignore_ack) 775 { 776 struct dwc2_core_regs *regs = priv->regs; 777 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 778 int devnum = usb_pipedevice(pipe); 779 int ep = usb_pipeendpoint(pipe); 780 int max = usb_maxpacket(dev, pipe); 781 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 782 int done = 0; 783 int ret = 0; 784 uint32_t sub; 785 uint32_t xfer_len; 786 uint32_t num_packets; 787 int stop_transfer = 0; 788 789 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 790 in, len); 791 792 do { 793 /* Initialize channel */ 794 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 795 eptype, max); 796 797 xfer_len = len - done; 798 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 799 xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1; 800 if (xfer_len > DWC2_DATA_BUF_SIZE) 801 xfer_len = DWC2_DATA_BUF_SIZE - max + 1; 802 803 /* Make sure that xfer_len is a multiple of max packet size. */ 804 if (xfer_len > 0) { 805 num_packets = (xfer_len + max - 1) / max; 806 if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) { 807 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT; 808 xfer_len = num_packets * max; 809 } 810 } else { 811 num_packets = 1; 812 } 813 814 if (in) 815 xfer_len = num_packets * max; 816 817 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 818 *pid, xfer_len, num_packets); 819 820 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 821 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 822 (*pid << DWC2_HCTSIZ_PID_OFFSET), 823 &hc_regs->hctsiz); 824 825 if (!in) { 826 memcpy(priv->aligned_buffer, (char *)buffer + done, len); 827 828 flush_dcache_range((unsigned long)priv->aligned_buffer, 829 (unsigned long)((void *)priv->aligned_buffer + 830 roundup(len, ARCH_DMA_MINALIGN))); 831 } 832 833 writel(phys_to_bus((unsigned long)priv->aligned_buffer), 834 &hc_regs->hcdma); 835 836 /* Set host channel enable after all other setup is complete. */ 837 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 838 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS, 839 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 840 DWC2_HCCHAR_CHEN); 841 842 ret = wait_for_chhltd(regs, &sub, pid, ignore_ack); 843 if (ret) 844 break; 845 846 if (in) { 847 xfer_len -= sub; 848 849 invalidate_dcache_range((unsigned long)priv->aligned_buffer, 850 (unsigned long)((void *)priv->aligned_buffer + 851 roundup(xfer_len, ARCH_DMA_MINALIGN))); 852 853 memcpy(buffer + done, priv->aligned_buffer, xfer_len); 854 if (sub) 855 stop_transfer = 1; 856 } 857 858 done += xfer_len; 859 860 } while ((done < len) && !stop_transfer); 861 862 writel(0, &hc_regs->hcintmsk); 863 writel(0xFFFFFFFF, &hc_regs->hcint); 864 865 dev->status = 0; 866 dev->act_len = done; 867 868 return ret; 869 } 870 871 /* U-Boot USB transmission interface */ 872 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 873 unsigned long pipe, void *buffer, int len) 874 { 875 int devnum = usb_pipedevice(pipe); 876 int ep = usb_pipeendpoint(pipe); 877 878 if (devnum == priv->root_hub_devnum) { 879 dev->status = 0; 880 return -EINVAL; 881 } 882 883 return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep], 884 usb_pipein(pipe), buffer, len, true); 885 } 886 887 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 888 unsigned long pipe, void *buffer, int len, 889 struct devrequest *setup) 890 { 891 int devnum = usb_pipedevice(pipe); 892 int pid, ret, act_len; 893 /* For CONTROL endpoint pid should start with DATA1 */ 894 int status_direction; 895 896 if (devnum == priv->root_hub_devnum) { 897 dev->status = 0; 898 dev->speed = USB_SPEED_HIGH; 899 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 900 setup); 901 } 902 903 pid = DWC2_HC_PID_SETUP; 904 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true); 905 if (ret) 906 return ret; 907 908 if (buffer) { 909 pid = DWC2_HC_PID_DATA1; 910 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer, 911 len, false); 912 if (ret) 913 return ret; 914 act_len = dev->act_len; 915 } /* End of DATA stage */ 916 else 917 act_len = 0; 918 919 /* STATUS stage */ 920 if ((len == 0) || usb_pipeout(pipe)) 921 status_direction = 1; 922 else 923 status_direction = 0; 924 925 pid = DWC2_HC_PID_DATA1; 926 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 927 priv->status_buffer, 0, false); 928 if (ret) 929 return ret; 930 931 dev->act_len = act_len; 932 933 return 0; 934 } 935 936 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 937 unsigned long pipe, void *buffer, int len, int interval) 938 { 939 unsigned long timeout; 940 int ret; 941 942 /* FIXME: what is interval? */ 943 944 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 945 for (;;) { 946 if (get_timer(0) > timeout) { 947 printf("Timeout poll on interrupt endpoint\n"); 948 return -ETIMEDOUT; 949 } 950 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 951 if (ret != -EAGAIN) 952 return ret; 953 } 954 } 955 956 static int dwc2_init_common(struct dwc2_priv *priv) 957 { 958 struct dwc2_core_regs *regs = priv->regs; 959 uint32_t snpsid; 960 int i, j; 961 962 snpsid = readl(®s->gsnpsid); 963 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); 964 965 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 966 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 967 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); 968 return -ENODEV; 969 } 970 971 dwc_otg_core_init(regs); 972 dwc_otg_core_host_init(regs); 973 974 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 975 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 976 DWC2_HPRT0_PRTOVRCURRCHNG, 977 DWC2_HPRT0_PRTRST); 978 mdelay(50); 979 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 980 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 981 DWC2_HPRT0_PRTRST); 982 983 for (i = 0; i < MAX_DEVICE; i++) { 984 for (j = 0; j < MAX_ENDPOINT; j++) 985 priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0; 986 } 987 988 return 0; 989 } 990 991 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 992 { 993 /* Put everything in reset. */ 994 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 995 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 996 DWC2_HPRT0_PRTOVRCURRCHNG, 997 DWC2_HPRT0_PRTRST); 998 } 999 1000 #ifndef CONFIG_DM_USB 1001 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1002 int len, struct devrequest *setup) 1003 { 1004 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1005 } 1006 1007 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1008 int len) 1009 { 1010 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1011 } 1012 1013 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1014 int len, int interval) 1015 { 1016 return _submit_int_msg(&local, dev, pipe, buffer, len, interval); 1017 } 1018 1019 /* U-Boot USB control interface */ 1020 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1021 { 1022 struct dwc2_priv *priv = &local; 1023 1024 memset(priv, '\0', sizeof(*priv)); 1025 priv->root_hub_devnum = 0; 1026 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1027 priv->aligned_buffer = aligned_buffer_addr; 1028 priv->status_buffer = status_buffer_addr; 1029 1030 /* board-dependant init */ 1031 if (board_usb_init(index, USB_INIT_HOST)) 1032 return -1; 1033 1034 return dwc2_init_common(priv); 1035 } 1036 1037 int usb_lowlevel_stop(int index) 1038 { 1039 dwc2_uninit_common(local.regs); 1040 1041 return 0; 1042 } 1043 #endif 1044 1045 #ifdef CONFIG_DM_USB 1046 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1047 unsigned long pipe, void *buffer, int length, 1048 struct devrequest *setup) 1049 { 1050 struct dwc2_priv *priv = dev_get_priv(dev); 1051 1052 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1053 dev->name, udev, udev->dev->name, udev->portnr); 1054 1055 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1056 } 1057 1058 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1059 unsigned long pipe, void *buffer, int length) 1060 { 1061 struct dwc2_priv *priv = dev_get_priv(dev); 1062 1063 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1064 1065 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1066 } 1067 1068 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1069 unsigned long pipe, void *buffer, int length, 1070 int interval) 1071 { 1072 struct dwc2_priv *priv = dev_get_priv(dev); 1073 1074 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1075 1076 return _submit_int_msg(priv, udev, pipe, buffer, length, interval); 1077 } 1078 1079 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1080 { 1081 struct dwc2_priv *priv = dev_get_priv(dev); 1082 fdt_addr_t addr; 1083 1084 addr = dev_get_addr(dev); 1085 if (addr == FDT_ADDR_T_NONE) 1086 return -EINVAL; 1087 priv->regs = (struct dwc2_core_regs *)addr; 1088 1089 return 0; 1090 } 1091 1092 static int dwc2_usb_probe(struct udevice *dev) 1093 { 1094 struct dwc2_priv *priv = dev_get_priv(dev); 1095 1096 return dwc2_init_common(priv); 1097 } 1098 1099 static int dwc2_usb_remove(struct udevice *dev) 1100 { 1101 struct dwc2_priv *priv = dev_get_priv(dev); 1102 1103 dwc2_uninit_common(priv->regs); 1104 1105 return 0; 1106 } 1107 1108 struct dm_usb_ops dwc2_usb_ops = { 1109 .control = dwc2_submit_control_msg, 1110 .bulk = dwc2_submit_bulk_msg, 1111 .interrupt = dwc2_submit_int_msg, 1112 }; 1113 1114 static const struct udevice_id dwc2_usb_ids[] = { 1115 { .compatible = "brcm,bcm2835-usb" }, 1116 { .compatible = "snps,dwc2" }, 1117 { } 1118 }; 1119 1120 U_BOOT_DRIVER(usb_dwc2) = { 1121 .name = "dwc2_usb", 1122 .id = UCLASS_USB, 1123 .of_match = dwc2_usb_ids, 1124 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1125 .probe = dwc2_usb_probe, 1126 .remove = dwc2_usb_remove, 1127 .ops = &dwc2_usb_ops, 1128 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1129 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1130 }; 1131 #endif 1132