1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <usb.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <phys2bus.h> 15 #include <usbroothubdes.h> 16 #include <wait_bit.h> 17 #include <asm/io.h> 18 #include <power/regulator.h> 19 20 #include "dwc2.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /* Use only HC channel 0. */ 25 #define DWC2_HC_CHANNEL 0 26 27 #define DWC2_STATUS_BUF_SIZE 64 28 #define DWC2_DATA_BUF_SIZE (64 * 1024) 29 30 #define MAX_DEVICE 16 31 #define MAX_ENDPOINT 16 32 33 struct dwc2_priv { 34 #ifdef CONFIG_DM_USB 35 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 36 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 37 #else 38 uint8_t *aligned_buffer; 39 uint8_t *status_buffer; 40 #endif 41 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 42 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 43 struct dwc2_core_regs *regs; 44 int root_hub_devnum; 45 bool ext_vbus; 46 bool hnp_srp_disable; 47 bool oc_disable; 48 }; 49 50 #ifndef CONFIG_DM_USB 51 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 52 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 53 ARCH_DMA_MINALIGN); 54 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 55 ARCH_DMA_MINALIGN); 56 57 static struct dwc2_priv local; 58 #endif 59 60 /* 61 * DWC2 IP interface 62 */ 63 64 /* 65 * Initializes the FSLSPClkSel field of the HCFG register 66 * depending on the PHY type. 67 */ 68 static void init_fslspclksel(struct dwc2_core_regs *regs) 69 { 70 uint32_t phyclk; 71 72 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 73 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 74 #else 75 /* High speed PHY running at full speed or high speed */ 76 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 77 #endif 78 79 #ifdef CONFIG_DWC2_ULPI_FS_LS 80 uint32_t hwcfg2 = readl(®s->ghwcfg2); 81 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 82 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 83 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 84 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 85 86 if (hval == 2 && fval == 1) 87 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 88 #endif 89 90 clrsetbits_le32(®s->host_regs.hcfg, 91 DWC2_HCFG_FSLSPCLKSEL_MASK, 92 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 93 } 94 95 /* 96 * Flush a Tx FIFO. 97 * 98 * @param regs Programming view of DWC_otg controller. 99 * @param num Tx FIFO to flush. 100 */ 101 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 102 { 103 int ret; 104 105 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 106 ®s->grstctl); 107 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 108 false, 1000, false); 109 if (ret) 110 printf("%s: Timeout!\n", __func__); 111 112 /* Wait for 3 PHY Clocks */ 113 udelay(1); 114 } 115 116 /* 117 * Flush Rx FIFO. 118 * 119 * @param regs Programming view of DWC_otg controller. 120 */ 121 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 122 { 123 int ret; 124 125 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 126 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 127 false, 1000, false); 128 if (ret) 129 printf("%s: Timeout!\n", __func__); 130 131 /* Wait for 3 PHY Clocks */ 132 udelay(1); 133 } 134 135 /* 136 * Do core a soft reset of the core. Be careful with this because it 137 * resets all the internal state machines of the core. 138 */ 139 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 140 { 141 int ret; 142 143 /* Wait for AHB master IDLE state. */ 144 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 145 true, 1000, false); 146 if (ret) 147 printf("%s: Timeout!\n", __func__); 148 149 /* Core Soft Reset */ 150 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 151 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST, 152 false, 1000, false); 153 if (ret) 154 printf("%s: Timeout!\n", __func__); 155 156 /* 157 * Wait for core to come out of reset. 158 * NOTE: This long sleep is _very_ important, otherwise the core will 159 * not stay in host mode after a connector ID change! 160 */ 161 mdelay(100); 162 } 163 164 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) 165 static int dwc_vbus_supply_init(struct udevice *dev) 166 { 167 struct udevice *vbus_supply; 168 int ret; 169 170 ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply); 171 if (ret) { 172 debug("%s: No vbus supply\n", dev->name); 173 return 0; 174 } 175 176 ret = regulator_set_enable(vbus_supply, true); 177 if (ret) { 178 error("Error enabling vbus supply\n"); 179 return ret; 180 } 181 182 return 0; 183 } 184 #else 185 static int dwc_vbus_supply_init(struct udevice *dev) 186 { 187 return 0; 188 } 189 #endif 190 191 /* 192 * This function initializes the DWC_otg controller registers for 193 * host mode. 194 * 195 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 196 * request queues. Host channels are reset to ensure that they are ready for 197 * performing transfers. 198 * 199 * @param dev USB Device (NULL if driver model is not being used) 200 * @param regs Programming view of DWC_otg controller 201 * 202 */ 203 static void dwc_otg_core_host_init(struct udevice *dev, 204 struct dwc2_core_regs *regs) 205 { 206 uint32_t nptxfifosize = 0; 207 uint32_t ptxfifosize = 0; 208 uint32_t hprt0 = 0; 209 int i, ret, num_channels; 210 211 /* Restart the Phy Clock */ 212 writel(0, ®s->pcgcctl); 213 214 /* Initialize Host Configuration Register */ 215 init_fslspclksel(regs); 216 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 217 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 218 #endif 219 220 /* Configure data FIFO sizes */ 221 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 222 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 223 /* Rx FIFO */ 224 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 225 226 /* Non-periodic Tx FIFO */ 227 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 228 DWC2_FIFOSIZE_DEPTH_OFFSET; 229 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 230 DWC2_FIFOSIZE_STARTADDR_OFFSET; 231 writel(nptxfifosize, ®s->gnptxfsiz); 232 233 /* Periodic Tx FIFO */ 234 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 235 DWC2_FIFOSIZE_DEPTH_OFFSET; 236 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 237 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 238 DWC2_FIFOSIZE_STARTADDR_OFFSET; 239 writel(ptxfifosize, ®s->hptxfsiz); 240 } 241 #endif 242 243 /* Clear Host Set HNP Enable in the OTG Control Register */ 244 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 245 246 /* Make sure the FIFOs are flushed. */ 247 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 248 dwc_otg_flush_rx_fifo(regs); 249 250 /* Flush out any leftover queued requests. */ 251 num_channels = readl(®s->ghwcfg2); 252 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 253 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 254 num_channels += 1; 255 256 for (i = 0; i < num_channels; i++) 257 clrsetbits_le32(®s->hc_regs[i].hcchar, 258 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 259 DWC2_HCCHAR_CHDIS); 260 261 /* Halt all channels to put them into a known state. */ 262 for (i = 0; i < num_channels; i++) { 263 clrsetbits_le32(®s->hc_regs[i].hcchar, 264 DWC2_HCCHAR_EPDIR, 265 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 266 ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar, 267 DWC2_HCCHAR_CHEN, false, 1000, false); 268 if (ret) 269 printf("%s: Timeout!\n", __func__); 270 } 271 272 /* Turn on the vbus power. */ 273 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 274 hprt0 = readl(®s->hprt0); 275 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 276 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 277 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 278 hprt0 |= DWC2_HPRT0_PRTPWR; 279 writel(hprt0, ®s->hprt0); 280 } 281 } 282 283 if (dev) 284 dwc_vbus_supply_init(dev); 285 } 286 287 /* 288 * This function initializes the DWC_otg controller registers and 289 * prepares the core for device mode or host mode operation. 290 * 291 * @param regs Programming view of the DWC_otg controller 292 */ 293 static void dwc_otg_core_init(struct dwc2_priv *priv) 294 { 295 struct dwc2_core_regs *regs = priv->regs; 296 uint32_t ahbcfg = 0; 297 uint32_t usbcfg = 0; 298 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 299 300 /* Common Initialization */ 301 usbcfg = readl(®s->gusbcfg); 302 303 /* Program the ULPI External VBUS bit if needed */ 304 if (priv->ext_vbus) { 305 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 306 if (!priv->oc_disable) { 307 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | 308 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH; 309 } 310 } else { 311 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 312 } 313 314 /* Set external TS Dline pulsing */ 315 #ifdef CONFIG_DWC2_TS_DLINE 316 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 317 #else 318 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 319 #endif 320 writel(usbcfg, ®s->gusbcfg); 321 322 /* Reset the Controller */ 323 dwc_otg_core_reset(regs); 324 325 /* 326 * This programming sequence needs to happen in FS mode before 327 * any other programming occurs 328 */ 329 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 330 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 331 /* If FS mode with FS PHY */ 332 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 333 334 /* Reset after a PHY select */ 335 dwc_otg_core_reset(regs); 336 337 /* 338 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 339 * Also do this on HNP Dev/Host mode switches (done in dev_init 340 * and host_init). 341 */ 342 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 343 init_fslspclksel(regs); 344 345 #ifdef CONFIG_DWC2_I2C_ENABLE 346 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 347 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 348 349 /* Program GI2CCTL.I2CEn */ 350 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 351 DWC2_GI2CCTL_I2CDEVADDR_MASK, 352 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 353 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 354 #endif 355 356 #else 357 /* High speed PHY. */ 358 359 /* 360 * HS PHY parameters. These parameters are preserved during 361 * soft reset so only program the first time. Do a soft reset 362 * immediately after setting phyif. 363 */ 364 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 365 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 366 367 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 368 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 369 usbcfg |= DWC2_GUSBCFG_DDRSEL; 370 #else 371 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 372 #endif 373 } else { /* UTMI+ interface */ 374 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) 375 usbcfg |= DWC2_GUSBCFG_PHYIF; 376 #endif 377 } 378 379 writel(usbcfg, ®s->gusbcfg); 380 381 /* Reset after setting the PHY parameters */ 382 dwc_otg_core_reset(regs); 383 #endif 384 385 usbcfg = readl(®s->gusbcfg); 386 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 387 #ifdef CONFIG_DWC2_ULPI_FS_LS 388 uint32_t hwcfg2 = readl(®s->ghwcfg2); 389 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 390 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 391 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 392 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 393 if (hval == 2 && fval == 1) { 394 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 395 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 396 } 397 #endif 398 if (priv->hnp_srp_disable) 399 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE; 400 401 writel(usbcfg, ®s->gusbcfg); 402 403 /* Program the GAHBCFG Register. */ 404 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 405 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 406 break; 407 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 408 while (brst_sz > 1) { 409 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 410 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 411 brst_sz >>= 1; 412 } 413 414 #ifdef CONFIG_DWC2_DMA_ENABLE 415 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 416 #endif 417 break; 418 419 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 420 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 421 #ifdef CONFIG_DWC2_DMA_ENABLE 422 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 423 #endif 424 break; 425 } 426 427 writel(ahbcfg, ®s->gahbcfg); 428 429 /* Program the capabilities in GUSBCFG Register */ 430 usbcfg = 0; 431 432 if (!priv->hnp_srp_disable) 433 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; 434 #ifdef CONFIG_DWC2_IC_USB_CAP 435 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; 436 #endif 437 438 setbits_le32(®s->gusbcfg, usbcfg); 439 } 440 441 /* 442 * Prepares a host channel for transferring packets to/from a specific 443 * endpoint. The HCCHARn register is set up with the characteristics specified 444 * in _hc. Host channel interrupts that may need to be serviced while this 445 * transfer is in progress are enabled. 446 * 447 * @param regs Programming view of DWC_otg controller 448 * @param hc Information needed to initialize the host channel 449 */ 450 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 451 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 452 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 453 { 454 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 455 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 456 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 457 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 458 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 459 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 460 461 if (dev->speed == USB_SPEED_LOW) 462 hcchar |= DWC2_HCCHAR_LSPDDEV; 463 464 /* 465 * Program the HCCHARn register with the endpoint characteristics 466 * for the current transfer. 467 */ 468 writel(hcchar, &hc_regs->hcchar); 469 470 /* Program the HCSPLIT register, default to no SPLIT */ 471 writel(0, &hc_regs->hcsplt); 472 } 473 474 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 475 uint8_t hub_devnum, uint8_t hub_port) 476 { 477 uint32_t hcsplt = 0; 478 479 hcsplt = DWC2_HCSPLT_SPLTENA; 480 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 481 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 482 483 /* Program the HCSPLIT register for SPLITs */ 484 writel(hcsplt, &hc_regs->hcsplt); 485 } 486 487 /* 488 * DWC2 to USB API interface 489 */ 490 /* Direction: In ; Request: Status */ 491 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 492 struct usb_device *dev, void *buffer, 493 int txlen, struct devrequest *cmd) 494 { 495 uint32_t hprt0 = 0; 496 uint32_t port_status = 0; 497 uint32_t port_change = 0; 498 int len = 0; 499 int stat = 0; 500 501 switch (cmd->requesttype & ~USB_DIR_IN) { 502 case 0: 503 *(uint16_t *)buffer = cpu_to_le16(1); 504 len = 2; 505 break; 506 case USB_RECIP_INTERFACE: 507 case USB_RECIP_ENDPOINT: 508 *(uint16_t *)buffer = cpu_to_le16(0); 509 len = 2; 510 break; 511 case USB_TYPE_CLASS: 512 *(uint32_t *)buffer = cpu_to_le32(0); 513 len = 4; 514 break; 515 case USB_RECIP_OTHER | USB_TYPE_CLASS: 516 hprt0 = readl(®s->hprt0); 517 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 518 port_status |= USB_PORT_STAT_CONNECTION; 519 if (hprt0 & DWC2_HPRT0_PRTENA) 520 port_status |= USB_PORT_STAT_ENABLE; 521 if (hprt0 & DWC2_HPRT0_PRTSUSP) 522 port_status |= USB_PORT_STAT_SUSPEND; 523 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 524 port_status |= USB_PORT_STAT_OVERCURRENT; 525 if (hprt0 & DWC2_HPRT0_PRTRST) 526 port_status |= USB_PORT_STAT_RESET; 527 if (hprt0 & DWC2_HPRT0_PRTPWR) 528 port_status |= USB_PORT_STAT_POWER; 529 530 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 531 port_status |= USB_PORT_STAT_LOW_SPEED; 532 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 533 DWC2_HPRT0_PRTSPD_HIGH) 534 port_status |= USB_PORT_STAT_HIGH_SPEED; 535 536 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 537 port_change |= USB_PORT_STAT_C_ENABLE; 538 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 539 port_change |= USB_PORT_STAT_C_CONNECTION; 540 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 541 port_change |= USB_PORT_STAT_C_OVERCURRENT; 542 543 *(uint32_t *)buffer = cpu_to_le32(port_status | 544 (port_change << 16)); 545 len = 4; 546 break; 547 default: 548 puts("unsupported root hub command\n"); 549 stat = USB_ST_STALLED; 550 } 551 552 dev->act_len = min(len, txlen); 553 dev->status = stat; 554 555 return stat; 556 } 557 558 /* Direction: In ; Request: Descriptor */ 559 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 560 void *buffer, int txlen, 561 struct devrequest *cmd) 562 { 563 unsigned char data[32]; 564 uint32_t dsc; 565 int len = 0; 566 int stat = 0; 567 uint16_t wValue = cpu_to_le16(cmd->value); 568 uint16_t wLength = cpu_to_le16(cmd->length); 569 570 switch (cmd->requesttype & ~USB_DIR_IN) { 571 case 0: 572 switch (wValue & 0xff00) { 573 case 0x0100: /* device descriptor */ 574 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 575 memcpy(buffer, root_hub_dev_des, len); 576 break; 577 case 0x0200: /* configuration descriptor */ 578 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 579 memcpy(buffer, root_hub_config_des, len); 580 break; 581 case 0x0300: /* string descriptors */ 582 switch (wValue & 0xff) { 583 case 0x00: 584 len = min3(txlen, (int)sizeof(root_hub_str_index0), 585 (int)wLength); 586 memcpy(buffer, root_hub_str_index0, len); 587 break; 588 case 0x01: 589 len = min3(txlen, (int)sizeof(root_hub_str_index1), 590 (int)wLength); 591 memcpy(buffer, root_hub_str_index1, len); 592 break; 593 } 594 break; 595 default: 596 stat = USB_ST_STALLED; 597 } 598 break; 599 600 case USB_TYPE_CLASS: 601 /* Root port config, set 1 port and nothing else. */ 602 dsc = 0x00000001; 603 604 data[0] = 9; /* min length; */ 605 data[1] = 0x29; 606 data[2] = dsc & RH_A_NDP; 607 data[3] = 0; 608 if (dsc & RH_A_PSM) 609 data[3] |= 0x1; 610 if (dsc & RH_A_NOCP) 611 data[3] |= 0x10; 612 else if (dsc & RH_A_OCPM) 613 data[3] |= 0x8; 614 615 /* corresponds to data[4-7] */ 616 data[5] = (dsc & RH_A_POTPGT) >> 24; 617 data[7] = dsc & RH_B_DR; 618 if (data[2] < 7) { 619 data[8] = 0xff; 620 } else { 621 data[0] += 2; 622 data[8] = (dsc & RH_B_DR) >> 8; 623 data[9] = 0xff; 624 data[10] = data[9]; 625 } 626 627 len = min3(txlen, (int)data[0], (int)wLength); 628 memcpy(buffer, data, len); 629 break; 630 default: 631 puts("unsupported root hub command\n"); 632 stat = USB_ST_STALLED; 633 } 634 635 dev->act_len = min(len, txlen); 636 dev->status = stat; 637 638 return stat; 639 } 640 641 /* Direction: In ; Request: Configuration */ 642 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 643 void *buffer, int txlen, 644 struct devrequest *cmd) 645 { 646 int len = 0; 647 int stat = 0; 648 649 switch (cmd->requesttype & ~USB_DIR_IN) { 650 case 0: 651 *(uint8_t *)buffer = 0x01; 652 len = 1; 653 break; 654 default: 655 puts("unsupported root hub command\n"); 656 stat = USB_ST_STALLED; 657 } 658 659 dev->act_len = min(len, txlen); 660 dev->status = stat; 661 662 return stat; 663 } 664 665 /* Direction: In */ 666 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 667 struct usb_device *dev, void *buffer, 668 int txlen, struct devrequest *cmd) 669 { 670 switch (cmd->request) { 671 case USB_REQ_GET_STATUS: 672 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 673 txlen, cmd); 674 case USB_REQ_GET_DESCRIPTOR: 675 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 676 txlen, cmd); 677 case USB_REQ_GET_CONFIGURATION: 678 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 679 txlen, cmd); 680 default: 681 puts("unsupported root hub command\n"); 682 return USB_ST_STALLED; 683 } 684 } 685 686 /* Direction: Out */ 687 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 688 struct usb_device *dev, 689 void *buffer, int txlen, 690 struct devrequest *cmd) 691 { 692 struct dwc2_core_regs *regs = priv->regs; 693 int len = 0; 694 int stat = 0; 695 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 696 uint16_t wValue = cpu_to_le16(cmd->value); 697 698 switch (bmrtype_breq & ~USB_DIR_IN) { 699 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 700 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 701 break; 702 703 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 704 switch (wValue) { 705 case USB_PORT_FEAT_C_CONNECTION: 706 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 707 break; 708 } 709 break; 710 711 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 712 switch (wValue) { 713 case USB_PORT_FEAT_SUSPEND: 714 break; 715 716 case USB_PORT_FEAT_RESET: 717 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 718 DWC2_HPRT0_PRTCONNDET | 719 DWC2_HPRT0_PRTENCHNG | 720 DWC2_HPRT0_PRTOVRCURRCHNG, 721 DWC2_HPRT0_PRTRST); 722 mdelay(50); 723 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 724 break; 725 726 case USB_PORT_FEAT_POWER: 727 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 728 DWC2_HPRT0_PRTCONNDET | 729 DWC2_HPRT0_PRTENCHNG | 730 DWC2_HPRT0_PRTOVRCURRCHNG, 731 DWC2_HPRT0_PRTRST); 732 break; 733 734 case USB_PORT_FEAT_ENABLE: 735 break; 736 } 737 break; 738 case (USB_REQ_SET_ADDRESS << 8): 739 priv->root_hub_devnum = wValue; 740 break; 741 case (USB_REQ_SET_CONFIGURATION << 8): 742 break; 743 default: 744 puts("unsupported root hub command\n"); 745 stat = USB_ST_STALLED; 746 } 747 748 len = min(len, txlen); 749 750 dev->act_len = len; 751 dev->status = stat; 752 753 return stat; 754 } 755 756 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 757 unsigned long pipe, void *buffer, int txlen, 758 struct devrequest *cmd) 759 { 760 int stat = 0; 761 762 if (usb_pipeint(pipe)) { 763 puts("Root-Hub submit IRQ: NOT implemented\n"); 764 return 0; 765 } 766 767 if (cmd->requesttype & USB_DIR_IN) 768 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 769 else 770 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 771 772 mdelay(1); 773 774 return stat; 775 } 776 777 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) 778 { 779 int ret; 780 uint32_t hcint, hctsiz; 781 782 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true, 783 1000, false); 784 if (ret) 785 return ret; 786 787 hcint = readl(&hc_regs->hcint); 788 hctsiz = readl(&hc_regs->hctsiz); 789 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 790 DWC2_HCTSIZ_XFERSIZE_OFFSET; 791 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 792 793 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 794 *toggle); 795 796 if (hcint & DWC2_HCINT_XFERCOMP) 797 return 0; 798 799 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 800 return -EAGAIN; 801 802 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 803 return -EINVAL; 804 } 805 806 static int dwc2_eptype[] = { 807 DWC2_HCCHAR_EPTYPE_ISOC, 808 DWC2_HCCHAR_EPTYPE_INTR, 809 DWC2_HCCHAR_EPTYPE_CONTROL, 810 DWC2_HCCHAR_EPTYPE_BULK, 811 }; 812 813 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 814 u8 *pid, int in, void *buffer, int num_packets, 815 int xfer_len, int *actual_len, int odd_frame) 816 { 817 int ret = 0; 818 uint32_t sub; 819 820 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 821 *pid, xfer_len, num_packets); 822 823 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 824 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 825 (*pid << DWC2_HCTSIZ_PID_OFFSET), 826 &hc_regs->hctsiz); 827 828 if (xfer_len) { 829 if (in) { 830 invalidate_dcache_range( 831 (uintptr_t)aligned_buffer, 832 (uintptr_t)aligned_buffer + 833 roundup(xfer_len, ARCH_DMA_MINALIGN)); 834 } else { 835 memcpy(aligned_buffer, buffer, xfer_len); 836 flush_dcache_range( 837 (uintptr_t)aligned_buffer, 838 (uintptr_t)aligned_buffer + 839 roundup(xfer_len, ARCH_DMA_MINALIGN)); 840 } 841 } 842 843 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 844 845 /* Clear old interrupt conditions for this host channel. */ 846 writel(0x3fff, &hc_regs->hcint); 847 848 /* Set host channel enable after all other setup is complete. */ 849 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 850 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 851 DWC2_HCCHAR_ODDFRM, 852 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 853 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 854 DWC2_HCCHAR_CHEN); 855 856 ret = wait_for_chhltd(hc_regs, &sub, pid); 857 if (ret < 0) 858 return ret; 859 860 if (in) { 861 xfer_len -= sub; 862 863 invalidate_dcache_range((unsigned long)aligned_buffer, 864 (unsigned long)aligned_buffer + 865 roundup(xfer_len, ARCH_DMA_MINALIGN)); 866 867 memcpy(buffer, aligned_buffer, xfer_len); 868 } 869 *actual_len = xfer_len; 870 871 return ret; 872 } 873 874 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 875 unsigned long pipe, u8 *pid, int in, void *buffer, int len) 876 { 877 struct dwc2_core_regs *regs = priv->regs; 878 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 879 struct dwc2_host_regs *host_regs = ®s->host_regs; 880 int devnum = usb_pipedevice(pipe); 881 int ep = usb_pipeendpoint(pipe); 882 int max = usb_maxpacket(dev, pipe); 883 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 884 int done = 0; 885 int ret = 0; 886 int do_split = 0; 887 int complete_split = 0; 888 uint32_t xfer_len; 889 uint32_t num_packets; 890 int stop_transfer = 0; 891 uint32_t max_xfer_len; 892 int ssplit_frame_num = 0; 893 894 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 895 in, len); 896 897 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 898 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 899 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 900 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 901 max_xfer_len = DWC2_DATA_BUF_SIZE; 902 903 /* Make sure that max_xfer_len is a multiple of max packet size. */ 904 num_packets = max_xfer_len / max; 905 max_xfer_len = num_packets * max; 906 907 /* Initialize channel */ 908 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 909 eptype, max); 910 911 /* Check if the target is a FS/LS device behind a HS hub */ 912 if (dev->speed != USB_SPEED_HIGH) { 913 uint8_t hub_addr; 914 uint8_t hub_port; 915 uint32_t hprt0 = readl(®s->hprt0); 916 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 917 DWC2_HPRT0_PRTSPD_HIGH) { 918 usb_find_usb2_hub_address_port(dev, &hub_addr, 919 &hub_port); 920 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 921 922 do_split = 1; 923 num_packets = 1; 924 max_xfer_len = max; 925 } 926 } 927 928 do { 929 int actual_len = 0; 930 uint32_t hcint; 931 int odd_frame = 0; 932 xfer_len = len - done; 933 934 if (xfer_len > max_xfer_len) 935 xfer_len = max_xfer_len; 936 else if (xfer_len > max) 937 num_packets = (xfer_len + max - 1) / max; 938 else 939 num_packets = 1; 940 941 if (complete_split) 942 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 943 else if (do_split) 944 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 945 946 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 947 int uframe_num = readl(&host_regs->hfnum); 948 if (!(uframe_num & 0x1)) 949 odd_frame = 1; 950 } 951 952 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 953 in, (char *)buffer + done, num_packets, 954 xfer_len, &actual_len, odd_frame); 955 956 hcint = readl(&hc_regs->hcint); 957 if (complete_split) { 958 stop_transfer = 0; 959 if (hcint & DWC2_HCINT_NYET) { 960 ret = 0; 961 int frame_num = DWC2_HFNUM_MAX_FRNUM & 962 readl(&host_regs->hfnum); 963 if (((frame_num - ssplit_frame_num) & 964 DWC2_HFNUM_MAX_FRNUM) > 4) 965 ret = -EAGAIN; 966 } else 967 complete_split = 0; 968 } else if (do_split) { 969 if (hcint & DWC2_HCINT_ACK) { 970 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 971 readl(&host_regs->hfnum); 972 ret = 0; 973 complete_split = 1; 974 } 975 } 976 977 if (ret) 978 break; 979 980 if (actual_len < xfer_len) 981 stop_transfer = 1; 982 983 done += actual_len; 984 985 /* Transactions are done when when either all data is transferred or 986 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 987 * is executed. 988 */ 989 } while (((done < len) && !stop_transfer) || complete_split); 990 991 writel(0, &hc_regs->hcintmsk); 992 writel(0xFFFFFFFF, &hc_regs->hcint); 993 994 dev->status = 0; 995 dev->act_len = done; 996 997 return ret; 998 } 999 1000 /* U-Boot USB transmission interface */ 1001 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 1002 unsigned long pipe, void *buffer, int len) 1003 { 1004 int devnum = usb_pipedevice(pipe); 1005 int ep = usb_pipeendpoint(pipe); 1006 u8* pid; 1007 1008 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { 1009 dev->status = 0; 1010 return -EINVAL; 1011 } 1012 1013 if (usb_pipein(pipe)) 1014 pid = &priv->in_data_toggle[devnum][ep]; 1015 else 1016 pid = &priv->out_data_toggle[devnum][ep]; 1017 1018 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); 1019 } 1020 1021 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 1022 unsigned long pipe, void *buffer, int len, 1023 struct devrequest *setup) 1024 { 1025 int devnum = usb_pipedevice(pipe); 1026 int ret, act_len; 1027 u8 pid; 1028 /* For CONTROL endpoint pid should start with DATA1 */ 1029 int status_direction; 1030 1031 if (devnum == priv->root_hub_devnum) { 1032 dev->status = 0; 1033 dev->speed = USB_SPEED_HIGH; 1034 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 1035 setup); 1036 } 1037 1038 /* SETUP stage */ 1039 pid = DWC2_HC_PID_SETUP; 1040 do { 1041 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 1042 } while (ret == -EAGAIN); 1043 if (ret) 1044 return ret; 1045 1046 /* DATA stage */ 1047 act_len = 0; 1048 if (buffer) { 1049 pid = DWC2_HC_PID_DATA1; 1050 do { 1051 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 1052 buffer, len); 1053 act_len += dev->act_len; 1054 buffer += dev->act_len; 1055 len -= dev->act_len; 1056 } while (ret == -EAGAIN); 1057 if (ret) 1058 return ret; 1059 status_direction = usb_pipeout(pipe); 1060 } else { 1061 /* No-data CONTROL always ends with an IN transaction */ 1062 status_direction = 1; 1063 } 1064 1065 /* STATUS stage */ 1066 pid = DWC2_HC_PID_DATA1; 1067 do { 1068 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1069 priv->status_buffer, 0); 1070 } while (ret == -EAGAIN); 1071 if (ret) 1072 return ret; 1073 1074 dev->act_len = act_len; 1075 1076 return 0; 1077 } 1078 1079 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1080 unsigned long pipe, void *buffer, int len, int interval) 1081 { 1082 unsigned long timeout; 1083 int ret; 1084 1085 /* FIXME: what is interval? */ 1086 1087 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1088 for (;;) { 1089 if (get_timer(0) > timeout) { 1090 printf("Timeout poll on interrupt endpoint\n"); 1091 return -ETIMEDOUT; 1092 } 1093 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1094 if (ret != -EAGAIN) 1095 return ret; 1096 } 1097 } 1098 1099 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) 1100 { 1101 struct dwc2_core_regs *regs = priv->regs; 1102 uint32_t snpsid; 1103 int i, j; 1104 1105 snpsid = readl(®s->gsnpsid); 1106 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); 1107 1108 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1109 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1110 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); 1111 return -ENODEV; 1112 } 1113 1114 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 1115 priv->ext_vbus = 1; 1116 #else 1117 priv->ext_vbus = 0; 1118 #endif 1119 1120 dwc_otg_core_init(priv); 1121 dwc_otg_core_host_init(dev, regs); 1122 1123 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1124 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1125 DWC2_HPRT0_PRTOVRCURRCHNG, 1126 DWC2_HPRT0_PRTRST); 1127 mdelay(50); 1128 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1129 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1130 DWC2_HPRT0_PRTRST); 1131 1132 for (i = 0; i < MAX_DEVICE; i++) { 1133 for (j = 0; j < MAX_ENDPOINT; j++) { 1134 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1135 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1136 } 1137 } 1138 1139 /* 1140 * Add a 1 second delay here. This gives the host controller 1141 * a bit time before the comminucation with the USB devices 1142 * is started (the bus is scanned) and fixes the USB detection 1143 * problems with some problematic USB keys. 1144 */ 1145 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 1146 mdelay(1000); 1147 1148 return 0; 1149 } 1150 1151 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1152 { 1153 /* Put everything in reset. */ 1154 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1155 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1156 DWC2_HPRT0_PRTOVRCURRCHNG, 1157 DWC2_HPRT0_PRTRST); 1158 } 1159 1160 #ifndef CONFIG_DM_USB 1161 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1162 int len, struct devrequest *setup) 1163 { 1164 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1165 } 1166 1167 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1168 int len) 1169 { 1170 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1171 } 1172 1173 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1174 int len, int interval) 1175 { 1176 return _submit_int_msg(&local, dev, pipe, buffer, len, interval); 1177 } 1178 1179 /* U-Boot USB control interface */ 1180 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1181 { 1182 struct dwc2_priv *priv = &local; 1183 1184 memset(priv, '\0', sizeof(*priv)); 1185 priv->root_hub_devnum = 0; 1186 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1187 priv->aligned_buffer = aligned_buffer_addr; 1188 priv->status_buffer = status_buffer_addr; 1189 1190 /* board-dependant init */ 1191 if (board_usb_init(index, USB_INIT_HOST)) 1192 return -1; 1193 1194 return dwc2_init_common(NULL, priv); 1195 } 1196 1197 int usb_lowlevel_stop(int index) 1198 { 1199 dwc2_uninit_common(local.regs); 1200 1201 return 0; 1202 } 1203 #endif 1204 1205 #ifdef CONFIG_DM_USB 1206 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1207 unsigned long pipe, void *buffer, int length, 1208 struct devrequest *setup) 1209 { 1210 struct dwc2_priv *priv = dev_get_priv(dev); 1211 1212 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1213 dev->name, udev, udev->dev->name, udev->portnr); 1214 1215 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1216 } 1217 1218 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1219 unsigned long pipe, void *buffer, int length) 1220 { 1221 struct dwc2_priv *priv = dev_get_priv(dev); 1222 1223 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1224 1225 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1226 } 1227 1228 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1229 unsigned long pipe, void *buffer, int length, 1230 int interval) 1231 { 1232 struct dwc2_priv *priv = dev_get_priv(dev); 1233 1234 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1235 1236 return _submit_int_msg(priv, udev, pipe, buffer, length, interval); 1237 } 1238 1239 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1240 { 1241 struct dwc2_priv *priv = dev_get_priv(dev); 1242 const void *prop; 1243 fdt_addr_t addr; 1244 1245 addr = devfdt_get_addr(dev); 1246 if (addr == FDT_ADDR_T_NONE) 1247 return -EINVAL; 1248 priv->regs = (struct dwc2_core_regs *)addr; 1249 1250 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), 1251 "disable-over-current", NULL); 1252 if (prop) 1253 priv->oc_disable = true; 1254 1255 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), 1256 "hnp-srp-disable", NULL); 1257 if (prop) 1258 priv->hnp_srp_disable = true; 1259 1260 return 0; 1261 } 1262 1263 static int dwc2_usb_probe(struct udevice *dev) 1264 { 1265 struct dwc2_priv *priv = dev_get_priv(dev); 1266 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); 1267 1268 bus_priv->desc_before_addr = true; 1269 1270 return dwc2_init_common(dev, priv); 1271 } 1272 1273 static int dwc2_usb_remove(struct udevice *dev) 1274 { 1275 struct dwc2_priv *priv = dev_get_priv(dev); 1276 1277 dwc2_uninit_common(priv->regs); 1278 1279 return 0; 1280 } 1281 1282 struct dm_usb_ops dwc2_usb_ops = { 1283 .control = dwc2_submit_control_msg, 1284 .bulk = dwc2_submit_bulk_msg, 1285 .interrupt = dwc2_submit_int_msg, 1286 }; 1287 1288 static const struct udevice_id dwc2_usb_ids[] = { 1289 { .compatible = "brcm,bcm2835-usb" }, 1290 { .compatible = "snps,dwc2" }, 1291 { } 1292 }; 1293 1294 U_BOOT_DRIVER(usb_dwc2) = { 1295 .name = "dwc2_usb", 1296 .id = UCLASS_USB, 1297 .of_match = dwc2_usb_ids, 1298 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1299 .probe = dwc2_usb_probe, 1300 .remove = dwc2_usb_remove, 1301 .ops = &dwc2_usb_ops, 1302 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1303 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1304 }; 1305 #endif 1306