1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <usb.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <phys2bus.h> 15 #include <usbroothubdes.h> 16 #include <wait_bit.h> 17 #include <asm/io.h> 18 19 #include "dwc2.h" 20 21 /* Use only HC channel 0. */ 22 #define DWC2_HC_CHANNEL 0 23 24 #define DWC2_STATUS_BUF_SIZE 64 25 #define DWC2_DATA_BUF_SIZE (64 * 1024) 26 27 #define MAX_DEVICE 16 28 #define MAX_ENDPOINT 16 29 30 struct dwc2_priv { 31 #ifdef CONFIG_DM_USB 32 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 33 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 34 #else 35 uint8_t *aligned_buffer; 36 uint8_t *status_buffer; 37 #endif 38 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 39 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 40 struct dwc2_core_regs *regs; 41 int root_hub_devnum; 42 }; 43 44 #ifndef CONFIG_DM_USB 45 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 46 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 47 ARCH_DMA_MINALIGN); 48 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 49 ARCH_DMA_MINALIGN); 50 51 static struct dwc2_priv local; 52 #endif 53 54 /* 55 * DWC2 IP interface 56 */ 57 58 /* 59 * Initializes the FSLSPClkSel field of the HCFG register 60 * depending on the PHY type. 61 */ 62 static void init_fslspclksel(struct dwc2_core_regs *regs) 63 { 64 uint32_t phyclk; 65 66 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 67 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 68 #else 69 /* High speed PHY running at full speed or high speed */ 70 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 71 #endif 72 73 #ifdef CONFIG_DWC2_ULPI_FS_LS 74 uint32_t hwcfg2 = readl(®s->ghwcfg2); 75 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 76 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 77 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 78 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 79 80 if (hval == 2 && fval == 1) 81 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 82 #endif 83 84 clrsetbits_le32(®s->host_regs.hcfg, 85 DWC2_HCFG_FSLSPCLKSEL_MASK, 86 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 87 } 88 89 /* 90 * Flush a Tx FIFO. 91 * 92 * @param regs Programming view of DWC_otg controller. 93 * @param num Tx FIFO to flush. 94 */ 95 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 96 { 97 int ret; 98 99 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 100 ®s->grstctl); 101 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 102 false, 1000, false); 103 if (ret) 104 printf("%s: Timeout!\n", __func__); 105 106 /* Wait for 3 PHY Clocks */ 107 udelay(1); 108 } 109 110 /* 111 * Flush Rx FIFO. 112 * 113 * @param regs Programming view of DWC_otg controller. 114 */ 115 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 116 { 117 int ret; 118 119 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 120 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 121 false, 1000, false); 122 if (ret) 123 printf("%s: Timeout!\n", __func__); 124 125 /* Wait for 3 PHY Clocks */ 126 udelay(1); 127 } 128 129 /* 130 * Do core a soft reset of the core. Be careful with this because it 131 * resets all the internal state machines of the core. 132 */ 133 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 134 { 135 int ret; 136 137 /* Wait for AHB master IDLE state. */ 138 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 139 true, 1000, false); 140 if (ret) 141 printf("%s: Timeout!\n", __func__); 142 143 /* Core Soft Reset */ 144 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 145 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST, 146 false, 1000, false); 147 if (ret) 148 printf("%s: Timeout!\n", __func__); 149 150 /* 151 * Wait for core to come out of reset. 152 * NOTE: This long sleep is _very_ important, otherwise the core will 153 * not stay in host mode after a connector ID change! 154 */ 155 mdelay(100); 156 } 157 158 /* 159 * This function initializes the DWC_otg controller registers for 160 * host mode. 161 * 162 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 163 * request queues. Host channels are reset to ensure that they are ready for 164 * performing transfers. 165 * 166 * @param regs Programming view of DWC_otg controller 167 * 168 */ 169 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) 170 { 171 uint32_t nptxfifosize = 0; 172 uint32_t ptxfifosize = 0; 173 uint32_t hprt0 = 0; 174 int i, ret, num_channels; 175 176 /* Restart the Phy Clock */ 177 writel(0, ®s->pcgcctl); 178 179 /* Initialize Host Configuration Register */ 180 init_fslspclksel(regs); 181 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 182 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 183 #endif 184 185 /* Configure data FIFO sizes */ 186 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 187 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 188 /* Rx FIFO */ 189 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 190 191 /* Non-periodic Tx FIFO */ 192 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 193 DWC2_FIFOSIZE_DEPTH_OFFSET; 194 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 195 DWC2_FIFOSIZE_STARTADDR_OFFSET; 196 writel(nptxfifosize, ®s->gnptxfsiz); 197 198 /* Periodic Tx FIFO */ 199 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 200 DWC2_FIFOSIZE_DEPTH_OFFSET; 201 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 202 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 203 DWC2_FIFOSIZE_STARTADDR_OFFSET; 204 writel(ptxfifosize, ®s->hptxfsiz); 205 } 206 #endif 207 208 /* Clear Host Set HNP Enable in the OTG Control Register */ 209 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 210 211 /* Make sure the FIFOs are flushed. */ 212 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 213 dwc_otg_flush_rx_fifo(regs); 214 215 /* Flush out any leftover queued requests. */ 216 num_channels = readl(®s->ghwcfg2); 217 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 218 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 219 num_channels += 1; 220 221 for (i = 0; i < num_channels; i++) 222 clrsetbits_le32(®s->hc_regs[i].hcchar, 223 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 224 DWC2_HCCHAR_CHDIS); 225 226 /* Halt all channels to put them into a known state. */ 227 for (i = 0; i < num_channels; i++) { 228 clrsetbits_le32(®s->hc_regs[i].hcchar, 229 DWC2_HCCHAR_EPDIR, 230 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 231 ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar, 232 DWC2_HCCHAR_CHEN, false, 1000, false); 233 if (ret) 234 printf("%s: Timeout!\n", __func__); 235 } 236 237 /* Turn on the vbus power. */ 238 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 239 hprt0 = readl(®s->hprt0); 240 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 241 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 242 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 243 hprt0 |= DWC2_HPRT0_PRTPWR; 244 writel(hprt0, ®s->hprt0); 245 } 246 } 247 } 248 249 /* 250 * This function initializes the DWC_otg controller registers and 251 * prepares the core for device mode or host mode operation. 252 * 253 * @param regs Programming view of the DWC_otg controller 254 */ 255 static void dwc_otg_core_init(struct dwc2_core_regs *regs) 256 { 257 uint32_t ahbcfg = 0; 258 uint32_t usbcfg = 0; 259 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 260 261 /* Common Initialization */ 262 usbcfg = readl(®s->gusbcfg); 263 264 /* Program the ULPI External VBUS bit if needed */ 265 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 266 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 267 #else 268 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 269 #endif 270 271 /* Set external TS Dline pulsing */ 272 #ifdef CONFIG_DWC2_TS_DLINE 273 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 274 #else 275 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 276 #endif 277 writel(usbcfg, ®s->gusbcfg); 278 279 /* Reset the Controller */ 280 dwc_otg_core_reset(regs); 281 282 /* 283 * This programming sequence needs to happen in FS mode before 284 * any other programming occurs 285 */ 286 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 287 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 288 /* If FS mode with FS PHY */ 289 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 290 291 /* Reset after a PHY select */ 292 dwc_otg_core_reset(regs); 293 294 /* 295 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 296 * Also do this on HNP Dev/Host mode switches (done in dev_init 297 * and host_init). 298 */ 299 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 300 init_fslspclksel(regs); 301 302 #ifdef CONFIG_DWC2_I2C_ENABLE 303 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 304 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 305 306 /* Program GI2CCTL.I2CEn */ 307 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 308 DWC2_GI2CCTL_I2CDEVADDR_MASK, 309 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 310 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 311 #endif 312 313 #else 314 /* High speed PHY. */ 315 316 /* 317 * HS PHY parameters. These parameters are preserved during 318 * soft reset so only program the first time. Do a soft reset 319 * immediately after setting phyif. 320 */ 321 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 322 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 323 324 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 325 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 326 usbcfg |= DWC2_GUSBCFG_DDRSEL; 327 #else 328 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 329 #endif 330 } else { /* UTMI+ interface */ 331 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) 332 usbcfg |= DWC2_GUSBCFG_PHYIF; 333 #endif 334 } 335 336 writel(usbcfg, ®s->gusbcfg); 337 338 /* Reset after setting the PHY parameters */ 339 dwc_otg_core_reset(regs); 340 #endif 341 342 usbcfg = readl(®s->gusbcfg); 343 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 344 #ifdef CONFIG_DWC2_ULPI_FS_LS 345 uint32_t hwcfg2 = readl(®s->ghwcfg2); 346 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 347 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 348 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 349 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 350 if (hval == 2 && fval == 1) { 351 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 352 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 353 } 354 #endif 355 writel(usbcfg, ®s->gusbcfg); 356 357 /* Program the GAHBCFG Register. */ 358 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 359 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 360 break; 361 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 362 while (brst_sz > 1) { 363 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 364 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 365 brst_sz >>= 1; 366 } 367 368 #ifdef CONFIG_DWC2_DMA_ENABLE 369 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 370 #endif 371 break; 372 373 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 374 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 375 #ifdef CONFIG_DWC2_DMA_ENABLE 376 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 377 #endif 378 break; 379 } 380 381 writel(ahbcfg, ®s->gahbcfg); 382 383 /* Program the GUSBCFG register for HNP/SRP. */ 384 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); 385 386 #ifdef CONFIG_DWC2_IC_USB_CAP 387 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); 388 #endif 389 } 390 391 /* 392 * Prepares a host channel for transferring packets to/from a specific 393 * endpoint. The HCCHARn register is set up with the characteristics specified 394 * in _hc. Host channel interrupts that may need to be serviced while this 395 * transfer is in progress are enabled. 396 * 397 * @param regs Programming view of DWC_otg controller 398 * @param hc Information needed to initialize the host channel 399 */ 400 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 401 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 402 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 403 { 404 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 405 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 406 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 407 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 408 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 409 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 410 411 if (dev->speed == USB_SPEED_LOW) 412 hcchar |= DWC2_HCCHAR_LSPDDEV; 413 414 /* 415 * Program the HCCHARn register with the endpoint characteristics 416 * for the current transfer. 417 */ 418 writel(hcchar, &hc_regs->hcchar); 419 420 /* Program the HCSPLIT register, default to no SPLIT */ 421 writel(0, &hc_regs->hcsplt); 422 } 423 424 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 425 uint8_t hub_devnum, uint8_t hub_port) 426 { 427 uint32_t hcsplt = 0; 428 429 hcsplt = DWC2_HCSPLT_SPLTENA; 430 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 431 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 432 433 /* Program the HCSPLIT register for SPLITs */ 434 writel(hcsplt, &hc_regs->hcsplt); 435 } 436 437 /* 438 * DWC2 to USB API interface 439 */ 440 /* Direction: In ; Request: Status */ 441 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 442 struct usb_device *dev, void *buffer, 443 int txlen, struct devrequest *cmd) 444 { 445 uint32_t hprt0 = 0; 446 uint32_t port_status = 0; 447 uint32_t port_change = 0; 448 int len = 0; 449 int stat = 0; 450 451 switch (cmd->requesttype & ~USB_DIR_IN) { 452 case 0: 453 *(uint16_t *)buffer = cpu_to_le16(1); 454 len = 2; 455 break; 456 case USB_RECIP_INTERFACE: 457 case USB_RECIP_ENDPOINT: 458 *(uint16_t *)buffer = cpu_to_le16(0); 459 len = 2; 460 break; 461 case USB_TYPE_CLASS: 462 *(uint32_t *)buffer = cpu_to_le32(0); 463 len = 4; 464 break; 465 case USB_RECIP_OTHER | USB_TYPE_CLASS: 466 hprt0 = readl(®s->hprt0); 467 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 468 port_status |= USB_PORT_STAT_CONNECTION; 469 if (hprt0 & DWC2_HPRT0_PRTENA) 470 port_status |= USB_PORT_STAT_ENABLE; 471 if (hprt0 & DWC2_HPRT0_PRTSUSP) 472 port_status |= USB_PORT_STAT_SUSPEND; 473 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 474 port_status |= USB_PORT_STAT_OVERCURRENT; 475 if (hprt0 & DWC2_HPRT0_PRTRST) 476 port_status |= USB_PORT_STAT_RESET; 477 if (hprt0 & DWC2_HPRT0_PRTPWR) 478 port_status |= USB_PORT_STAT_POWER; 479 480 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 481 port_status |= USB_PORT_STAT_LOW_SPEED; 482 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 483 DWC2_HPRT0_PRTSPD_HIGH) 484 port_status |= USB_PORT_STAT_HIGH_SPEED; 485 486 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 487 port_change |= USB_PORT_STAT_C_ENABLE; 488 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 489 port_change |= USB_PORT_STAT_C_CONNECTION; 490 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 491 port_change |= USB_PORT_STAT_C_OVERCURRENT; 492 493 *(uint32_t *)buffer = cpu_to_le32(port_status | 494 (port_change << 16)); 495 len = 4; 496 break; 497 default: 498 puts("unsupported root hub command\n"); 499 stat = USB_ST_STALLED; 500 } 501 502 dev->act_len = min(len, txlen); 503 dev->status = stat; 504 505 return stat; 506 } 507 508 /* Direction: In ; Request: Descriptor */ 509 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 510 void *buffer, int txlen, 511 struct devrequest *cmd) 512 { 513 unsigned char data[32]; 514 uint32_t dsc; 515 int len = 0; 516 int stat = 0; 517 uint16_t wValue = cpu_to_le16(cmd->value); 518 uint16_t wLength = cpu_to_le16(cmd->length); 519 520 switch (cmd->requesttype & ~USB_DIR_IN) { 521 case 0: 522 switch (wValue & 0xff00) { 523 case 0x0100: /* device descriptor */ 524 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 525 memcpy(buffer, root_hub_dev_des, len); 526 break; 527 case 0x0200: /* configuration descriptor */ 528 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 529 memcpy(buffer, root_hub_config_des, len); 530 break; 531 case 0x0300: /* string descriptors */ 532 switch (wValue & 0xff) { 533 case 0x00: 534 len = min3(txlen, (int)sizeof(root_hub_str_index0), 535 (int)wLength); 536 memcpy(buffer, root_hub_str_index0, len); 537 break; 538 case 0x01: 539 len = min3(txlen, (int)sizeof(root_hub_str_index1), 540 (int)wLength); 541 memcpy(buffer, root_hub_str_index1, len); 542 break; 543 } 544 break; 545 default: 546 stat = USB_ST_STALLED; 547 } 548 break; 549 550 case USB_TYPE_CLASS: 551 /* Root port config, set 1 port and nothing else. */ 552 dsc = 0x00000001; 553 554 data[0] = 9; /* min length; */ 555 data[1] = 0x29; 556 data[2] = dsc & RH_A_NDP; 557 data[3] = 0; 558 if (dsc & RH_A_PSM) 559 data[3] |= 0x1; 560 if (dsc & RH_A_NOCP) 561 data[3] |= 0x10; 562 else if (dsc & RH_A_OCPM) 563 data[3] |= 0x8; 564 565 /* corresponds to data[4-7] */ 566 data[5] = (dsc & RH_A_POTPGT) >> 24; 567 data[7] = dsc & RH_B_DR; 568 if (data[2] < 7) { 569 data[8] = 0xff; 570 } else { 571 data[0] += 2; 572 data[8] = (dsc & RH_B_DR) >> 8; 573 data[9] = 0xff; 574 data[10] = data[9]; 575 } 576 577 len = min3(txlen, (int)data[0], (int)wLength); 578 memcpy(buffer, data, len); 579 break; 580 default: 581 puts("unsupported root hub command\n"); 582 stat = USB_ST_STALLED; 583 } 584 585 dev->act_len = min(len, txlen); 586 dev->status = stat; 587 588 return stat; 589 } 590 591 /* Direction: In ; Request: Configuration */ 592 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 593 void *buffer, int txlen, 594 struct devrequest *cmd) 595 { 596 int len = 0; 597 int stat = 0; 598 599 switch (cmd->requesttype & ~USB_DIR_IN) { 600 case 0: 601 *(uint8_t *)buffer = 0x01; 602 len = 1; 603 break; 604 default: 605 puts("unsupported root hub command\n"); 606 stat = USB_ST_STALLED; 607 } 608 609 dev->act_len = min(len, txlen); 610 dev->status = stat; 611 612 return stat; 613 } 614 615 /* Direction: In */ 616 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 617 struct usb_device *dev, void *buffer, 618 int txlen, struct devrequest *cmd) 619 { 620 switch (cmd->request) { 621 case USB_REQ_GET_STATUS: 622 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 623 txlen, cmd); 624 case USB_REQ_GET_DESCRIPTOR: 625 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 626 txlen, cmd); 627 case USB_REQ_GET_CONFIGURATION: 628 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 629 txlen, cmd); 630 default: 631 puts("unsupported root hub command\n"); 632 return USB_ST_STALLED; 633 } 634 } 635 636 /* Direction: Out */ 637 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 638 struct usb_device *dev, 639 void *buffer, int txlen, 640 struct devrequest *cmd) 641 { 642 struct dwc2_core_regs *regs = priv->regs; 643 int len = 0; 644 int stat = 0; 645 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 646 uint16_t wValue = cpu_to_le16(cmd->value); 647 648 switch (bmrtype_breq & ~USB_DIR_IN) { 649 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 650 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 651 break; 652 653 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 654 switch (wValue) { 655 case USB_PORT_FEAT_C_CONNECTION: 656 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 657 break; 658 } 659 break; 660 661 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 662 switch (wValue) { 663 case USB_PORT_FEAT_SUSPEND: 664 break; 665 666 case USB_PORT_FEAT_RESET: 667 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 668 DWC2_HPRT0_PRTCONNDET | 669 DWC2_HPRT0_PRTENCHNG | 670 DWC2_HPRT0_PRTOVRCURRCHNG, 671 DWC2_HPRT0_PRTRST); 672 mdelay(50); 673 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 674 break; 675 676 case USB_PORT_FEAT_POWER: 677 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 678 DWC2_HPRT0_PRTCONNDET | 679 DWC2_HPRT0_PRTENCHNG | 680 DWC2_HPRT0_PRTOVRCURRCHNG, 681 DWC2_HPRT0_PRTRST); 682 break; 683 684 case USB_PORT_FEAT_ENABLE: 685 break; 686 } 687 break; 688 case (USB_REQ_SET_ADDRESS << 8): 689 priv->root_hub_devnum = wValue; 690 break; 691 case (USB_REQ_SET_CONFIGURATION << 8): 692 break; 693 default: 694 puts("unsupported root hub command\n"); 695 stat = USB_ST_STALLED; 696 } 697 698 len = min(len, txlen); 699 700 dev->act_len = len; 701 dev->status = stat; 702 703 return stat; 704 } 705 706 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 707 unsigned long pipe, void *buffer, int txlen, 708 struct devrequest *cmd) 709 { 710 int stat = 0; 711 712 if (usb_pipeint(pipe)) { 713 puts("Root-Hub submit IRQ: NOT implemented\n"); 714 return 0; 715 } 716 717 if (cmd->requesttype & USB_DIR_IN) 718 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 719 else 720 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 721 722 mdelay(1); 723 724 return stat; 725 } 726 727 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) 728 { 729 int ret; 730 uint32_t hcint, hctsiz; 731 732 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true, 733 1000, false); 734 if (ret) 735 return ret; 736 737 hcint = readl(&hc_regs->hcint); 738 hctsiz = readl(&hc_regs->hctsiz); 739 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 740 DWC2_HCTSIZ_XFERSIZE_OFFSET; 741 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 742 743 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 744 *toggle); 745 746 if (hcint & DWC2_HCINT_XFERCOMP) 747 return 0; 748 749 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 750 return -EAGAIN; 751 752 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 753 return -EINVAL; 754 } 755 756 static int dwc2_eptype[] = { 757 DWC2_HCCHAR_EPTYPE_ISOC, 758 DWC2_HCCHAR_EPTYPE_INTR, 759 DWC2_HCCHAR_EPTYPE_CONTROL, 760 DWC2_HCCHAR_EPTYPE_BULK, 761 }; 762 763 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 764 u8 *pid, int in, void *buffer, int num_packets, 765 int xfer_len, int *actual_len, int odd_frame) 766 { 767 int ret = 0; 768 uint32_t sub; 769 770 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 771 *pid, xfer_len, num_packets); 772 773 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 774 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 775 (*pid << DWC2_HCTSIZ_PID_OFFSET), 776 &hc_regs->hctsiz); 777 778 if (!in && xfer_len) { 779 memcpy(aligned_buffer, buffer, xfer_len); 780 781 flush_dcache_range((unsigned long)aligned_buffer, 782 (unsigned long)aligned_buffer + 783 roundup(xfer_len, ARCH_DMA_MINALIGN)); 784 } 785 786 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 787 788 /* Clear old interrupt conditions for this host channel. */ 789 writel(0x3fff, &hc_regs->hcint); 790 791 /* Set host channel enable after all other setup is complete. */ 792 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 793 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 794 DWC2_HCCHAR_ODDFRM, 795 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 796 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 797 DWC2_HCCHAR_CHEN); 798 799 ret = wait_for_chhltd(hc_regs, &sub, pid); 800 if (ret < 0) 801 return ret; 802 803 if (in) { 804 xfer_len -= sub; 805 806 invalidate_dcache_range((unsigned long)aligned_buffer, 807 (unsigned long)aligned_buffer + 808 roundup(xfer_len, ARCH_DMA_MINALIGN)); 809 810 memcpy(buffer, aligned_buffer, xfer_len); 811 } 812 *actual_len = xfer_len; 813 814 return ret; 815 } 816 817 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 818 unsigned long pipe, u8 *pid, int in, void *buffer, int len) 819 { 820 struct dwc2_core_regs *regs = priv->regs; 821 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 822 struct dwc2_host_regs *host_regs = ®s->host_regs; 823 int devnum = usb_pipedevice(pipe); 824 int ep = usb_pipeendpoint(pipe); 825 int max = usb_maxpacket(dev, pipe); 826 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 827 int done = 0; 828 int ret = 0; 829 int do_split = 0; 830 int complete_split = 0; 831 uint32_t xfer_len; 832 uint32_t num_packets; 833 int stop_transfer = 0; 834 uint32_t max_xfer_len; 835 int ssplit_frame_num = 0; 836 837 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 838 in, len); 839 840 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 841 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 842 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 843 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 844 max_xfer_len = DWC2_DATA_BUF_SIZE; 845 846 /* Make sure that max_xfer_len is a multiple of max packet size. */ 847 num_packets = max_xfer_len / max; 848 max_xfer_len = num_packets * max; 849 850 /* Initialize channel */ 851 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 852 eptype, max); 853 854 /* Check if the target is a FS/LS device behind a HS hub */ 855 if (dev->speed != USB_SPEED_HIGH) { 856 uint8_t hub_addr; 857 uint8_t hub_port; 858 uint32_t hprt0 = readl(®s->hprt0); 859 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 860 DWC2_HPRT0_PRTSPD_HIGH) { 861 usb_find_usb2_hub_address_port(dev, &hub_addr, 862 &hub_port); 863 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 864 865 do_split = 1; 866 num_packets = 1; 867 max_xfer_len = max; 868 } 869 } 870 871 do { 872 int actual_len = 0; 873 uint32_t hcint; 874 int odd_frame = 0; 875 xfer_len = len - done; 876 877 if (xfer_len > max_xfer_len) 878 xfer_len = max_xfer_len; 879 else if (xfer_len > max) 880 num_packets = (xfer_len + max - 1) / max; 881 else 882 num_packets = 1; 883 884 if (complete_split) 885 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 886 else if (do_split) 887 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 888 889 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 890 int uframe_num = readl(&host_regs->hfnum); 891 if (!(uframe_num & 0x1)) 892 odd_frame = 1; 893 } 894 895 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 896 in, (char *)buffer + done, num_packets, 897 xfer_len, &actual_len, odd_frame); 898 899 hcint = readl(&hc_regs->hcint); 900 if (complete_split) { 901 stop_transfer = 0; 902 if (hcint & DWC2_HCINT_NYET) { 903 ret = 0; 904 int frame_num = DWC2_HFNUM_MAX_FRNUM & 905 readl(&host_regs->hfnum); 906 if (((frame_num - ssplit_frame_num) & 907 DWC2_HFNUM_MAX_FRNUM) > 4) 908 ret = -EAGAIN; 909 } else 910 complete_split = 0; 911 } else if (do_split) { 912 if (hcint & DWC2_HCINT_ACK) { 913 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 914 readl(&host_regs->hfnum); 915 ret = 0; 916 complete_split = 1; 917 } 918 } 919 920 if (ret) 921 break; 922 923 if (actual_len < xfer_len) 924 stop_transfer = 1; 925 926 done += actual_len; 927 928 /* Transactions are done when when either all data is transferred or 929 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 930 * is executed. 931 */ 932 } while (((done < len) && !stop_transfer) || complete_split); 933 934 writel(0, &hc_regs->hcintmsk); 935 writel(0xFFFFFFFF, &hc_regs->hcint); 936 937 dev->status = 0; 938 dev->act_len = done; 939 940 return ret; 941 } 942 943 /* U-Boot USB transmission interface */ 944 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 945 unsigned long pipe, void *buffer, int len) 946 { 947 int devnum = usb_pipedevice(pipe); 948 int ep = usb_pipeendpoint(pipe); 949 u8* pid; 950 951 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { 952 dev->status = 0; 953 return -EINVAL; 954 } 955 956 if (usb_pipein(pipe)) 957 pid = &priv->in_data_toggle[devnum][ep]; 958 else 959 pid = &priv->out_data_toggle[devnum][ep]; 960 961 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); 962 } 963 964 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 965 unsigned long pipe, void *buffer, int len, 966 struct devrequest *setup) 967 { 968 int devnum = usb_pipedevice(pipe); 969 int ret, act_len; 970 u8 pid; 971 /* For CONTROL endpoint pid should start with DATA1 */ 972 int status_direction; 973 974 if (devnum == priv->root_hub_devnum) { 975 dev->status = 0; 976 dev->speed = USB_SPEED_HIGH; 977 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 978 setup); 979 } 980 981 /* SETUP stage */ 982 pid = DWC2_HC_PID_SETUP; 983 do { 984 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 985 } while (ret == -EAGAIN); 986 if (ret) 987 return ret; 988 989 /* DATA stage */ 990 act_len = 0; 991 if (buffer) { 992 pid = DWC2_HC_PID_DATA1; 993 do { 994 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 995 buffer, len); 996 act_len += dev->act_len; 997 buffer += dev->act_len; 998 len -= dev->act_len; 999 } while (ret == -EAGAIN); 1000 if (ret) 1001 return ret; 1002 status_direction = usb_pipeout(pipe); 1003 } else { 1004 /* No-data CONTROL always ends with an IN transaction */ 1005 status_direction = 1; 1006 } 1007 1008 /* STATUS stage */ 1009 pid = DWC2_HC_PID_DATA1; 1010 do { 1011 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1012 priv->status_buffer, 0); 1013 } while (ret == -EAGAIN); 1014 if (ret) 1015 return ret; 1016 1017 dev->act_len = act_len; 1018 1019 return 0; 1020 } 1021 1022 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1023 unsigned long pipe, void *buffer, int len, int interval) 1024 { 1025 unsigned long timeout; 1026 int ret; 1027 1028 /* FIXME: what is interval? */ 1029 1030 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1031 for (;;) { 1032 if (get_timer(0) > timeout) { 1033 printf("Timeout poll on interrupt endpoint\n"); 1034 return -ETIMEDOUT; 1035 } 1036 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1037 if (ret != -EAGAIN) 1038 return ret; 1039 } 1040 } 1041 1042 static int dwc2_init_common(struct dwc2_priv *priv) 1043 { 1044 struct dwc2_core_regs *regs = priv->regs; 1045 uint32_t snpsid; 1046 int i, j; 1047 1048 snpsid = readl(®s->gsnpsid); 1049 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); 1050 1051 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1052 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1053 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); 1054 return -ENODEV; 1055 } 1056 1057 dwc_otg_core_init(regs); 1058 dwc_otg_core_host_init(regs); 1059 1060 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1061 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1062 DWC2_HPRT0_PRTOVRCURRCHNG, 1063 DWC2_HPRT0_PRTRST); 1064 mdelay(50); 1065 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1066 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1067 DWC2_HPRT0_PRTRST); 1068 1069 for (i = 0; i < MAX_DEVICE; i++) { 1070 for (j = 0; j < MAX_ENDPOINT; j++) { 1071 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1072 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1073 } 1074 } 1075 1076 return 0; 1077 } 1078 1079 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1080 { 1081 /* Put everything in reset. */ 1082 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1083 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1084 DWC2_HPRT0_PRTOVRCURRCHNG, 1085 DWC2_HPRT0_PRTRST); 1086 } 1087 1088 #ifndef CONFIG_DM_USB 1089 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1090 int len, struct devrequest *setup) 1091 { 1092 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1093 } 1094 1095 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1096 int len) 1097 { 1098 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1099 } 1100 1101 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1102 int len, int interval) 1103 { 1104 return _submit_int_msg(&local, dev, pipe, buffer, len, interval); 1105 } 1106 1107 /* U-Boot USB control interface */ 1108 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1109 { 1110 struct dwc2_priv *priv = &local; 1111 1112 memset(priv, '\0', sizeof(*priv)); 1113 priv->root_hub_devnum = 0; 1114 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1115 priv->aligned_buffer = aligned_buffer_addr; 1116 priv->status_buffer = status_buffer_addr; 1117 1118 /* board-dependant init */ 1119 if (board_usb_init(index, USB_INIT_HOST)) 1120 return -1; 1121 1122 return dwc2_init_common(priv); 1123 } 1124 1125 int usb_lowlevel_stop(int index) 1126 { 1127 dwc2_uninit_common(local.regs); 1128 1129 return 0; 1130 } 1131 #endif 1132 1133 #ifdef CONFIG_DM_USB 1134 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1135 unsigned long pipe, void *buffer, int length, 1136 struct devrequest *setup) 1137 { 1138 struct dwc2_priv *priv = dev_get_priv(dev); 1139 1140 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1141 dev->name, udev, udev->dev->name, udev->portnr); 1142 1143 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1144 } 1145 1146 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1147 unsigned long pipe, void *buffer, int length) 1148 { 1149 struct dwc2_priv *priv = dev_get_priv(dev); 1150 1151 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1152 1153 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1154 } 1155 1156 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1157 unsigned long pipe, void *buffer, int length, 1158 int interval) 1159 { 1160 struct dwc2_priv *priv = dev_get_priv(dev); 1161 1162 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1163 1164 return _submit_int_msg(priv, udev, pipe, buffer, length, interval); 1165 } 1166 1167 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1168 { 1169 struct dwc2_priv *priv = dev_get_priv(dev); 1170 fdt_addr_t addr; 1171 1172 addr = dev_get_addr(dev); 1173 if (addr == FDT_ADDR_T_NONE) 1174 return -EINVAL; 1175 priv->regs = (struct dwc2_core_regs *)addr; 1176 1177 return 0; 1178 } 1179 1180 static int dwc2_usb_probe(struct udevice *dev) 1181 { 1182 struct dwc2_priv *priv = dev_get_priv(dev); 1183 1184 return dwc2_init_common(priv); 1185 } 1186 1187 static int dwc2_usb_remove(struct udevice *dev) 1188 { 1189 struct dwc2_priv *priv = dev_get_priv(dev); 1190 1191 dwc2_uninit_common(priv->regs); 1192 1193 return 0; 1194 } 1195 1196 struct dm_usb_ops dwc2_usb_ops = { 1197 .control = dwc2_submit_control_msg, 1198 .bulk = dwc2_submit_bulk_msg, 1199 .interrupt = dwc2_submit_int_msg, 1200 }; 1201 1202 static const struct udevice_id dwc2_usb_ids[] = { 1203 { .compatible = "brcm,bcm2835-usb" }, 1204 { .compatible = "snps,dwc2" }, 1205 { } 1206 }; 1207 1208 U_BOOT_DRIVER(usb_dwc2) = { 1209 .name = "dwc2_usb", 1210 .id = UCLASS_USB, 1211 .of_match = dwc2_usb_ids, 1212 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1213 .probe = dwc2_usb_probe, 1214 .remove = dwc2_usb_remove, 1215 .ops = &dwc2_usb_ops, 1216 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1217 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1218 }; 1219 #endif 1220