1# 2# USB Host Controller Drivers 3# 4comment "USB Host Controller Drivers" 5 6config USB_HOST 7 bool 8 9config USB_XHCI_HCD 10 bool "xHCI HCD (USB 3.0) support" 11 select USB_HOST 12 ---help--- 13 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 14 "SuperSpeed" host controller hardware. 15 16if USB_XHCI_HCD 17 18config USB_XHCI_DWC3 19 bool "DesignWare USB3 DRD Core Support" 20 help 21 Say Y or if your system has a Dual Role SuperSpeed 22 USB controller based on the DesignWare USB3 IP Core. 23 24config USB_XHCI_DWC3_OF_SIMPLE 25 bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" 26 select MISC 27 help 28 Support USB2/3 functionality in simple SoC integrations with 29 USB controller based on the DesignWare USB3 IP Core. 30 31config USB_XHCI_MVEBU 32 bool "MVEBU USB 3.0 support" 33 default y 34 depends on ARCH_MVEBU 35 select DM_REGULATOR 36 help 37 Choose this option to add support for USB 3.0 driver on mvebu 38 SoCs, which includes Armada8K, Armada3700 and other Armada 39 family SoCs. 40 41config USB_XHCI_PCI 42 bool "Support for PCI-based xHCI USB controller" 43 depends on DM_USB 44 default y if X86 45 help 46 Enables support for the PCI-based xHCI controller. 47 48config USB_XHCI_ROCKCHIP 49 bool "Support for Rockchip on-chip xHCI USB controller" 50 depends on ARCH_ROCKCHIP 51 depends on DM_REGULATOR 52 depends on DM_USB 53 default y 54 help 55 Enables support for the on-chip xHCI controller on Rockchip SoCs. 56 57config USB_XHCI_RCAR 58 bool "Renesas RCar USB 3.0 support" 59 default y 60 depends on ARCH_RMOBILE 61 help 62 Choose this option to add support for USB 3.0 driver on Renesas 63 RCar Gen3 SoCs. 64 65config USB_XHCI_STI 66 bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" 67 depends on ARCH_STI 68 default y 69 help 70 Enables support for the on-chip xHCI controller on STMicroelectronics 71 STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic 72 to configure the controller. 73 74config USB_XHCI_ZYNQMP 75 bool "Support for Xilinx ZynqMP on-chip xHCI USB controller" 76 depends on ARCH_ZYNQMP 77 help 78 Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs. 79 80config USB_XHCI_DRA7XX_INDEX 81 int "DRA7XX xHCI USB index" 82 range 0 1 83 default 0 84 depends on DRA7XX 85 help 86 Select the DRA7XX xHCI USB index. 87 Current supported values: 0, 1. 88 89config USB_XHCI_FSL 90 bool "Support for NXP Layerscape on-chip xHCI USB controller" 91 default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2 92 depends on !SPL_NO_USB 93 help 94 Enables support for the on-chip xHCI controller on NXP Layerscape SoCs. 95endif # USB_XHCI_HCD 96 97config USB_EHCI_HCD 98 bool "EHCI HCD (USB 2.0) support" 99 default y if ARCH_MX5 || ARCH_MX6 100 select USB_HOST 101 ---help--- 102 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 103 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. 104 If your USB host controller supports USB 2.0, you will likely want to 105 configure this Host Controller Driver. 106 107 EHCI controllers are packaged with "companion" host controllers (OHCI 108 or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports 109 will connect to EHCI if the device is high speed, otherwise they 110 connect to a companion controller. If you configure EHCI, you should 111 probably configure the OHCI (for NEC and some other vendors) USB Host 112 Controller Driver or UHCI (for Via motherboards) Host Controller 113 Driver too. 114 115 You may want to read <file:Documentation/usb/ehci.txt>. 116 117if USB_EHCI_HCD 118 119config USB_EHCI_ATMEL 120 bool "Support for Atmel on-chip EHCI USB controller" 121 depends on ARCH_AT91 122 default y 123 ---help--- 124 Enables support for the on-chip EHCI controller on Atmel chips. 125 126config USB_EHCI_MARVELL 127 bool "Support for Marvell on-chip EHCI USB controller" 128 depends on ARCH_MVEBU || KIRKWOOD || ORION5X 129 default y 130 ---help--- 131 Enables support for the on-chip EHCI controller on MVEBU SoCs. 132 133config USB_EHCI_MX6 134 bool "Support for i.MX6 on-chip EHCI USB controller" 135 depends on ARCH_MX6 136 default y 137 ---help--- 138 Enables support for the on-chip EHCI controller on i.MX6 SoCs. 139 140config USB_EHCI_MX7 141 bool "Support for i.MX7 on-chip EHCI USB controller" 142 depends on ARCH_MX7 143 default y 144 ---help--- 145 Enables support for the on-chip EHCI controller on i.MX7 SoCs. 146 147config USB_EHCI_OMAP 148 bool "Support for OMAP3+ on-chip EHCI USB controller" 149 depends on ARCH_OMAP2PLUS 150 default y 151 ---help--- 152 Enables support for the on-chip EHCI controller on OMAP3 and later 153 SoCs. 154 155if USB_EHCI_MX7 156 157config MXC_USB_OTG_HACTIVE 158 bool "USB Power pin high active" 159 ---help--- 160 Set the USB Power pin polarity to be high active (PWR_POL) 161 162endif 163 164config USB_EHCI_MSM 165 bool "Support for Qualcomm on-chip EHCI USB controller" 166 depends on DM_USB 167 select USB_ULPI_VIEWPORT 168 default n 169 ---help--- 170 Enables support for the on-chip EHCI controller on Qualcomm 171 Snapdragon SoCs. 172 This driver supports combination of Chipidea USB controller 173 and Synapsys USB PHY in host mode only. 174 175config USB_EHCI_PCI 176 bool "Support for PCI-based EHCI USB controller" 177 default y if X86 178 help 179 Enables support for the PCI-based EHCI controller. 180 181config USB_EHCI_ZYNQ 182 bool "Support for Xilinx Zynq on-chip EHCI USB controller" 183 depends on ARCH_ZYNQ 184 default y 185 ---help--- 186 Enable support for Zynq on-chip EHCI USB controller 187 188config USB_EHCI_GENERIC 189 bool "Support for generic EHCI USB controller" 190 depends on OF_CONTROL 191 depends on DM_USB 192 default n 193 ---help--- 194 Enables support for generic EHCI controller. 195 196config USB_EHCI_FSL 197 bool "Support for FSL on-chip EHCI USB controller" 198 default n 199 select CONFIG_EHCI_HCD_INIT_AFTER_RESET 200 ---help--- 201 Enables support for the on-chip EHCI controller on FSL chips. 202endif # USB_EHCI_HCD 203 204config USB_OHCI_HCD 205 bool "OHCI HCD (USB 1.1) support" 206 ---help--- 207 The Open Host Controller Interface (OHCI) is a standard for accessing 208 USB 1.1 host controller hardware. It does more in hardware than Intel's 209 UHCI specification. If your USB host controller follows the OHCI spec, 210 say Y. On most non-x86 systems, and on x86 hardware that's not using a 211 USB controller from Intel or VIA, this is appropriate. If your host 212 controller doesn't use PCI, this is probably appropriate. For a PCI 213 based system where you're not sure, the "lspci -v" entry will list the 214 right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. 215 216if USB_OHCI_HCD 217 218config USB_OHCI_GENERIC 219 bool "Support for generic OHCI USB controller" 220 depends on OF_CONTROL 221 depends on DM_USB 222 select USB_HOST 223 ---help--- 224 Enables support for generic OHCI controller. 225 226endif # USB_OHCI_HCD 227 228config USB_UHCI_HCD 229 bool "UHCI HCD (most Intel and VIA) support" 230 select USB_HOST 231 ---help--- 232 The Universal Host Controller Interface is a standard by Intel for 233 accessing the USB hardware in the PC (which is also called the USB 234 host controller). If your USB host controller conforms to this 235 standard, you may want to say Y, but see below. All recent boards 236 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, 237 i810, i820) conform to this standard. Also all VIA PCI chipsets 238 (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro 239 133) and LEON/GRLIB SoCs with the GRUSBHC controller. 240 If unsure, say Y. 241 242if USB_UHCI_HCD 243 244endif # USB_UHCI_HCD 245 246config USB_DWC2 247 bool "DesignWare USB2 Core support" 248 select USB_HOST 249 ---help--- 250 The DesignWare USB 2.0 controller is compliant with the 251 USB-Implementers Forum (USB-IF) USB 2.0 specifications. 252 Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) 253 operation is compliant to the controller Supplement. If you want to 254 enable this controller in host mode, say Y. 255 256if USB_DWC2 257config USB_DWC2_BUFFER_SIZE 258 int "Data buffer size in kB" 259 default 64 260 ---help--- 261 By default 64 kB buffer is used but if amount of RAM avaialble on 262 the target is not enough to accommodate allocation of buffer of 263 that size it is possible to shrink it. Smaller sizes should be fine 264 because larger transactions could be split in smaller ones. 265 266endif # USB_DWC2 267