1# 2# USB Host Controller Drivers 3# 4comment "USB Host Controller Drivers" 5 6config USB_HOST 7 bool 8 9config USB_XHCI_HCD 10 bool "xHCI HCD (USB 3.0) support" 11 select USB_HOST 12 ---help--- 13 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 14 "SuperSpeed" host controller hardware. 15 16if USB_XHCI_HCD 17 18config USB_XHCI_DWC3 19 bool "DesignWare USB3 DRD Core Support" 20 help 21 Say Y or if your system has a Dual Role SuperSpeed 22 USB controller based on the DesignWare USB3 IP Core. 23 24config USB_XHCI_DWC3_OF_SIMPLE 25 bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" 26 depends on DM_USB 27 default y if DRA7XX 28 help 29 Support USB2/3 functionality in simple SoC integrations with 30 USB controller based on the DesignWare USB3 IP Core. 31 32config USB_XHCI_MVEBU 33 bool "MVEBU USB 3.0 support" 34 default y 35 depends on ARCH_MVEBU 36 select DM_REGULATOR 37 help 38 Choose this option to add support for USB 3.0 driver on mvebu 39 SoCs, which includes Armada8K, Armada3700 and other Armada 40 family SoCs. 41 42config USB_XHCI_PCI 43 bool "Support for PCI-based xHCI USB controller" 44 depends on DM_USB 45 default y if X86 46 help 47 Enables support for the PCI-based xHCI controller. 48 49config USB_XHCI_ROCKCHIP 50 bool "Support for Rockchip on-chip xHCI USB controller" 51 depends on ARCH_ROCKCHIP 52 depends on DM_REGULATOR 53 depends on DM_USB 54 default y 55 help 56 Enables support for the on-chip xHCI controller on Rockchip SoCs. 57 58config USB_XHCI_RCAR 59 bool "Renesas RCar USB 3.0 support" 60 default y 61 depends on ARCH_RMOBILE 62 help 63 Choose this option to add support for USB 3.0 driver on Renesas 64 RCar Gen3 SoCs. 65 66config USB_XHCI_STI 67 bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" 68 depends on ARCH_STI 69 default y 70 help 71 Enables support for the on-chip xHCI controller on STMicroelectronics 72 STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic 73 to configure the controller. 74 75config USB_XHCI_ZYNQMP 76 bool "Support for Xilinx ZynqMP on-chip xHCI USB controller" 77 depends on ARCH_ZYNQMP 78 depends on DM_USB 79 help 80 Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs. 81 82config USB_XHCI_DRA7XX_INDEX 83 int "DRA7XX xHCI USB index" 84 range 0 1 85 default 0 86 depends on DRA7XX 87 help 88 Select the DRA7XX xHCI USB index. 89 Current supported values: 0, 1. 90 91config USB_XHCI_FSL 92 bool "Support for NXP Layerscape on-chip xHCI USB controller" 93 default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2 94 depends on !SPL_NO_USB 95 help 96 Enables support for the on-chip xHCI controller on NXP Layerscape SoCs. 97endif # USB_XHCI_HCD 98 99config USB_EHCI_HCD 100 bool "EHCI HCD (USB 2.0) support" 101 default y if ARCH_MX5 || ARCH_MX6 102 select USB_HOST 103 ---help--- 104 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 105 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. 106 If your USB host controller supports USB 2.0, you will likely want to 107 configure this Host Controller Driver. 108 109 EHCI controllers are packaged with "companion" host controllers (OHCI 110 or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports 111 will connect to EHCI if the device is high speed, otherwise they 112 connect to a companion controller. If you configure EHCI, you should 113 probably configure the OHCI (for NEC and some other vendors) USB Host 114 Controller Driver or UHCI (for Via motherboards) Host Controller 115 Driver too. 116 117 You may want to read <file:Documentation/usb/ehci.txt>. 118 119if USB_EHCI_HCD 120 121config USB_EHCI_ATMEL 122 bool "Support for Atmel on-chip EHCI USB controller" 123 depends on ARCH_AT91 124 default y 125 ---help--- 126 Enables support for the on-chip EHCI controller on Atmel chips. 127 128config USB_EHCI_MARVELL 129 bool "Support for Marvell on-chip EHCI USB controller" 130 depends on ARCH_MVEBU || KIRKWOOD || ORION5X 131 default y 132 ---help--- 133 Enables support for the on-chip EHCI controller on MVEBU SoCs. 134 135config USB_EHCI_MX6 136 bool "Support for i.MX6 on-chip EHCI USB controller" 137 depends on ARCH_MX6 138 default y 139 ---help--- 140 Enables support for the on-chip EHCI controller on i.MX6 SoCs. 141 142config USB_EHCI_MX7 143 bool "Support for i.MX7 on-chip EHCI USB controller" 144 depends on ARCH_MX7 145 default y 146 ---help--- 147 Enables support for the on-chip EHCI controller on i.MX7 SoCs. 148 149config USB_EHCI_OMAP 150 bool "Support for OMAP3+ on-chip EHCI USB controller" 151 depends on ARCH_OMAP2PLUS 152 default y 153 ---help--- 154 Enables support for the on-chip EHCI controller on OMAP3 and later 155 SoCs. 156 157if USB_EHCI_MX7 158 159config MXC_USB_OTG_HACTIVE 160 bool "USB Power pin high active" 161 ---help--- 162 Set the USB Power pin polarity to be high active (PWR_POL) 163 164endif 165 166config USB_EHCI_MSM 167 bool "Support for Qualcomm on-chip EHCI USB controller" 168 depends on DM_USB 169 select USB_ULPI_VIEWPORT 170 select MSM8916_USB_PHY 171 default n 172 ---help--- 173 Enables support for the on-chip EHCI controller on Qualcomm 174 Snapdragon SoCs. 175 176config USB_EHCI_PCI 177 bool "Support for PCI-based EHCI USB controller" 178 default y if X86 179 help 180 Enables support for the PCI-based EHCI controller. 181 182config USB_EHCI_ZYNQ 183 bool "Support for Xilinx Zynq on-chip EHCI USB controller" 184 depends on ARCH_ZYNQ 185 default y 186 ---help--- 187 Enable support for Zynq on-chip EHCI USB controller 188 189config USB_EHCI_GENERIC 190 bool "Support for generic EHCI USB controller" 191 depends on OF_CONTROL 192 depends on DM_USB 193 default n 194 ---help--- 195 Enables support for generic EHCI controller. 196 197config USB_EHCI_FSL 198 bool "Support for FSL on-chip EHCI USB controller" 199 default n 200 select CONFIG_EHCI_HCD_INIT_AFTER_RESET 201 ---help--- 202 Enables support for the on-chip EHCI controller on FSL chips. 203endif # USB_EHCI_HCD 204 205config USB_OHCI_HCD 206 bool "OHCI HCD (USB 1.1) support" 207 ---help--- 208 The Open Host Controller Interface (OHCI) is a standard for accessing 209 USB 1.1 host controller hardware. It does more in hardware than Intel's 210 UHCI specification. If your USB host controller follows the OHCI spec, 211 say Y. On most non-x86 systems, and on x86 hardware that's not using a 212 USB controller from Intel or VIA, this is appropriate. If your host 213 controller doesn't use PCI, this is probably appropriate. For a PCI 214 based system where you're not sure, the "lspci -v" entry will list the 215 right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. 216 217if USB_OHCI_HCD 218 219config USB_OHCI_GENERIC 220 bool "Support for generic OHCI USB controller" 221 depends on OF_CONTROL 222 depends on DM_USB 223 select USB_HOST 224 ---help--- 225 Enables support for generic OHCI controller. 226 227endif # USB_OHCI_HCD 228 229config USB_UHCI_HCD 230 bool "UHCI HCD (most Intel and VIA) support" 231 select USB_HOST 232 ---help--- 233 The Universal Host Controller Interface is a standard by Intel for 234 accessing the USB hardware in the PC (which is also called the USB 235 host controller). If your USB host controller conforms to this 236 standard, you may want to say Y, but see below. All recent boards 237 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, 238 i810, i820) conform to this standard. Also all VIA PCI chipsets 239 (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro 240 133) and LEON/GRLIB SoCs with the GRUSBHC controller. 241 If unsure, say Y. 242 243if USB_UHCI_HCD 244 245endif # USB_UHCI_HCD 246 247config USB_DWC2 248 bool "DesignWare USB2 Core support" 249 select USB_HOST 250 ---help--- 251 The DesignWare USB 2.0 controller is compliant with the 252 USB-Implementers Forum (USB-IF) USB 2.0 specifications. 253 Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) 254 operation is compliant to the controller Supplement. If you want to 255 enable this controller in host mode, say Y. 256 257if USB_DWC2 258config USB_DWC2_BUFFER_SIZE 259 int "Data buffer size in kB" 260 default 64 261 ---help--- 262 By default 64 kB buffer is used but if amount of RAM avaialble on 263 the target is not enough to accommodate allocation of buffer of 264 that size it is possible to shrink it. Smaller sizes should be fine 265 because larger transactions could be split in smaller ones. 266 267endif # USB_DWC2 268