1 /* 2 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers 3 * 4 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) 5 * Copyright (C) 2003 Robert Schwebel, Pengutronix 6 * Copyright (C) 2003 Benedikt Spranger, Pengutronix 7 * Copyright (C) 2003 David Brownell 8 * Copyright (C) 2003 Joshua Wise 9 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 * 25 * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); 26 */ 27 28 #define CONFIG_USB_PXA25X_SMALL 29 #define DRIVER_NAME "pxa25x_udc_linux" 30 #define ARCH_HAS_PREFETCH 31 32 #include <common.h> 33 #include <errno.h> 34 #include <asm/byteorder.h> 35 #include <asm/system.h> 36 #include <asm/mach-types.h> 37 #include <asm/unaligned.h> 38 #include <linux/compat.h> 39 #include <malloc.h> 40 #include <asm/io.h> 41 #include <asm/arch/pxa.h> 42 43 #include <usbdescriptors.h> 44 #include <linux/usb/ch9.h> 45 #include <linux/usb/gadget.h> 46 #include <usb/lin_gadget_compat.h> 47 #include <asm/arch/pxa-regs.h> 48 49 #include "pxa25x_udc.h" 50 51 /* 52 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x 53 * series processors. The UDC for the IXP 4xx series is very similar. 54 * There are fifteen endpoints, in addition to ep0. 55 * 56 * Such controller drivers work with a gadget driver. The gadget driver 57 * returns descriptors, implements configuration and data protocols used 58 * by the host to interact with this device, and allocates endpoints to 59 * the different protocol interfaces. The controller driver virtualizes 60 * usb hardware so that the gadget drivers will be more portable. 61 * 62 * This UDC hardware wants to implement a bit too much USB protocol, so 63 * it constrains the sorts of USB configuration change events that work. 64 * The errata for these chips are misleading; some "fixed" bugs from 65 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. 66 * 67 * Note that the UDC hardware supports DMA (except on IXP) but that's 68 * not used here. IN-DMA (to host) is simple enough, when the data is 69 * suitably aligned (16 bytes) ... the network stack doesn't do that, 70 * other software can. OUT-DMA is buggy in most chip versions, as well 71 * as poorly designed (data toggle not automatic). So this driver won't 72 * bother using DMA. (Mostly-working IN-DMA support was available in 73 * kernels before 2.6.23, but was never enabled or well tested.) 74 */ 75 76 #define DRIVER_VERSION "18-August-2012" 77 #define DRIVER_DESC "PXA 25x USB Device Controller driver" 78 79 static const char driver_name[] = "pxa25x_udc"; 80 static const char ep0name[] = "ep0"; 81 82 /* Watchdog */ 83 static inline void start_watchdog(struct pxa25x_udc *udc) 84 { 85 debug("Started watchdog\n"); 86 udc->watchdog.base = get_timer(0); 87 udc->watchdog.running = 1; 88 } 89 90 static inline void stop_watchdog(struct pxa25x_udc *udc) 91 { 92 udc->watchdog.running = 0; 93 debug("Stopped watchdog\n"); 94 } 95 96 static inline void test_watchdog(struct pxa25x_udc *udc) 97 { 98 if (!udc->watchdog.running) 99 return; 100 101 debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base), 102 udc->watchdog.period); 103 104 if (get_timer(udc->watchdog.base) >= udc->watchdog.period) { 105 stop_watchdog(udc); 106 udc->watchdog.function(udc); 107 } 108 } 109 110 static void udc_watchdog(struct pxa25x_udc *dev) 111 { 112 uint32_t udccs0 = readl(&dev->regs->udccs[0]); 113 114 debug("Fired up udc_watchdog\n"); 115 116 local_irq_disable(); 117 if (dev->ep0state == EP0_STALL 118 && (udccs0 & UDCCS0_FST) == 0 119 && (udccs0 & UDCCS0_SST) == 0) { 120 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]); 121 debug("ep0 re-stall\n"); 122 start_watchdog(dev); 123 } 124 local_irq_enable(); 125 } 126 127 #ifdef DEBUG 128 129 static const char * const state_name[] = { 130 "EP0_IDLE", 131 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", 132 "EP0_END_XFER", "EP0_STALL" 133 }; 134 135 static void 136 dump_udccr(const char *label) 137 { 138 u32 udccr = readl(&UDC_REGS->udccr); 139 debug("%s %02X =%s%s%s%s%s%s%s%s\n", 140 label, udccr, 141 (udccr & UDCCR_REM) ? " rem" : "", 142 (udccr & UDCCR_RSTIR) ? " rstir" : "", 143 (udccr & UDCCR_SRM) ? " srm" : "", 144 (udccr & UDCCR_SUSIR) ? " susir" : "", 145 (udccr & UDCCR_RESIR) ? " resir" : "", 146 (udccr & UDCCR_RSM) ? " rsm" : "", 147 (udccr & UDCCR_UDA) ? " uda" : "", 148 (udccr & UDCCR_UDE) ? " ude" : ""); 149 } 150 151 static void 152 dump_udccs0(const char *label) 153 { 154 u32 udccs0 = readl(&UDC_REGS->udccs[0]); 155 156 debug("%s %s %02X =%s%s%s%s%s%s%s%s\n", 157 label, state_name[the_controller->ep0state], udccs0, 158 (udccs0 & UDCCS0_SA) ? " sa" : "", 159 (udccs0 & UDCCS0_RNE) ? " rne" : "", 160 (udccs0 & UDCCS0_FST) ? " fst" : "", 161 (udccs0 & UDCCS0_SST) ? " sst" : "", 162 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "", 163 (udccs0 & UDCCS0_FTF) ? " ftf" : "", 164 (udccs0 & UDCCS0_IPR) ? " ipr" : "", 165 (udccs0 & UDCCS0_OPR) ? " opr" : ""); 166 } 167 168 static void 169 dump_state(struct pxa25x_udc *dev) 170 { 171 u32 tmp; 172 unsigned i; 173 174 debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", 175 state_name[dev->ep0state], 176 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0), 177 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0), 178 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl)); 179 dump_udccr("udccr"); 180 if (dev->has_cfr) { 181 tmp = readl(&UDC_REGS->udccfr); 182 debug("udccfr %02X =%s%s\n", tmp, 183 (tmp & UDCCFR_AREN) ? " aren" : "", 184 (tmp & UDCCFR_ACM) ? " acm" : ""); 185 } 186 187 if (!dev->driver) { 188 debug("no gadget driver bound\n"); 189 return; 190 } else 191 debug("ep0 driver '%s'\n", "ether"); 192 193 dump_udccs0("udccs0"); 194 debug("ep0 IN %lu/%lu, OUT %lu/%lu\n", 195 dev->stats.write.bytes, dev->stats.write.ops, 196 dev->stats.read.bytes, dev->stats.read.ops); 197 198 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { 199 if (dev->ep[i].desc == NULL) 200 continue; 201 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs); 202 } 203 } 204 205 #else /* DEBUG */ 206 207 static inline void dump_udccr(const char *label) { } 208 static inline void dump_udccs0(const char *label) { } 209 static inline void dump_state(struct pxa25x_udc *dev) { } 210 211 #endif /* DEBUG */ 212 213 /* 214 * --------------------------------------------------------------------------- 215 * endpoint related parts of the api to the usb controller hardware, 216 * used by gadget driver; and the inner talker-to-hardware core. 217 * --------------------------------------------------------------------------- 218 */ 219 220 static void pxa25x_ep_fifo_flush(struct usb_ep *ep); 221 static void nuke(struct pxa25x_ep *, int status); 222 223 /* one GPIO should control a D+ pullup, so host sees this device (or not) */ 224 static void pullup_off(void) 225 { 226 struct pxa2xx_udc_mach_info *mach = the_controller->mach; 227 228 if (mach->udc_command) 229 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); 230 } 231 232 static void pullup_on(void) 233 { 234 struct pxa2xx_udc_mach_info *mach = the_controller->mach; 235 236 if (mach->udc_command) 237 mach->udc_command(PXA2XX_UDC_CMD_CONNECT); 238 } 239 240 static void pio_irq_enable(int bEndpointAddress) 241 { 242 bEndpointAddress &= 0xf; 243 if (bEndpointAddress < 8) { 244 clrbits_le32(&the_controller->regs->uicr0, 245 1 << bEndpointAddress); 246 } else { 247 bEndpointAddress -= 8; 248 clrbits_le32(&the_controller->regs->uicr1, 249 1 << bEndpointAddress); 250 } 251 } 252 253 static void pio_irq_disable(int bEndpointAddress) 254 { 255 bEndpointAddress &= 0xf; 256 if (bEndpointAddress < 8) { 257 setbits_le32(&the_controller->regs->uicr0, 258 1 << bEndpointAddress); 259 } else { 260 bEndpointAddress -= 8; 261 setbits_le32(&the_controller->regs->uicr1, 262 1 << bEndpointAddress); 263 } 264 } 265 266 static inline void udc_set_mask_UDCCR(int mask) 267 { 268 /* 269 * The UDCCR reg contains mask and interrupt status bits, 270 * so using '|=' isn't safe as it may ack an interrupt. 271 */ 272 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 273 274 mask &= mask_bits; 275 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); 276 } 277 278 static inline void udc_clear_mask_UDCCR(int mask) 279 { 280 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 281 282 mask = ~mask & mask_bits; 283 clrbits_le32(&the_controller->regs->udccr, ~mask); 284 } 285 286 static inline void udc_ack_int_UDCCR(int mask) 287 { 288 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 289 290 mask &= ~mask_bits; 291 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); 292 } 293 294 /* 295 * endpoint enable/disable 296 * 297 * we need to verify the descriptors used to enable endpoints. since pxa25x 298 * endpoint configurations are fixed, and are pretty much always enabled, 299 * there's not a lot to manage here. 300 * 301 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, 302 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except 303 * for a single interface (with only the default altsetting) and for gadget 304 * drivers that don't halt endpoints (not reset by set_interface). that also 305 * means that if you use ISO, you must violate the USB spec rule that all 306 * iso endpoints must be in non-default altsettings. 307 */ 308 static int pxa25x_ep_enable(struct usb_ep *_ep, 309 const struct usb_endpoint_descriptor *desc) 310 { 311 struct pxa25x_ep *ep; 312 struct pxa25x_udc *dev; 313 314 ep = container_of(_ep, struct pxa25x_ep, ep); 315 if (!_ep || !desc || ep->desc || _ep->name == ep0name 316 || desc->bDescriptorType != USB_DT_ENDPOINT 317 || ep->bEndpointAddress != desc->bEndpointAddress 318 || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) { 319 printf("%s, bad ep or descriptor\n", __func__); 320 return -EINVAL; 321 } 322 323 /* xfer types must match, except that interrupt ~= bulk */ 324 if (ep->bmAttributes != desc->bmAttributes 325 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 326 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 327 printf("%s, %s type mismatch\n", __func__, _ep->name); 328 return -EINVAL; 329 } 330 331 /* hardware _could_ do smaller, but driver doesn't */ 332 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 333 && le16_to_cpu(desc->wMaxPacketSize) 334 != BULK_FIFO_SIZE) 335 || !desc->wMaxPacketSize) { 336 printf("%s, bad %s maxpacket\n", __func__, _ep->name); 337 return -ERANGE; 338 } 339 340 dev = ep->dev; 341 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { 342 printf("%s, bogus device state\n", __func__); 343 return -ESHUTDOWN; 344 } 345 346 ep->desc = desc; 347 ep->stopped = 0; 348 ep->pio_irqs = 0; 349 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); 350 351 /* flush fifo (mostly for OUT buffers) */ 352 pxa25x_ep_fifo_flush(_ep); 353 354 /* ... reset halt state too, if we could ... */ 355 356 debug("enabled %s\n", _ep->name); 357 return 0; 358 } 359 360 static int pxa25x_ep_disable(struct usb_ep *_ep) 361 { 362 struct pxa25x_ep *ep; 363 unsigned long flags; 364 365 ep = container_of(_ep, struct pxa25x_ep, ep); 366 if (!_ep || !ep->desc) { 367 printf("%s, %s not enabled\n", __func__, 368 _ep ? ep->ep.name : NULL); 369 return -EINVAL; 370 } 371 local_irq_save(flags); 372 373 nuke(ep, -ESHUTDOWN); 374 375 /* flush fifo (mostly for IN buffers) */ 376 pxa25x_ep_fifo_flush(_ep); 377 378 ep->desc = NULL; 379 ep->stopped = 1; 380 381 local_irq_restore(flags); 382 debug("%s disabled\n", _ep->name); 383 return 0; 384 } 385 386 /*-------------------------------------------------------------------------*/ 387 388 /* 389 * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers 390 * must still pass correctly initialized endpoints, since other controller 391 * drivers may care about how it's currently set up (dma issues etc). 392 */ 393 394 /* 395 * pxa25x_ep_alloc_request - allocate a request data structure 396 */ 397 static struct usb_request * 398 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 399 { 400 struct pxa25x_request *req; 401 402 req = kzalloc(sizeof(*req), gfp_flags); 403 if (!req) 404 return NULL; 405 406 INIT_LIST_HEAD(&req->queue); 407 return &req->req; 408 } 409 410 411 /* 412 * pxa25x_ep_free_request - deallocate a request data structure 413 */ 414 static void 415 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) 416 { 417 struct pxa25x_request *req; 418 419 req = container_of(_req, struct pxa25x_request, req); 420 WARN_ON(!list_empty(&req->queue)); 421 kfree(req); 422 } 423 424 /*-------------------------------------------------------------------------*/ 425 426 /* 427 * done - retire a request; caller blocked irqs 428 */ 429 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) 430 { 431 unsigned stopped = ep->stopped; 432 433 list_del_init(&req->queue); 434 435 if (likely(req->req.status == -EINPROGRESS)) 436 req->req.status = status; 437 else 438 status = req->req.status; 439 440 if (status && status != -ESHUTDOWN) 441 debug("complete %s req %p stat %d len %u/%u\n", 442 ep->ep.name, &req->req, status, 443 req->req.actual, req->req.length); 444 445 /* don't modify queue heads during completion callback */ 446 ep->stopped = 1; 447 req->req.complete(&ep->ep, &req->req); 448 ep->stopped = stopped; 449 } 450 451 452 static inline void ep0_idle(struct pxa25x_udc *dev) 453 { 454 dev->ep0state = EP0_IDLE; 455 } 456 457 static int 458 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max) 459 { 460 u8 *buf; 461 unsigned length, count; 462 463 debug("%s(): uddr %p\n", __func__, uddr); 464 465 buf = req->req.buf + req->req.actual; 466 prefetch(buf); 467 468 /* how big will this packet be? */ 469 length = min(req->req.length - req->req.actual, max); 470 req->req.actual += length; 471 472 count = length; 473 while (likely(count--)) 474 writeb(*buf++, uddr); 475 476 return length; 477 } 478 479 /* 480 * write to an IN endpoint fifo, as many packets as possible. 481 * irqs will use this to write the rest later. 482 * caller guarantees at least one packet buffer is ready (or a zlp). 483 */ 484 static int 485 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 486 { 487 unsigned max; 488 489 max = le16_to_cpu(ep->desc->wMaxPacketSize); 490 do { 491 unsigned count; 492 int is_last, is_short; 493 494 count = write_packet(ep->reg_uddr, req, max); 495 496 /* last packet is usually short (or a zlp) */ 497 if (unlikely(count != max)) 498 is_last = is_short = 1; 499 else { 500 if (likely(req->req.length != req->req.actual) 501 || req->req.zero) 502 is_last = 0; 503 else 504 is_last = 1; 505 /* interrupt/iso maxpacket may not fill the fifo */ 506 is_short = unlikely(max < ep->fifo_size); 507 } 508 509 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n", 510 ep->ep.name, count, 511 is_last ? "/L" : "", is_short ? "/S" : "", 512 req->req.length - req->req.actual, req); 513 514 /* 515 * let loose that packet. maybe try writing another one, 516 * double buffering might work. TSP, TPC, and TFS 517 * bit values are the same for all normal IN endpoints. 518 */ 519 writel(UDCCS_BI_TPC, ep->reg_udccs); 520 if (is_short) 521 writel(UDCCS_BI_TSP, ep->reg_udccs); 522 523 /* requests complete when all IN data is in the FIFO */ 524 if (is_last) { 525 done(ep, req, 0); 526 if (list_empty(&ep->queue)) 527 pio_irq_disable(ep->bEndpointAddress); 528 return 1; 529 } 530 531 /* 532 * TODO experiment: how robust can fifo mode tweaking be? 533 * double buffering is off in the default fifo mode, which 534 * prevents TFS from being set here. 535 */ 536 537 } while (readl(ep->reg_udccs) & UDCCS_BI_TFS); 538 return 0; 539 } 540 541 /* 542 * caller asserts req->pending (ep0 irq status nyet cleared); starts 543 * ep0 data stage. these chips want very simple state transitions. 544 */ 545 static inline 546 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) 547 { 548 writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]); 549 writel(USIR0_IR0, &dev->regs->usir0); 550 dev->req_pending = 0; 551 debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n", 552 __func__, tag, readl(&dev->regs->udccs[0]), flags, 553 readl(&dev->regs->usir1), readl(&dev->regs->usir0)); 554 } 555 556 static int 557 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 558 { 559 unsigned count; 560 int is_short; 561 562 count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE); 563 ep->dev->stats.write.bytes += count; 564 565 /* last packet "must be" short (or a zlp) */ 566 is_short = (count != EP0_FIFO_SIZE); 567 568 debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count, 569 req->req.length - req->req.actual, req); 570 571 if (unlikely(is_short)) { 572 if (ep->dev->req_pending) 573 ep0start(ep->dev, UDCCS0_IPR, "short IN"); 574 else 575 writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]); 576 577 count = req->req.length; 578 done(ep, req, 0); 579 ep0_idle(ep->dev); 580 581 /* 582 * This seems to get rid of lost status irqs in some cases: 583 * host responds quickly, or next request involves config 584 * change automagic, or should have been hidden, or ... 585 * 586 * FIXME get rid of all udelays possible... 587 */ 588 if (count >= EP0_FIFO_SIZE) { 589 count = 100; 590 do { 591 if ((readl(&ep->dev->regs->udccs[0]) & 592 UDCCS0_OPR) != 0) { 593 /* clear OPR, generate ack */ 594 writel(UDCCS0_OPR, 595 &ep->dev->regs->udccs[0]); 596 break; 597 } 598 count--; 599 udelay(1); 600 } while (count); 601 } 602 } else if (ep->dev->req_pending) 603 ep0start(ep->dev, 0, "IN"); 604 605 return is_short; 606 } 607 608 609 /* 610 * read_fifo - unload packet(s) from the fifo we use for usb OUT 611 * transfers and put them into the request. caller should have made 612 * sure there's at least one packet ready. 613 * 614 * returns true if the request completed because of short packet or the 615 * request buffer having filled (and maybe overran till end-of-packet). 616 */ 617 static int 618 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 619 { 620 u32 udccs; 621 u8 *buf; 622 unsigned bufferspace, count, is_short; 623 624 for (;;) { 625 /* 626 * make sure there's a packet in the FIFO. 627 * UDCCS_{BO,IO}_RPC are all the same bit value. 628 * UDCCS_{BO,IO}_RNE are all the same bit value. 629 */ 630 udccs = readl(ep->reg_udccs); 631 if (unlikely((udccs & UDCCS_BO_RPC) == 0)) 632 break; 633 buf = req->req.buf + req->req.actual; 634 prefetchw(buf); 635 bufferspace = req->req.length - req->req.actual; 636 637 /* read all bytes from this packet */ 638 if (likely(udccs & UDCCS_BO_RNE)) { 639 count = 1 + (0x0ff & readl(ep->reg_ubcr)); 640 req->req.actual += min(count, bufferspace); 641 } else /* zlp */ 642 count = 0; 643 is_short = (count < ep->ep.maxpacket); 644 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n", 645 ep->ep.name, udccs, count, 646 is_short ? "/S" : "", 647 req, req->req.actual, req->req.length); 648 while (likely(count-- != 0)) { 649 u8 byte = readb(ep->reg_uddr); 650 651 if (unlikely(bufferspace == 0)) { 652 /* 653 * this happens when the driver's buffer 654 * is smaller than what the host sent. 655 * discard the extra data. 656 */ 657 if (req->req.status != -EOVERFLOW) 658 printf("%s overflow %d\n", 659 ep->ep.name, count); 660 req->req.status = -EOVERFLOW; 661 } else { 662 *buf++ = byte; 663 bufferspace--; 664 } 665 } 666 writel(UDCCS_BO_RPC, ep->reg_udccs); 667 /* RPC/RSP/RNE could now reflect the other packet buffer */ 668 669 /* iso is one request per packet */ 670 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 671 if (udccs & UDCCS_IO_ROF) 672 req->req.status = -EHOSTUNREACH; 673 /* more like "is_done" */ 674 is_short = 1; 675 } 676 677 /* completion */ 678 if (is_short || req->req.actual == req->req.length) { 679 done(ep, req, 0); 680 if (list_empty(&ep->queue)) 681 pio_irq_disable(ep->bEndpointAddress); 682 return 1; 683 } 684 685 /* finished that packet. the next one may be waiting... */ 686 } 687 return 0; 688 } 689 690 /* 691 * special ep0 version of the above. no UBCR0 or double buffering; status 692 * handshaking is magic. most device protocols don't need control-OUT. 693 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other 694 * protocols do use them. 695 */ 696 static int 697 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 698 { 699 u8 *buf, byte; 700 unsigned bufferspace; 701 702 buf = req->req.buf + req->req.actual; 703 bufferspace = req->req.length - req->req.actual; 704 705 while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) { 706 byte = (u8)readb(&ep->dev->regs->uddr0); 707 708 if (unlikely(bufferspace == 0)) { 709 /* 710 * this happens when the driver's buffer 711 * is smaller than what the host sent. 712 * discard the extra data. 713 */ 714 if (req->req.status != -EOVERFLOW) 715 printf("%s overflow\n", ep->ep.name); 716 req->req.status = -EOVERFLOW; 717 } else { 718 *buf++ = byte; 719 req->req.actual++; 720 bufferspace--; 721 } 722 } 723 724 writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]); 725 726 /* completion */ 727 if (req->req.actual >= req->req.length) 728 return 1; 729 730 /* finished that packet. the next one may be waiting... */ 731 return 0; 732 } 733 734 /*-------------------------------------------------------------------------*/ 735 736 static int 737 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 738 { 739 struct pxa25x_request *req; 740 struct pxa25x_ep *ep; 741 struct pxa25x_udc *dev; 742 unsigned long flags; 743 744 req = container_of(_req, struct pxa25x_request, req); 745 if (unlikely(!_req || !_req->complete || !_req->buf 746 || !list_empty(&req->queue))) { 747 printf("%s, bad params\n", __func__); 748 return -EINVAL; 749 } 750 751 ep = container_of(_ep, struct pxa25x_ep, ep); 752 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { 753 printf("%s, bad ep\n", __func__); 754 return -EINVAL; 755 } 756 757 dev = ep->dev; 758 if (unlikely(!dev->driver 759 || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 760 printf("%s, bogus device state\n", __func__); 761 return -ESHUTDOWN; 762 } 763 764 /* 765 * iso is always one packet per request, that's the only way 766 * we can report per-packet status. that also helps with dma. 767 */ 768 if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 769 && req->req.length > 770 le16_to_cpu(ep->desc->wMaxPacketSize))) 771 return -EMSGSIZE; 772 773 debug_cond(NOISY, "%s queue req %p, len %d buf %p\n", 774 _ep->name, _req, _req->length, _req->buf); 775 776 local_irq_save(flags); 777 778 _req->status = -EINPROGRESS; 779 _req->actual = 0; 780 781 /* kickstart this i/o queue? */ 782 if (list_empty(&ep->queue) && !ep->stopped) { 783 if (ep->desc == NULL/* ep0 */) { 784 unsigned length = _req->length; 785 786 switch (dev->ep0state) { 787 case EP0_IN_DATA_PHASE: 788 dev->stats.write.ops++; 789 if (write_ep0_fifo(ep, req)) 790 req = NULL; 791 break; 792 793 case EP0_OUT_DATA_PHASE: 794 dev->stats.read.ops++; 795 /* messy ... */ 796 if (dev->req_config) { 797 debug("ep0 config ack%s\n", 798 dev->has_cfr ? "" : " raced"); 799 if (dev->has_cfr) 800 writel(UDCCFR_AREN|UDCCFR_ACM 801 |UDCCFR_MB1, 802 &ep->dev->regs->udccfr); 803 done(ep, req, 0); 804 dev->ep0state = EP0_END_XFER; 805 local_irq_restore(flags); 806 return 0; 807 } 808 if (dev->req_pending) 809 ep0start(dev, UDCCS0_IPR, "OUT"); 810 if (length == 0 || 811 ((readl( 812 &ep->dev->regs->udccs[0]) 813 & UDCCS0_RNE) != 0 814 && read_ep0_fifo(ep, req))) { 815 ep0_idle(dev); 816 done(ep, req, 0); 817 req = NULL; 818 } 819 break; 820 821 default: 822 printf("ep0 i/o, odd state %d\n", 823 dev->ep0state); 824 local_irq_restore(flags); 825 return -EL2HLT; 826 } 827 /* can the FIFO can satisfy the request immediately? */ 828 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { 829 if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0 830 && write_fifo(ep, req)) 831 req = NULL; 832 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0 833 && read_fifo(ep, req)) { 834 req = NULL; 835 } 836 837 if (likely(req && ep->desc)) 838 pio_irq_enable(ep->bEndpointAddress); 839 } 840 841 /* pio or dma irq handler advances the queue. */ 842 if (likely(req != NULL)) 843 list_add_tail(&req->queue, &ep->queue); 844 local_irq_restore(flags); 845 846 return 0; 847 } 848 849 850 /* 851 * nuke - dequeue ALL requests 852 */ 853 static void nuke(struct pxa25x_ep *ep, int status) 854 { 855 struct pxa25x_request *req; 856 857 /* called with irqs blocked */ 858 while (!list_empty(&ep->queue)) { 859 req = list_entry(ep->queue.next, 860 struct pxa25x_request, 861 queue); 862 done(ep, req, status); 863 } 864 if (ep->desc) 865 pio_irq_disable(ep->bEndpointAddress); 866 } 867 868 869 /* dequeue JUST ONE request */ 870 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 871 { 872 struct pxa25x_ep *ep; 873 struct pxa25x_request *req; 874 unsigned long flags; 875 876 ep = container_of(_ep, struct pxa25x_ep, ep); 877 if (!_ep || ep->ep.name == ep0name) 878 return -EINVAL; 879 880 local_irq_save(flags); 881 882 /* make sure it's actually queued on this endpoint */ 883 list_for_each_entry(req, &ep->queue, queue) { 884 if (&req->req == _req) 885 break; 886 } 887 if (&req->req != _req) { 888 local_irq_restore(flags); 889 return -EINVAL; 890 } 891 892 done(ep, req, -ECONNRESET); 893 894 local_irq_restore(flags); 895 return 0; 896 } 897 898 /*-------------------------------------------------------------------------*/ 899 900 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) 901 { 902 struct pxa25x_ep *ep; 903 unsigned long flags; 904 905 ep = container_of(_ep, struct pxa25x_ep, ep); 906 if (unlikely(!_ep 907 || (!ep->desc && ep->ep.name != ep0name)) 908 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 909 printf("%s, bad ep\n", __func__); 910 return -EINVAL; 911 } 912 if (value == 0) { 913 /* 914 * this path (reset toggle+halt) is needed to implement 915 * SET_INTERFACE on normal hardware. but it can't be 916 * done from software on the PXA UDC, and the hardware 917 * forgets to do it as part of SET_INTERFACE automagic. 918 */ 919 printf("only host can clear %s halt\n", _ep->name); 920 return -EROFS; 921 } 922 923 local_irq_save(flags); 924 925 if ((ep->bEndpointAddress & USB_DIR_IN) != 0 926 && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0 927 || !list_empty(&ep->queue))) { 928 local_irq_restore(flags); 929 return -EAGAIN; 930 } 931 932 /* FST bit is the same for control, bulk in, bulk out, interrupt in */ 933 writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs); 934 935 /* ep0 needs special care */ 936 if (!ep->desc) { 937 start_watchdog(ep->dev); 938 ep->dev->req_pending = 0; 939 ep->dev->ep0state = EP0_STALL; 940 941 /* and bulk/intr endpoints like dropping stalls too */ 942 } else { 943 unsigned i; 944 for (i = 0; i < 1000; i += 20) { 945 if (readl(ep->reg_udccs) & UDCCS_BI_SST) 946 break; 947 udelay(20); 948 } 949 } 950 local_irq_restore(flags); 951 952 debug("%s halt\n", _ep->name); 953 return 0; 954 } 955 956 static int pxa25x_ep_fifo_status(struct usb_ep *_ep) 957 { 958 struct pxa25x_ep *ep; 959 960 ep = container_of(_ep, struct pxa25x_ep, ep); 961 if (!_ep) { 962 printf("%s, bad ep\n", __func__); 963 return -ENODEV; 964 } 965 /* pxa can't report unclaimed bytes from IN fifos */ 966 if ((ep->bEndpointAddress & USB_DIR_IN) != 0) 967 return -EOPNOTSUPP; 968 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN 969 || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0) 970 return 0; 971 else 972 return (readl(ep->reg_ubcr) & 0xfff) + 1; 973 } 974 975 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) 976 { 977 struct pxa25x_ep *ep; 978 979 ep = container_of(_ep, struct pxa25x_ep, ep); 980 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { 981 printf("%s, bad ep\n", __func__); 982 return; 983 } 984 985 /* toggle and halt bits stay unchanged */ 986 987 /* for OUT, just read and discard the FIFO contents. */ 988 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { 989 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0) 990 (void)readb(ep->reg_uddr); 991 return; 992 } 993 994 /* most IN status is the same, but ISO can't stall */ 995 writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR 996 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 997 ? 0 : UDCCS_BI_SST), ep->reg_udccs); 998 } 999 1000 1001 static struct usb_ep_ops pxa25x_ep_ops = { 1002 .enable = pxa25x_ep_enable, 1003 .disable = pxa25x_ep_disable, 1004 1005 .alloc_request = pxa25x_ep_alloc_request, 1006 .free_request = pxa25x_ep_free_request, 1007 1008 .queue = pxa25x_ep_queue, 1009 .dequeue = pxa25x_ep_dequeue, 1010 1011 .set_halt = pxa25x_ep_set_halt, 1012 .fifo_status = pxa25x_ep_fifo_status, 1013 .fifo_flush = pxa25x_ep_fifo_flush, 1014 }; 1015 1016 1017 /* --------------------------------------------------------------------------- 1018 * device-scoped parts of the api to the usb controller hardware 1019 * --------------------------------------------------------------------------- 1020 */ 1021 1022 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) 1023 { 1024 return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) | 1025 (readl(&the_controller->regs->ufnrl) & 0xff); 1026 } 1027 1028 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) 1029 { 1030 /* host may not have enabled remote wakeup */ 1031 if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0) 1032 return -EHOSTUNREACH; 1033 udc_set_mask_UDCCR(UDCCR_RSM); 1034 return 0; 1035 } 1036 1037 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); 1038 static void udc_enable(struct pxa25x_udc *); 1039 static void udc_disable(struct pxa25x_udc *); 1040 1041 /* 1042 * We disable the UDC -- and its 48 MHz clock -- whenever it's not 1043 * in active use. 1044 */ 1045 static int pullup(struct pxa25x_udc *udc) 1046 { 1047 if (udc->pullup) 1048 pullup_on(); 1049 else 1050 pullup_off(); 1051 1052 1053 int is_active = udc->pullup; 1054 if (is_active) { 1055 if (!udc->active) { 1056 udc->active = 1; 1057 udc_enable(udc); 1058 } 1059 } else { 1060 if (udc->active) { 1061 if (udc->gadget.speed != USB_SPEED_UNKNOWN) 1062 stop_activity(udc, udc->driver); 1063 udc_disable(udc); 1064 udc->active = 0; 1065 } 1066 1067 } 1068 return 0; 1069 } 1070 1071 /* VBUS reporting logically comes from a transceiver */ 1072 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) 1073 { 1074 struct pxa25x_udc *udc; 1075 1076 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1077 printf("vbus %s\n", is_active ? "supplied" : "inactive"); 1078 pullup(udc); 1079 return 0; 1080 } 1081 1082 /* drivers may have software control over D+ pullup */ 1083 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) 1084 { 1085 struct pxa25x_udc *udc; 1086 1087 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1088 1089 /* not all boards support pullup control */ 1090 if (!udc->mach->udc_command) 1091 return -EOPNOTSUPP; 1092 1093 udc->pullup = (is_active != 0); 1094 pullup(udc); 1095 return 0; 1096 } 1097 1098 /* 1099 * boards may consume current from VBUS, up to 100-500mA based on config. 1100 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs 1101 * violate USB specs. 1102 */ 1103 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) 1104 { 1105 return -EOPNOTSUPP; 1106 } 1107 1108 static const struct usb_gadget_ops pxa25x_udc_ops = { 1109 .get_frame = pxa25x_udc_get_frame, 1110 .wakeup = pxa25x_udc_wakeup, 1111 .vbus_session = pxa25x_udc_vbus_session, 1112 .pullup = pxa25x_udc_pullup, 1113 .vbus_draw = pxa25x_udc_vbus_draw, 1114 }; 1115 1116 /*-------------------------------------------------------------------------*/ 1117 1118 /* 1119 * udc_disable - disable USB device controller 1120 */ 1121 static void udc_disable(struct pxa25x_udc *dev) 1122 { 1123 /* block all irqs */ 1124 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); 1125 writel(0xff, &dev->regs->uicr0); 1126 writel(0xff, &dev->regs->uicr1); 1127 writel(UFNRH_SIM, &dev->regs->ufnrh); 1128 1129 /* if hardware supports it, disconnect from usb */ 1130 pullup_off(); 1131 1132 udc_clear_mask_UDCCR(UDCCR_UDE); 1133 1134 ep0_idle(dev); 1135 dev->gadget.speed = USB_SPEED_UNKNOWN; 1136 } 1137 1138 /* 1139 * udc_reinit - initialize software state 1140 */ 1141 static void udc_reinit(struct pxa25x_udc *dev) 1142 { 1143 u32 i; 1144 1145 /* device/ep0 records init */ 1146 INIT_LIST_HEAD(&dev->gadget.ep_list); 1147 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 1148 dev->ep0state = EP0_IDLE; 1149 1150 /* basic endpoint records init */ 1151 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1152 struct pxa25x_ep *ep = &dev->ep[i]; 1153 1154 if (i != 0) 1155 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); 1156 1157 ep->desc = NULL; 1158 ep->stopped = 0; 1159 INIT_LIST_HEAD(&ep->queue); 1160 ep->pio_irqs = 0; 1161 } 1162 1163 /* the rest was statically initialized, and is read-only */ 1164 } 1165 1166 /* 1167 * until it's enabled, this UDC should be completely invisible 1168 * to any USB host. 1169 */ 1170 static void udc_enable(struct pxa25x_udc *dev) 1171 { 1172 debug("udc: enabling udc\n"); 1173 1174 udc_clear_mask_UDCCR(UDCCR_UDE); 1175 1176 /* 1177 * Try to clear these bits before we enable the udc. 1178 * Do not touch reset ack bit, we would take care of it in 1179 * interrupt handle routine 1180 */ 1181 udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR); 1182 1183 ep0_idle(dev); 1184 dev->gadget.speed = USB_SPEED_UNKNOWN; 1185 dev->stats.irqs = 0; 1186 1187 /* 1188 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: 1189 * - enable UDC 1190 * - if RESET is already in progress, ack interrupt 1191 * - unmask reset interrupt 1192 */ 1193 udc_set_mask_UDCCR(UDCCR_UDE); 1194 if (!(readl(&dev->regs->udccr) & UDCCR_UDA)) 1195 udc_ack_int_UDCCR(UDCCR_RSTIR); 1196 1197 if (dev->has_cfr /* UDC_RES2 is defined */) { 1198 /* 1199 * pxa255 (a0+) can avoid a set_config race that could 1200 * prevent gadget drivers from configuring correctly 1201 */ 1202 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr); 1203 } 1204 1205 /* enable suspend/resume and reset irqs */ 1206 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM); 1207 1208 /* enable ep0 irqs */ 1209 clrbits_le32(&dev->regs->uicr0, UICR0_IM0); 1210 1211 /* if hardware supports it, pullup D+ and wait for reset */ 1212 pullup_on(); 1213 } 1214 1215 static inline void clear_ep_state(struct pxa25x_udc *dev) 1216 { 1217 unsigned i; 1218 1219 /* 1220 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint 1221 * fifos, and pending transactions mustn't be continued in any case. 1222 */ 1223 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) 1224 nuke(&dev->ep[i], -ECONNABORTED); 1225 } 1226 1227 static void handle_ep0(struct pxa25x_udc *dev) 1228 { 1229 u32 udccs0 = readl(&dev->regs->udccs[0]); 1230 struct pxa25x_ep *ep = &dev->ep[0]; 1231 struct pxa25x_request *req; 1232 union { 1233 struct usb_ctrlrequest r; 1234 u8 raw[8]; 1235 u32 word[2]; 1236 } u; 1237 1238 if (list_empty(&ep->queue)) 1239 req = NULL; 1240 else 1241 req = list_entry(ep->queue.next, struct pxa25x_request, queue); 1242 1243 /* clear stall status */ 1244 if (udccs0 & UDCCS0_SST) { 1245 nuke(ep, -EPIPE); 1246 writel(UDCCS0_SST, &dev->regs->udccs[0]); 1247 stop_watchdog(dev); 1248 ep0_idle(dev); 1249 } 1250 1251 /* previous request unfinished? non-error iff back-to-back ... */ 1252 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { 1253 nuke(ep, 0); 1254 stop_watchdog(dev); 1255 ep0_idle(dev); 1256 } 1257 1258 switch (dev->ep0state) { 1259 case EP0_IDLE: 1260 /* late-breaking status? */ 1261 udccs0 = readl(&dev->regs->udccs[0]); 1262 1263 /* start control request? */ 1264 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) 1265 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { 1266 int i; 1267 1268 nuke(ep, -EPROTO); 1269 1270 /* read SETUP packet */ 1271 for (i = 0; i < 8; i++) { 1272 if (unlikely(!(readl(&dev->regs->udccs[0]) & 1273 UDCCS0_RNE))) { 1274 bad_setup: 1275 debug("SETUP %d!\n", i); 1276 goto stall; 1277 } 1278 u.raw[i] = (u8)readb(&dev->regs->uddr0); 1279 } 1280 if (unlikely((readl(&dev->regs->udccs[0]) & 1281 UDCCS0_RNE) != 0)) 1282 goto bad_setup; 1283 1284 got_setup: 1285 debug("SETUP %02x.%02x v%04x i%04x l%04x\n", 1286 u.r.bRequestType, u.r.bRequest, 1287 le16_to_cpu(u.r.wValue), 1288 le16_to_cpu(u.r.wIndex), 1289 le16_to_cpu(u.r.wLength)); 1290 1291 /* cope with automagic for some standard requests. */ 1292 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) 1293 == USB_TYPE_STANDARD; 1294 dev->req_config = 0; 1295 dev->req_pending = 1; 1296 switch (u.r.bRequest) { 1297 /* hardware restricts gadget drivers here! */ 1298 case USB_REQ_SET_CONFIGURATION: 1299 debug("GOT SET_CONFIGURATION\n"); 1300 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1301 /* 1302 * reflect hardware's automagic 1303 * up to the gadget driver. 1304 */ 1305 config_change: 1306 dev->req_config = 1; 1307 clear_ep_state(dev); 1308 /* 1309 * if !has_cfr, there's no synch 1310 * else use AREN (later) not SA|OPR 1311 * USIR0_IR0 acts edge sensitive 1312 */ 1313 } 1314 break; 1315 /* ... and here, even more ... */ 1316 case USB_REQ_SET_INTERFACE: 1317 if (u.r.bRequestType == USB_RECIP_INTERFACE) { 1318 /* 1319 * udc hardware is broken by design: 1320 * - altsetting may only be zero; 1321 * - hw resets all interfaces' eps; 1322 * - ep reset doesn't include halt(?). 1323 */ 1324 printf("broken set_interface (%d/%d)\n", 1325 le16_to_cpu(u.r.wIndex), 1326 le16_to_cpu(u.r.wValue)); 1327 goto config_change; 1328 } 1329 break; 1330 /* hardware was supposed to hide this */ 1331 case USB_REQ_SET_ADDRESS: 1332 debug("GOT SET ADDRESS\n"); 1333 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1334 ep0start(dev, 0, "address"); 1335 return; 1336 } 1337 break; 1338 } 1339 1340 if (u.r.bRequestType & USB_DIR_IN) 1341 dev->ep0state = EP0_IN_DATA_PHASE; 1342 else 1343 dev->ep0state = EP0_OUT_DATA_PHASE; 1344 1345 i = dev->driver->setup(&dev->gadget, &u.r); 1346 if (i < 0) { 1347 /* hardware automagic preventing STALL... */ 1348 if (dev->req_config) { 1349 /* 1350 * hardware sometimes neglects to tell 1351 * tell us about config change events, 1352 * so later ones may fail... 1353 */ 1354 printf("config change %02x fail %d?\n", 1355 u.r.bRequest, i); 1356 return; 1357 /* 1358 * TODO experiment: if has_cfr, 1359 * hardware didn't ACK; maybe we 1360 * could actually STALL! 1361 */ 1362 } 1363 if (0) { 1364 stall: 1365 /* uninitialized when goto stall */ 1366 i = 0; 1367 } 1368 debug("protocol STALL, " 1369 "%02x err %d\n", 1370 readl(&dev->regs->udccs[0]), i); 1371 1372 /* 1373 * the watchdog timer helps deal with cases 1374 * where udc seems to clear FST wrongly, and 1375 * then NAKs instead of STALLing. 1376 */ 1377 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall"); 1378 start_watchdog(dev); 1379 dev->ep0state = EP0_STALL; 1380 1381 /* deferred i/o == no response yet */ 1382 } else if (dev->req_pending) { 1383 if (likely(dev->ep0state == EP0_IN_DATA_PHASE 1384 || dev->req_std || u.r.wLength)) 1385 ep0start(dev, 0, "defer"); 1386 else 1387 ep0start(dev, UDCCS0_IPR, "defer/IPR"); 1388 } 1389 1390 /* expect at least one data or status stage irq */ 1391 return; 1392 1393 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) 1394 == (UDCCS0_OPR|UDCCS0_SA))) { 1395 unsigned i; 1396 1397 /* 1398 * pxa210/250 erratum 131 for B0/B1 says RNE lies. 1399 * still observed on a pxa255 a0. 1400 */ 1401 debug("e131\n"); 1402 nuke(ep, -EPROTO); 1403 1404 /* read SETUP data, but don't trust it too much */ 1405 for (i = 0; i < 8; i++) 1406 u.raw[i] = (u8)readb(&dev->regs->uddr0); 1407 if ((u.r.bRequestType & USB_RECIP_MASK) 1408 > USB_RECIP_OTHER) 1409 goto stall; 1410 if (u.word[0] == 0 && u.word[1] == 0) 1411 goto stall; 1412 goto got_setup; 1413 } else { 1414 /* 1415 * some random early IRQ: 1416 * - we acked FST 1417 * - IPR cleared 1418 * - OPR got set, without SA (likely status stage) 1419 */ 1420 debug("random IRQ %X %X\n", udccs0, 1421 readl(&dev->regs->udccs[0])); 1422 writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR), 1423 &dev->regs->udccs[0]); 1424 } 1425 break; 1426 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ 1427 if (udccs0 & UDCCS0_OPR) { 1428 debug("ep0in premature status\n"); 1429 if (req) 1430 done(ep, req, 0); 1431 ep0_idle(dev); 1432 } else /* irq was IPR clearing */ { 1433 if (req) { 1434 debug("next ep0 in packet\n"); 1435 /* this IN packet might finish the request */ 1436 (void) write_ep0_fifo(ep, req); 1437 } /* else IN token before response was written */ 1438 } 1439 break; 1440 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ 1441 if (udccs0 & UDCCS0_OPR) { 1442 if (req) { 1443 /* this OUT packet might finish the request */ 1444 if (read_ep0_fifo(ep, req)) 1445 done(ep, req, 0); 1446 /* else more OUT packets expected */ 1447 } /* else OUT token before read was issued */ 1448 } else /* irq was IPR clearing */ { 1449 debug("ep0out premature status\n"); 1450 if (req) 1451 done(ep, req, 0); 1452 ep0_idle(dev); 1453 } 1454 break; 1455 case EP0_END_XFER: 1456 if (req) 1457 done(ep, req, 0); 1458 /* 1459 * ack control-IN status (maybe in-zlp was skipped) 1460 * also appears after some config change events. 1461 */ 1462 if (udccs0 & UDCCS0_OPR) 1463 writel(UDCCS0_OPR, &dev->regs->udccs[0]); 1464 ep0_idle(dev); 1465 break; 1466 case EP0_STALL: 1467 writel(UDCCS0_FST, &dev->regs->udccs[0]); 1468 break; 1469 } 1470 1471 writel(USIR0_IR0, &dev->regs->usir0); 1472 } 1473 1474 static void handle_ep(struct pxa25x_ep *ep) 1475 { 1476 struct pxa25x_request *req; 1477 int is_in = ep->bEndpointAddress & USB_DIR_IN; 1478 int completed; 1479 u32 udccs, tmp; 1480 1481 do { 1482 completed = 0; 1483 if (likely(!list_empty(&ep->queue))) 1484 req = list_entry(ep->queue.next, 1485 struct pxa25x_request, queue); 1486 else 1487 req = NULL; 1488 1489 /* TODO check FST handling */ 1490 1491 udccs = readl(ep->reg_udccs); 1492 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ 1493 tmp = UDCCS_BI_TUR; 1494 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1495 tmp |= UDCCS_BI_SST; 1496 tmp &= udccs; 1497 if (likely(tmp)) 1498 writel(tmp, ep->reg_udccs); 1499 if (req && likely((udccs & UDCCS_BI_TFS) != 0)) 1500 completed = write_fifo(ep, req); 1501 1502 } else { /* irq from RPC (or for ISO, ROF) */ 1503 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1504 tmp = UDCCS_BO_SST | UDCCS_BO_DME; 1505 else 1506 tmp = UDCCS_IO_ROF | UDCCS_IO_DME; 1507 tmp &= udccs; 1508 if (likely(tmp)) 1509 writel(tmp, ep->reg_udccs); 1510 1511 /* fifos can hold packets, ready for reading... */ 1512 if (likely(req)) 1513 completed = read_fifo(ep, req); 1514 else 1515 pio_irq_disable(ep->bEndpointAddress); 1516 } 1517 ep->pio_irqs++; 1518 } while (completed); 1519 } 1520 1521 /* 1522 * pxa25x_udc_irq - interrupt handler 1523 * 1524 * avoid delays in ep0 processing. the control handshaking isn't always 1525 * under software control (pxa250c0 and the pxa255 are better), and delays 1526 * could cause usb protocol errors. 1527 */ 1528 static struct pxa25x_udc memory; 1529 static int 1530 pxa25x_udc_irq(void) 1531 { 1532 struct pxa25x_udc *dev = &memory; 1533 int handled; 1534 1535 test_watchdog(dev); 1536 1537 dev->stats.irqs++; 1538 do { 1539 u32 udccr = readl(&dev->regs->udccr); 1540 1541 handled = 0; 1542 1543 /* SUSpend Interrupt Request */ 1544 if (unlikely(udccr & UDCCR_SUSIR)) { 1545 udc_ack_int_UDCCR(UDCCR_SUSIR); 1546 handled = 1; 1547 debug("USB suspend\n"); 1548 1549 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1550 && dev->driver 1551 && dev->driver->suspend) 1552 dev->driver->suspend(&dev->gadget); 1553 ep0_idle(dev); 1554 } 1555 1556 /* RESume Interrupt Request */ 1557 if (unlikely(udccr & UDCCR_RESIR)) { 1558 udc_ack_int_UDCCR(UDCCR_RESIR); 1559 handled = 1; 1560 debug("USB resume\n"); 1561 1562 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1563 && dev->driver 1564 && dev->driver->resume) 1565 dev->driver->resume(&dev->gadget); 1566 } 1567 1568 /* ReSeT Interrupt Request - USB reset */ 1569 if (unlikely(udccr & UDCCR_RSTIR)) { 1570 udc_ack_int_UDCCR(UDCCR_RSTIR); 1571 handled = 1; 1572 1573 if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) { 1574 debug("USB reset start\n"); 1575 1576 /* 1577 * reset driver and endpoints, 1578 * in case that's not yet done 1579 */ 1580 stop_activity(dev, dev->driver); 1581 1582 } else { 1583 debug("USB reset end\n"); 1584 dev->gadget.speed = USB_SPEED_FULL; 1585 memset(&dev->stats, 0, sizeof dev->stats); 1586 /* driver and endpoints are still reset */ 1587 } 1588 1589 } else { 1590 u32 uicr0 = readl(&dev->regs->uicr0); 1591 u32 uicr1 = readl(&dev->regs->uicr1); 1592 u32 usir0 = readl(&dev->regs->usir0); 1593 u32 usir1 = readl(&dev->regs->usir1); 1594 1595 usir0 = usir0 & ~uicr0; 1596 usir1 = usir1 & ~uicr1; 1597 int i; 1598 1599 if (unlikely(!usir0 && !usir1)) 1600 continue; 1601 1602 debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0); 1603 1604 /* control traffic */ 1605 if (usir0 & USIR0_IR0) { 1606 dev->ep[0].pio_irqs++; 1607 handle_ep0(dev); 1608 handled = 1; 1609 } 1610 1611 /* endpoint data transfers */ 1612 for (i = 0; i < 8; i++) { 1613 u32 tmp = 1 << i; 1614 1615 if (i && (usir0 & tmp)) { 1616 handle_ep(&dev->ep[i]); 1617 setbits_le32(&dev->regs->usir0, tmp); 1618 handled = 1; 1619 } 1620 #ifndef CONFIG_USB_PXA25X_SMALL 1621 if (usir1 & tmp) { 1622 handle_ep(&dev->ep[i+8]); 1623 setbits_le32(&dev->regs->usir1, tmp); 1624 handled = 1; 1625 } 1626 #endif 1627 } 1628 } 1629 1630 /* we could also ask for 1 msec SOF (SIR) interrupts */ 1631 1632 } while (handled); 1633 return IRQ_HANDLED; 1634 } 1635 1636 /*-------------------------------------------------------------------------*/ 1637 1638 /* 1639 * this uses load-time allocation and initialization (instead of 1640 * doing it at run-time) to save code, eliminate fault paths, and 1641 * be more obviously correct. 1642 */ 1643 static struct pxa25x_udc memory = { 1644 .regs = UDC_REGS, 1645 1646 .gadget = { 1647 .ops = &pxa25x_udc_ops, 1648 .ep0 = &memory.ep[0].ep, 1649 .name = driver_name, 1650 }, 1651 1652 /* control endpoint */ 1653 .ep[0] = { 1654 .ep = { 1655 .name = ep0name, 1656 .ops = &pxa25x_ep_ops, 1657 .maxpacket = EP0_FIFO_SIZE, 1658 }, 1659 .dev = &memory, 1660 .reg_udccs = &UDC_REGS->udccs[0], 1661 .reg_uddr = &UDC_REGS->uddr0, 1662 }, 1663 1664 /* first group of endpoints */ 1665 .ep[1] = { 1666 .ep = { 1667 .name = "ep1in-bulk", 1668 .ops = &pxa25x_ep_ops, 1669 .maxpacket = BULK_FIFO_SIZE, 1670 }, 1671 .dev = &memory, 1672 .fifo_size = BULK_FIFO_SIZE, 1673 .bEndpointAddress = USB_DIR_IN | 1, 1674 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1675 .reg_udccs = &UDC_REGS->udccs[1], 1676 .reg_uddr = &UDC_REGS->uddr1, 1677 }, 1678 .ep[2] = { 1679 .ep = { 1680 .name = "ep2out-bulk", 1681 .ops = &pxa25x_ep_ops, 1682 .maxpacket = BULK_FIFO_SIZE, 1683 }, 1684 .dev = &memory, 1685 .fifo_size = BULK_FIFO_SIZE, 1686 .bEndpointAddress = 2, 1687 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1688 .reg_udccs = &UDC_REGS->udccs[2], 1689 .reg_ubcr = &UDC_REGS->ubcr2, 1690 .reg_uddr = &UDC_REGS->uddr2, 1691 }, 1692 #ifndef CONFIG_USB_PXA25X_SMALL 1693 .ep[3] = { 1694 .ep = { 1695 .name = "ep3in-iso", 1696 .ops = &pxa25x_ep_ops, 1697 .maxpacket = ISO_FIFO_SIZE, 1698 }, 1699 .dev = &memory, 1700 .fifo_size = ISO_FIFO_SIZE, 1701 .bEndpointAddress = USB_DIR_IN | 3, 1702 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1703 .reg_udccs = &UDC_REGS->udccs[3], 1704 .reg_uddr = &UDC_REGS->uddr3, 1705 }, 1706 .ep[4] = { 1707 .ep = { 1708 .name = "ep4out-iso", 1709 .ops = &pxa25x_ep_ops, 1710 .maxpacket = ISO_FIFO_SIZE, 1711 }, 1712 .dev = &memory, 1713 .fifo_size = ISO_FIFO_SIZE, 1714 .bEndpointAddress = 4, 1715 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1716 .reg_udccs = &UDC_REGS->udccs[4], 1717 .reg_ubcr = &UDC_REGS->ubcr4, 1718 .reg_uddr = &UDC_REGS->uddr4, 1719 }, 1720 .ep[5] = { 1721 .ep = { 1722 .name = "ep5in-int", 1723 .ops = &pxa25x_ep_ops, 1724 .maxpacket = INT_FIFO_SIZE, 1725 }, 1726 .dev = &memory, 1727 .fifo_size = INT_FIFO_SIZE, 1728 .bEndpointAddress = USB_DIR_IN | 5, 1729 .bmAttributes = USB_ENDPOINT_XFER_INT, 1730 .reg_udccs = &UDC_REGS->udccs[5], 1731 .reg_uddr = &UDC_REGS->uddr5, 1732 }, 1733 1734 /* second group of endpoints */ 1735 .ep[6] = { 1736 .ep = { 1737 .name = "ep6in-bulk", 1738 .ops = &pxa25x_ep_ops, 1739 .maxpacket = BULK_FIFO_SIZE, 1740 }, 1741 .dev = &memory, 1742 .fifo_size = BULK_FIFO_SIZE, 1743 .bEndpointAddress = USB_DIR_IN | 6, 1744 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1745 .reg_udccs = &UDC_REGS->udccs[6], 1746 .reg_uddr = &UDC_REGS->uddr6, 1747 }, 1748 .ep[7] = { 1749 .ep = { 1750 .name = "ep7out-bulk", 1751 .ops = &pxa25x_ep_ops, 1752 .maxpacket = BULK_FIFO_SIZE, 1753 }, 1754 .dev = &memory, 1755 .fifo_size = BULK_FIFO_SIZE, 1756 .bEndpointAddress = 7, 1757 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1758 .reg_udccs = &UDC_REGS->udccs[7], 1759 .reg_ubcr = &UDC_REGS->ubcr7, 1760 .reg_uddr = &UDC_REGS->uddr7, 1761 }, 1762 .ep[8] = { 1763 .ep = { 1764 .name = "ep8in-iso", 1765 .ops = &pxa25x_ep_ops, 1766 .maxpacket = ISO_FIFO_SIZE, 1767 }, 1768 .dev = &memory, 1769 .fifo_size = ISO_FIFO_SIZE, 1770 .bEndpointAddress = USB_DIR_IN | 8, 1771 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1772 .reg_udccs = &UDC_REGS->udccs[8], 1773 .reg_uddr = &UDC_REGS->uddr8, 1774 }, 1775 .ep[9] = { 1776 .ep = { 1777 .name = "ep9out-iso", 1778 .ops = &pxa25x_ep_ops, 1779 .maxpacket = ISO_FIFO_SIZE, 1780 }, 1781 .dev = &memory, 1782 .fifo_size = ISO_FIFO_SIZE, 1783 .bEndpointAddress = 9, 1784 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1785 .reg_udccs = &UDC_REGS->udccs[9], 1786 .reg_ubcr = &UDC_REGS->ubcr9, 1787 .reg_uddr = &UDC_REGS->uddr9, 1788 }, 1789 .ep[10] = { 1790 .ep = { 1791 .name = "ep10in-int", 1792 .ops = &pxa25x_ep_ops, 1793 .maxpacket = INT_FIFO_SIZE, 1794 }, 1795 .dev = &memory, 1796 .fifo_size = INT_FIFO_SIZE, 1797 .bEndpointAddress = USB_DIR_IN | 10, 1798 .bmAttributes = USB_ENDPOINT_XFER_INT, 1799 .reg_udccs = &UDC_REGS->udccs[10], 1800 .reg_uddr = &UDC_REGS->uddr10, 1801 }, 1802 1803 /* third group of endpoints */ 1804 .ep[11] = { 1805 .ep = { 1806 .name = "ep11in-bulk", 1807 .ops = &pxa25x_ep_ops, 1808 .maxpacket = BULK_FIFO_SIZE, 1809 }, 1810 .dev = &memory, 1811 .fifo_size = BULK_FIFO_SIZE, 1812 .bEndpointAddress = USB_DIR_IN | 11, 1813 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1814 .reg_udccs = &UDC_REGS->udccs[11], 1815 .reg_uddr = &UDC_REGS->uddr11, 1816 }, 1817 .ep[12] = { 1818 .ep = { 1819 .name = "ep12out-bulk", 1820 .ops = &pxa25x_ep_ops, 1821 .maxpacket = BULK_FIFO_SIZE, 1822 }, 1823 .dev = &memory, 1824 .fifo_size = BULK_FIFO_SIZE, 1825 .bEndpointAddress = 12, 1826 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1827 .reg_udccs = &UDC_REGS->udccs[12], 1828 .reg_ubcr = &UDC_REGS->ubcr12, 1829 .reg_uddr = &UDC_REGS->uddr12, 1830 }, 1831 .ep[13] = { 1832 .ep = { 1833 .name = "ep13in-iso", 1834 .ops = &pxa25x_ep_ops, 1835 .maxpacket = ISO_FIFO_SIZE, 1836 }, 1837 .dev = &memory, 1838 .fifo_size = ISO_FIFO_SIZE, 1839 .bEndpointAddress = USB_DIR_IN | 13, 1840 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1841 .reg_udccs = &UDC_REGS->udccs[13], 1842 .reg_uddr = &UDC_REGS->uddr13, 1843 }, 1844 .ep[14] = { 1845 .ep = { 1846 .name = "ep14out-iso", 1847 .ops = &pxa25x_ep_ops, 1848 .maxpacket = ISO_FIFO_SIZE, 1849 }, 1850 .dev = &memory, 1851 .fifo_size = ISO_FIFO_SIZE, 1852 .bEndpointAddress = 14, 1853 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1854 .reg_udccs = &UDC_REGS->udccs[14], 1855 .reg_ubcr = &UDC_REGS->ubcr14, 1856 .reg_uddr = &UDC_REGS->uddr14, 1857 }, 1858 .ep[15] = { 1859 .ep = { 1860 .name = "ep15in-int", 1861 .ops = &pxa25x_ep_ops, 1862 .maxpacket = INT_FIFO_SIZE, 1863 }, 1864 .dev = &memory, 1865 .fifo_size = INT_FIFO_SIZE, 1866 .bEndpointAddress = USB_DIR_IN | 15, 1867 .bmAttributes = USB_ENDPOINT_XFER_INT, 1868 .reg_udccs = &UDC_REGS->udccs[15], 1869 .reg_uddr = &UDC_REGS->uddr15, 1870 }, 1871 #endif /* !CONFIG_USB_PXA25X_SMALL */ 1872 }; 1873 1874 static void udc_command(int cmd) 1875 { 1876 switch (cmd) { 1877 case PXA2XX_UDC_CMD_CONNECT: 1878 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), 1879 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); 1880 1881 /* enable pullup */ 1882 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), 1883 GPCR(CONFIG_USB_DEV_PULLUP_GPIO)); 1884 1885 debug("Connected to USB\n"); 1886 break; 1887 1888 case PXA2XX_UDC_CMD_DISCONNECT: 1889 /* disable pullup resistor */ 1890 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), 1891 GPSR(CONFIG_USB_DEV_PULLUP_GPIO)); 1892 1893 /* setup pin as input, line will float */ 1894 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), 1895 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); 1896 1897 debug("Disconnected from USB\n"); 1898 break; 1899 } 1900 } 1901 1902 static struct pxa2xx_udc_mach_info mach_info = { 1903 .udc_command = udc_command, 1904 }; 1905 1906 /* 1907 * when a driver is successfully registered, it will receive 1908 * control requests including set_configuration(), which enables 1909 * non-control requests. then usb traffic follows until a 1910 * disconnect is reported. then a host may connect again, or 1911 * the driver might get unbound. 1912 */ 1913 int usb_gadget_register_driver(struct usb_gadget_driver *driver) 1914 { 1915 struct pxa25x_udc *dev = &memory; 1916 int retval; 1917 uint32_t chiprev; 1918 1919 if (!driver 1920 || driver->speed < USB_SPEED_FULL 1921 || !driver->disconnect 1922 || !driver->setup) 1923 return -EINVAL; 1924 if (!dev) 1925 return -ENODEV; 1926 if (dev->driver) 1927 return -EBUSY; 1928 1929 /* Enable clock for usb controller */ 1930 setbits_le32(CKEN, CKEN11_USB); 1931 1932 /* first hook up the driver ... */ 1933 dev->driver = driver; 1934 dev->pullup = 1; 1935 1936 /* trigger chiprev-specific logic */ 1937 switch ((chiprev = pxa_get_cpu_revision())) { 1938 case PXA255_A0: 1939 dev->has_cfr = 1; 1940 break; 1941 case PXA250_A0: 1942 case PXA250_A1: 1943 /* A0/A1 "not released"; ep 13, 15 unusable */ 1944 /* fall through */ 1945 case PXA250_B2: case PXA210_B2: 1946 case PXA250_B1: case PXA210_B1: 1947 case PXA250_B0: case PXA210_B0: 1948 /* OUT-DMA is broken ... */ 1949 /* fall through */ 1950 case PXA250_C0: case PXA210_C0: 1951 break; 1952 default: 1953 printf("%s: unrecognized processor: %08x\n", 1954 DRIVER_NAME, chiprev); 1955 return -ENODEV; 1956 } 1957 1958 the_controller = dev; 1959 1960 /* prepare watchdog timer */ 1961 dev->watchdog.running = 0; 1962 dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */ 1963 dev->watchdog.function = udc_watchdog; 1964 1965 udc_disable(dev); 1966 udc_reinit(dev); 1967 1968 dev->mach = &mach_info; 1969 1970 dev->gadget.name = "pxa2xx_udc"; 1971 retval = driver->bind(&dev->gadget); 1972 if (retval) { 1973 printf("bind to driver %s --> error %d\n", 1974 DRIVER_NAME, retval); 1975 dev->driver = NULL; 1976 return retval; 1977 } 1978 1979 /* 1980 * ... then enable host detection and ep0; and we're ready 1981 * for set_configuration as well as eventual disconnect. 1982 */ 1983 printf("registered gadget driver '%s'\n", DRIVER_NAME); 1984 1985 pullup(dev); 1986 dump_state(dev); 1987 return 0; 1988 } 1989 1990 static void 1991 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) 1992 { 1993 int i; 1994 1995 /* don't disconnect drivers more than once */ 1996 if (dev->gadget.speed == USB_SPEED_UNKNOWN) 1997 driver = NULL; 1998 dev->gadget.speed = USB_SPEED_UNKNOWN; 1999 2000 /* prevent new request submissions, kill any outstanding requests */ 2001 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 2002 struct pxa25x_ep *ep = &dev->ep[i]; 2003 2004 ep->stopped = 1; 2005 nuke(ep, -ESHUTDOWN); 2006 } 2007 stop_watchdog(dev); 2008 2009 /* report disconnect; the driver is already quiesced */ 2010 if (driver) 2011 driver->disconnect(&dev->gadget); 2012 2013 /* re-init driver-visible data structures */ 2014 udc_reinit(dev); 2015 } 2016 2017 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 2018 { 2019 struct pxa25x_udc *dev = the_controller; 2020 2021 if (!dev) 2022 return -ENODEV; 2023 if (!driver || driver != dev->driver || !driver->unbind) 2024 return -EINVAL; 2025 2026 local_irq_disable(); 2027 dev->pullup = 0; 2028 pullup(dev); 2029 stop_activity(dev, driver); 2030 local_irq_enable(); 2031 2032 driver->unbind(&dev->gadget); 2033 dev->driver = NULL; 2034 2035 printf("unregistered gadget driver '%s'\n", DRIVER_NAME); 2036 dump_state(dev); 2037 2038 the_controller = NULL; 2039 2040 clrbits_le32(CKEN, CKEN11_USB); 2041 2042 return 0; 2043 } 2044 2045 extern void udc_disconnect(void) 2046 { 2047 setbits_le32(CKEN, CKEN11_USB); 2048 udc_clear_mask_UDCCR(UDCCR_UDE); 2049 udc_command(PXA2XX_UDC_CMD_DISCONNECT); 2050 clrbits_le32(CKEN, CKEN11_USB); 2051 } 2052 2053 /*-------------------------------------------------------------------------*/ 2054 2055 extern int 2056 usb_gadget_handle_interrupts(void) 2057 { 2058 return pxa25x_udc_irq(); 2059 } 2060