1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers 4 * 5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) 6 * Copyright (C) 2003 Robert Schwebel, Pengutronix 7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix 8 * Copyright (C) 2003 David Brownell 9 * Copyright (C) 2003 Joshua Wise 10 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com> 11 * 12 * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); 13 */ 14 15 #define CONFIG_USB_PXA25X_SMALL 16 #define DRIVER_NAME "pxa25x_udc_linux" 17 #define ARCH_HAS_PREFETCH 18 19 #include <common.h> 20 #include <errno.h> 21 #include <asm/byteorder.h> 22 #include <asm/system.h> 23 #include <asm/mach-types.h> 24 #include <asm/unaligned.h> 25 #include <linux/compat.h> 26 #include <malloc.h> 27 #include <asm/io.h> 28 #include <asm/arch/pxa.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <asm/arch/pxa-regs.h> 33 34 #include "pxa25x_udc.h" 35 36 /* 37 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x 38 * series processors. The UDC for the IXP 4xx series is very similar. 39 * There are fifteen endpoints, in addition to ep0. 40 * 41 * Such controller drivers work with a gadget driver. The gadget driver 42 * returns descriptors, implements configuration and data protocols used 43 * by the host to interact with this device, and allocates endpoints to 44 * the different protocol interfaces. The controller driver virtualizes 45 * usb hardware so that the gadget drivers will be more portable. 46 * 47 * This UDC hardware wants to implement a bit too much USB protocol, so 48 * it constrains the sorts of USB configuration change events that work. 49 * The errata for these chips are misleading; some "fixed" bugs from 50 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. 51 * 52 * Note that the UDC hardware supports DMA (except on IXP) but that's 53 * not used here. IN-DMA (to host) is simple enough, when the data is 54 * suitably aligned (16 bytes) ... the network stack doesn't do that, 55 * other software can. OUT-DMA is buggy in most chip versions, as well 56 * as poorly designed (data toggle not automatic). So this driver won't 57 * bother using DMA. (Mostly-working IN-DMA support was available in 58 * kernels before 2.6.23, but was never enabled or well tested.) 59 */ 60 61 #define DRIVER_VERSION "18-August-2012" 62 #define DRIVER_DESC "PXA 25x USB Device Controller driver" 63 64 static const char driver_name[] = "pxa25x_udc"; 65 static const char ep0name[] = "ep0"; 66 67 /* Watchdog */ 68 static inline void start_watchdog(struct pxa25x_udc *udc) 69 { 70 debug("Started watchdog\n"); 71 udc->watchdog.base = get_timer(0); 72 udc->watchdog.running = 1; 73 } 74 75 static inline void stop_watchdog(struct pxa25x_udc *udc) 76 { 77 udc->watchdog.running = 0; 78 debug("Stopped watchdog\n"); 79 } 80 81 static inline void test_watchdog(struct pxa25x_udc *udc) 82 { 83 if (!udc->watchdog.running) 84 return; 85 86 debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base), 87 udc->watchdog.period); 88 89 if (get_timer(udc->watchdog.base) >= udc->watchdog.period) { 90 stop_watchdog(udc); 91 udc->watchdog.function(udc); 92 } 93 } 94 95 static void udc_watchdog(struct pxa25x_udc *dev) 96 { 97 uint32_t udccs0 = readl(&dev->regs->udccs[0]); 98 99 debug("Fired up udc_watchdog\n"); 100 101 local_irq_disable(); 102 if (dev->ep0state == EP0_STALL 103 && (udccs0 & UDCCS0_FST) == 0 104 && (udccs0 & UDCCS0_SST) == 0) { 105 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]); 106 debug("ep0 re-stall\n"); 107 start_watchdog(dev); 108 } 109 local_irq_enable(); 110 } 111 112 #ifdef DEBUG 113 114 static const char * const state_name[] = { 115 "EP0_IDLE", 116 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", 117 "EP0_END_XFER", "EP0_STALL" 118 }; 119 120 static void 121 dump_udccr(const char *label) 122 { 123 u32 udccr = readl(&UDC_REGS->udccr); 124 debug("%s %02X =%s%s%s%s%s%s%s%s\n", 125 label, udccr, 126 (udccr & UDCCR_REM) ? " rem" : "", 127 (udccr & UDCCR_RSTIR) ? " rstir" : "", 128 (udccr & UDCCR_SRM) ? " srm" : "", 129 (udccr & UDCCR_SUSIR) ? " susir" : "", 130 (udccr & UDCCR_RESIR) ? " resir" : "", 131 (udccr & UDCCR_RSM) ? " rsm" : "", 132 (udccr & UDCCR_UDA) ? " uda" : "", 133 (udccr & UDCCR_UDE) ? " ude" : ""); 134 } 135 136 static void 137 dump_udccs0(const char *label) 138 { 139 u32 udccs0 = readl(&UDC_REGS->udccs[0]); 140 141 debug("%s %s %02X =%s%s%s%s%s%s%s%s\n", 142 label, state_name[the_controller->ep0state], udccs0, 143 (udccs0 & UDCCS0_SA) ? " sa" : "", 144 (udccs0 & UDCCS0_RNE) ? " rne" : "", 145 (udccs0 & UDCCS0_FST) ? " fst" : "", 146 (udccs0 & UDCCS0_SST) ? " sst" : "", 147 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "", 148 (udccs0 & UDCCS0_FTF) ? " ftf" : "", 149 (udccs0 & UDCCS0_IPR) ? " ipr" : "", 150 (udccs0 & UDCCS0_OPR) ? " opr" : ""); 151 } 152 153 static void 154 dump_state(struct pxa25x_udc *dev) 155 { 156 u32 tmp; 157 unsigned i; 158 159 debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", 160 state_name[dev->ep0state], 161 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0), 162 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0), 163 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl)); 164 dump_udccr("udccr"); 165 if (dev->has_cfr) { 166 tmp = readl(&UDC_REGS->udccfr); 167 debug("udccfr %02X =%s%s\n", tmp, 168 (tmp & UDCCFR_AREN) ? " aren" : "", 169 (tmp & UDCCFR_ACM) ? " acm" : ""); 170 } 171 172 if (!dev->driver) { 173 debug("no gadget driver bound\n"); 174 return; 175 } else 176 debug("ep0 driver '%s'\n", "ether"); 177 178 dump_udccs0("udccs0"); 179 debug("ep0 IN %lu/%lu, OUT %lu/%lu\n", 180 dev->stats.write.bytes, dev->stats.write.ops, 181 dev->stats.read.bytes, dev->stats.read.ops); 182 183 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { 184 if (dev->ep[i].desc == NULL) 185 continue; 186 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs); 187 } 188 } 189 190 #else /* DEBUG */ 191 192 static inline void dump_udccr(const char *label) { } 193 static inline void dump_udccs0(const char *label) { } 194 static inline void dump_state(struct pxa25x_udc *dev) { } 195 196 #endif /* DEBUG */ 197 198 /* 199 * --------------------------------------------------------------------------- 200 * endpoint related parts of the api to the usb controller hardware, 201 * used by gadget driver; and the inner talker-to-hardware core. 202 * --------------------------------------------------------------------------- 203 */ 204 205 static void pxa25x_ep_fifo_flush(struct usb_ep *ep); 206 static void nuke(struct pxa25x_ep *, int status); 207 208 /* one GPIO should control a D+ pullup, so host sees this device (or not) */ 209 static void pullup_off(void) 210 { 211 struct pxa2xx_udc_mach_info *mach = the_controller->mach; 212 213 if (mach->udc_command) 214 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); 215 } 216 217 static void pullup_on(void) 218 { 219 struct pxa2xx_udc_mach_info *mach = the_controller->mach; 220 221 if (mach->udc_command) 222 mach->udc_command(PXA2XX_UDC_CMD_CONNECT); 223 } 224 225 static void pio_irq_enable(int bEndpointAddress) 226 { 227 bEndpointAddress &= 0xf; 228 if (bEndpointAddress < 8) { 229 clrbits_le32(&the_controller->regs->uicr0, 230 1 << bEndpointAddress); 231 } else { 232 bEndpointAddress -= 8; 233 clrbits_le32(&the_controller->regs->uicr1, 234 1 << bEndpointAddress); 235 } 236 } 237 238 static void pio_irq_disable(int bEndpointAddress) 239 { 240 bEndpointAddress &= 0xf; 241 if (bEndpointAddress < 8) { 242 setbits_le32(&the_controller->regs->uicr0, 243 1 << bEndpointAddress); 244 } else { 245 bEndpointAddress -= 8; 246 setbits_le32(&the_controller->regs->uicr1, 247 1 << bEndpointAddress); 248 } 249 } 250 251 static inline void udc_set_mask_UDCCR(int mask) 252 { 253 /* 254 * The UDCCR reg contains mask and interrupt status bits, 255 * so using '|=' isn't safe as it may ack an interrupt. 256 */ 257 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 258 259 mask &= mask_bits; 260 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); 261 } 262 263 static inline void udc_clear_mask_UDCCR(int mask) 264 { 265 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 266 267 mask = ~mask & mask_bits; 268 clrbits_le32(&the_controller->regs->udccr, ~mask); 269 } 270 271 static inline void udc_ack_int_UDCCR(int mask) 272 { 273 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 274 275 mask &= ~mask_bits; 276 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); 277 } 278 279 /* 280 * endpoint enable/disable 281 * 282 * we need to verify the descriptors used to enable endpoints. since pxa25x 283 * endpoint configurations are fixed, and are pretty much always enabled, 284 * there's not a lot to manage here. 285 * 286 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, 287 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except 288 * for a single interface (with only the default altsetting) and for gadget 289 * drivers that don't halt endpoints (not reset by set_interface). that also 290 * means that if you use ISO, you must violate the USB spec rule that all 291 * iso endpoints must be in non-default altsettings. 292 */ 293 static int pxa25x_ep_enable(struct usb_ep *_ep, 294 const struct usb_endpoint_descriptor *desc) 295 { 296 struct pxa25x_ep *ep; 297 struct pxa25x_udc *dev; 298 299 ep = container_of(_ep, struct pxa25x_ep, ep); 300 if (!_ep || !desc || ep->desc || _ep->name == ep0name 301 || desc->bDescriptorType != USB_DT_ENDPOINT 302 || ep->bEndpointAddress != desc->bEndpointAddress 303 || ep->fifo_size < 304 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) { 305 printf("%s, bad ep or descriptor\n", __func__); 306 return -EINVAL; 307 } 308 309 /* xfer types must match, except that interrupt ~= bulk */ 310 if (ep->bmAttributes != desc->bmAttributes 311 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 312 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 313 printf("%s, %s type mismatch\n", __func__, _ep->name); 314 return -EINVAL; 315 } 316 317 /* hardware _could_ do smaller, but driver doesn't */ 318 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 319 && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) 320 != BULK_FIFO_SIZE) 321 || !get_unaligned(&desc->wMaxPacketSize)) { 322 printf("%s, bad %s maxpacket\n", __func__, _ep->name); 323 return -ERANGE; 324 } 325 326 dev = ep->dev; 327 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { 328 printf("%s, bogus device state\n", __func__); 329 return -ESHUTDOWN; 330 } 331 332 ep->desc = desc; 333 ep->stopped = 0; 334 ep->pio_irqs = 0; 335 ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)); 336 337 /* flush fifo (mostly for OUT buffers) */ 338 pxa25x_ep_fifo_flush(_ep); 339 340 /* ... reset halt state too, if we could ... */ 341 342 debug("enabled %s\n", _ep->name); 343 return 0; 344 } 345 346 static int pxa25x_ep_disable(struct usb_ep *_ep) 347 { 348 struct pxa25x_ep *ep; 349 unsigned long flags; 350 351 ep = container_of(_ep, struct pxa25x_ep, ep); 352 if (!_ep || !ep->desc) { 353 printf("%s, %s not enabled\n", __func__, 354 _ep ? ep->ep.name : NULL); 355 return -EINVAL; 356 } 357 local_irq_save(flags); 358 359 nuke(ep, -ESHUTDOWN); 360 361 /* flush fifo (mostly for IN buffers) */ 362 pxa25x_ep_fifo_flush(_ep); 363 364 ep->desc = NULL; 365 ep->stopped = 1; 366 367 local_irq_restore(flags); 368 debug("%s disabled\n", _ep->name); 369 return 0; 370 } 371 372 /*-------------------------------------------------------------------------*/ 373 374 /* 375 * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers 376 * must still pass correctly initialized endpoints, since other controller 377 * drivers may care about how it's currently set up (dma issues etc). 378 */ 379 380 /* 381 * pxa25x_ep_alloc_request - allocate a request data structure 382 */ 383 static struct usb_request * 384 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 385 { 386 struct pxa25x_request *req; 387 388 req = kzalloc(sizeof(*req), gfp_flags); 389 if (!req) 390 return NULL; 391 392 INIT_LIST_HEAD(&req->queue); 393 return &req->req; 394 } 395 396 397 /* 398 * pxa25x_ep_free_request - deallocate a request data structure 399 */ 400 static void 401 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) 402 { 403 struct pxa25x_request *req; 404 405 req = container_of(_req, struct pxa25x_request, req); 406 WARN_ON(!list_empty(&req->queue)); 407 kfree(req); 408 } 409 410 /*-------------------------------------------------------------------------*/ 411 412 /* 413 * done - retire a request; caller blocked irqs 414 */ 415 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) 416 { 417 unsigned stopped = ep->stopped; 418 419 list_del_init(&req->queue); 420 421 if (likely(req->req.status == -EINPROGRESS)) 422 req->req.status = status; 423 else 424 status = req->req.status; 425 426 if (status && status != -ESHUTDOWN) 427 debug("complete %s req %p stat %d len %u/%u\n", 428 ep->ep.name, &req->req, status, 429 req->req.actual, req->req.length); 430 431 /* don't modify queue heads during completion callback */ 432 ep->stopped = 1; 433 req->req.complete(&ep->ep, &req->req); 434 ep->stopped = stopped; 435 } 436 437 438 static inline void ep0_idle(struct pxa25x_udc *dev) 439 { 440 dev->ep0state = EP0_IDLE; 441 } 442 443 static int 444 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max) 445 { 446 u8 *buf; 447 unsigned length, count; 448 449 debug("%s(): uddr %p\n", __func__, uddr); 450 451 buf = req->req.buf + req->req.actual; 452 prefetch(buf); 453 454 /* how big will this packet be? */ 455 length = min(req->req.length - req->req.actual, max); 456 req->req.actual += length; 457 458 count = length; 459 while (likely(count--)) 460 writeb(*buf++, uddr); 461 462 return length; 463 } 464 465 /* 466 * write to an IN endpoint fifo, as many packets as possible. 467 * irqs will use this to write the rest later. 468 * caller guarantees at least one packet buffer is ready (or a zlp). 469 */ 470 static int 471 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 472 { 473 unsigned max; 474 475 max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize)); 476 do { 477 unsigned count; 478 int is_last, is_short; 479 480 count = write_packet(ep->reg_uddr, req, max); 481 482 /* last packet is usually short (or a zlp) */ 483 if (unlikely(count != max)) 484 is_last = is_short = 1; 485 else { 486 if (likely(req->req.length != req->req.actual) 487 || req->req.zero) 488 is_last = 0; 489 else 490 is_last = 1; 491 /* interrupt/iso maxpacket may not fill the fifo */ 492 is_short = unlikely(max < ep->fifo_size); 493 } 494 495 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n", 496 ep->ep.name, count, 497 is_last ? "/L" : "", is_short ? "/S" : "", 498 req->req.length - req->req.actual, req); 499 500 /* 501 * let loose that packet. maybe try writing another one, 502 * double buffering might work. TSP, TPC, and TFS 503 * bit values are the same for all normal IN endpoints. 504 */ 505 writel(UDCCS_BI_TPC, ep->reg_udccs); 506 if (is_short) 507 writel(UDCCS_BI_TSP, ep->reg_udccs); 508 509 /* requests complete when all IN data is in the FIFO */ 510 if (is_last) { 511 done(ep, req, 0); 512 if (list_empty(&ep->queue)) 513 pio_irq_disable(ep->bEndpointAddress); 514 return 1; 515 } 516 517 /* 518 * TODO experiment: how robust can fifo mode tweaking be? 519 * double buffering is off in the default fifo mode, which 520 * prevents TFS from being set here. 521 */ 522 523 } while (readl(ep->reg_udccs) & UDCCS_BI_TFS); 524 return 0; 525 } 526 527 /* 528 * caller asserts req->pending (ep0 irq status nyet cleared); starts 529 * ep0 data stage. these chips want very simple state transitions. 530 */ 531 static inline 532 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) 533 { 534 writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]); 535 writel(USIR0_IR0, &dev->regs->usir0); 536 dev->req_pending = 0; 537 debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n", 538 __func__, tag, readl(&dev->regs->udccs[0]), flags, 539 readl(&dev->regs->usir1), readl(&dev->regs->usir0)); 540 } 541 542 static int 543 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 544 { 545 unsigned count; 546 int is_short; 547 548 count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE); 549 ep->dev->stats.write.bytes += count; 550 551 /* last packet "must be" short (or a zlp) */ 552 is_short = (count != EP0_FIFO_SIZE); 553 554 debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count, 555 req->req.length - req->req.actual, req); 556 557 if (unlikely(is_short)) { 558 if (ep->dev->req_pending) 559 ep0start(ep->dev, UDCCS0_IPR, "short IN"); 560 else 561 writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]); 562 563 count = req->req.length; 564 done(ep, req, 0); 565 ep0_idle(ep->dev); 566 567 /* 568 * This seems to get rid of lost status irqs in some cases: 569 * host responds quickly, or next request involves config 570 * change automagic, or should have been hidden, or ... 571 * 572 * FIXME get rid of all udelays possible... 573 */ 574 if (count >= EP0_FIFO_SIZE) { 575 count = 100; 576 do { 577 if ((readl(&ep->dev->regs->udccs[0]) & 578 UDCCS0_OPR) != 0) { 579 /* clear OPR, generate ack */ 580 writel(UDCCS0_OPR, 581 &ep->dev->regs->udccs[0]); 582 break; 583 } 584 count--; 585 udelay(1); 586 } while (count); 587 } 588 } else if (ep->dev->req_pending) 589 ep0start(ep->dev, 0, "IN"); 590 591 return is_short; 592 } 593 594 595 /* 596 * read_fifo - unload packet(s) from the fifo we use for usb OUT 597 * transfers and put them into the request. caller should have made 598 * sure there's at least one packet ready. 599 * 600 * returns true if the request completed because of short packet or the 601 * request buffer having filled (and maybe overran till end-of-packet). 602 */ 603 static int 604 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 605 { 606 u32 udccs; 607 u8 *buf; 608 unsigned bufferspace, count, is_short; 609 610 for (;;) { 611 /* 612 * make sure there's a packet in the FIFO. 613 * UDCCS_{BO,IO}_RPC are all the same bit value. 614 * UDCCS_{BO,IO}_RNE are all the same bit value. 615 */ 616 udccs = readl(ep->reg_udccs); 617 if (unlikely((udccs & UDCCS_BO_RPC) == 0)) 618 break; 619 buf = req->req.buf + req->req.actual; 620 prefetchw(buf); 621 bufferspace = req->req.length - req->req.actual; 622 623 /* read all bytes from this packet */ 624 if (likely(udccs & UDCCS_BO_RNE)) { 625 count = 1 + (0x0ff & readl(ep->reg_ubcr)); 626 req->req.actual += min(count, bufferspace); 627 } else /* zlp */ 628 count = 0; 629 is_short = (count < ep->ep.maxpacket); 630 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n", 631 ep->ep.name, udccs, count, 632 is_short ? "/S" : "", 633 req, req->req.actual, req->req.length); 634 while (likely(count-- != 0)) { 635 u8 byte = readb(ep->reg_uddr); 636 637 if (unlikely(bufferspace == 0)) { 638 /* 639 * this happens when the driver's buffer 640 * is smaller than what the host sent. 641 * discard the extra data. 642 */ 643 if (req->req.status != -EOVERFLOW) 644 printf("%s overflow %d\n", 645 ep->ep.name, count); 646 req->req.status = -EOVERFLOW; 647 } else { 648 *buf++ = byte; 649 bufferspace--; 650 } 651 } 652 writel(UDCCS_BO_RPC, ep->reg_udccs); 653 /* RPC/RSP/RNE could now reflect the other packet buffer */ 654 655 /* iso is one request per packet */ 656 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 657 if (udccs & UDCCS_IO_ROF) 658 req->req.status = -EHOSTUNREACH; 659 /* more like "is_done" */ 660 is_short = 1; 661 } 662 663 /* completion */ 664 if (is_short || req->req.actual == req->req.length) { 665 done(ep, req, 0); 666 if (list_empty(&ep->queue)) 667 pio_irq_disable(ep->bEndpointAddress); 668 return 1; 669 } 670 671 /* finished that packet. the next one may be waiting... */ 672 } 673 return 0; 674 } 675 676 /* 677 * special ep0 version of the above. no UBCR0 or double buffering; status 678 * handshaking is magic. most device protocols don't need control-OUT. 679 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other 680 * protocols do use them. 681 */ 682 static int 683 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 684 { 685 u8 *buf, byte; 686 unsigned bufferspace; 687 688 buf = req->req.buf + req->req.actual; 689 bufferspace = req->req.length - req->req.actual; 690 691 while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) { 692 byte = (u8)readb(&ep->dev->regs->uddr0); 693 694 if (unlikely(bufferspace == 0)) { 695 /* 696 * this happens when the driver's buffer 697 * is smaller than what the host sent. 698 * discard the extra data. 699 */ 700 if (req->req.status != -EOVERFLOW) 701 printf("%s overflow\n", ep->ep.name); 702 req->req.status = -EOVERFLOW; 703 } else { 704 *buf++ = byte; 705 req->req.actual++; 706 bufferspace--; 707 } 708 } 709 710 writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]); 711 712 /* completion */ 713 if (req->req.actual >= req->req.length) 714 return 1; 715 716 /* finished that packet. the next one may be waiting... */ 717 return 0; 718 } 719 720 /*-------------------------------------------------------------------------*/ 721 722 static int 723 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 724 { 725 struct pxa25x_request *req; 726 struct pxa25x_ep *ep; 727 struct pxa25x_udc *dev; 728 unsigned long flags; 729 730 req = container_of(_req, struct pxa25x_request, req); 731 if (unlikely(!_req || !_req->complete || !_req->buf 732 || !list_empty(&req->queue))) { 733 printf("%s, bad params\n", __func__); 734 return -EINVAL; 735 } 736 737 ep = container_of(_ep, struct pxa25x_ep, ep); 738 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { 739 printf("%s, bad ep\n", __func__); 740 return -EINVAL; 741 } 742 743 dev = ep->dev; 744 if (unlikely(!dev->driver 745 || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 746 printf("%s, bogus device state\n", __func__); 747 return -ESHUTDOWN; 748 } 749 750 /* 751 * iso is always one packet per request, that's the only way 752 * we can report per-packet status. that also helps with dma. 753 */ 754 if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 755 && req->req.length > 756 le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize)))) 757 return -EMSGSIZE; 758 759 debug_cond(NOISY, "%s queue req %p, len %d buf %p\n", 760 _ep->name, _req, _req->length, _req->buf); 761 762 local_irq_save(flags); 763 764 _req->status = -EINPROGRESS; 765 _req->actual = 0; 766 767 /* kickstart this i/o queue? */ 768 if (list_empty(&ep->queue) && !ep->stopped) { 769 if (ep->desc == NULL/* ep0 */) { 770 unsigned length = _req->length; 771 772 switch (dev->ep0state) { 773 case EP0_IN_DATA_PHASE: 774 dev->stats.write.ops++; 775 if (write_ep0_fifo(ep, req)) 776 req = NULL; 777 break; 778 779 case EP0_OUT_DATA_PHASE: 780 dev->stats.read.ops++; 781 /* messy ... */ 782 if (dev->req_config) { 783 debug("ep0 config ack%s\n", 784 dev->has_cfr ? "" : " raced"); 785 if (dev->has_cfr) 786 writel(UDCCFR_AREN|UDCCFR_ACM 787 |UDCCFR_MB1, 788 &ep->dev->regs->udccfr); 789 done(ep, req, 0); 790 dev->ep0state = EP0_END_XFER; 791 local_irq_restore(flags); 792 return 0; 793 } 794 if (dev->req_pending) 795 ep0start(dev, UDCCS0_IPR, "OUT"); 796 if (length == 0 || 797 ((readl( 798 &ep->dev->regs->udccs[0]) 799 & UDCCS0_RNE) != 0 800 && read_ep0_fifo(ep, req))) { 801 ep0_idle(dev); 802 done(ep, req, 0); 803 req = NULL; 804 } 805 break; 806 807 default: 808 printf("ep0 i/o, odd state %d\n", 809 dev->ep0state); 810 local_irq_restore(flags); 811 return -EL2HLT; 812 } 813 /* can the FIFO can satisfy the request immediately? */ 814 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { 815 if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0 816 && write_fifo(ep, req)) 817 req = NULL; 818 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0 819 && read_fifo(ep, req)) { 820 req = NULL; 821 } 822 823 if (likely(req && ep->desc)) 824 pio_irq_enable(ep->bEndpointAddress); 825 } 826 827 /* pio or dma irq handler advances the queue. */ 828 if (likely(req != NULL)) 829 list_add_tail(&req->queue, &ep->queue); 830 local_irq_restore(flags); 831 832 return 0; 833 } 834 835 836 /* 837 * nuke - dequeue ALL requests 838 */ 839 static void nuke(struct pxa25x_ep *ep, int status) 840 { 841 struct pxa25x_request *req; 842 843 /* called with irqs blocked */ 844 while (!list_empty(&ep->queue)) { 845 req = list_entry(ep->queue.next, 846 struct pxa25x_request, 847 queue); 848 done(ep, req, status); 849 } 850 if (ep->desc) 851 pio_irq_disable(ep->bEndpointAddress); 852 } 853 854 855 /* dequeue JUST ONE request */ 856 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 857 { 858 struct pxa25x_ep *ep; 859 struct pxa25x_request *req; 860 unsigned long flags; 861 862 ep = container_of(_ep, struct pxa25x_ep, ep); 863 if (!_ep || ep->ep.name == ep0name) 864 return -EINVAL; 865 866 local_irq_save(flags); 867 868 /* make sure it's actually queued on this endpoint */ 869 list_for_each_entry(req, &ep->queue, queue) { 870 if (&req->req == _req) 871 break; 872 } 873 if (&req->req != _req) { 874 local_irq_restore(flags); 875 return -EINVAL; 876 } 877 878 done(ep, req, -ECONNRESET); 879 880 local_irq_restore(flags); 881 return 0; 882 } 883 884 /*-------------------------------------------------------------------------*/ 885 886 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) 887 { 888 struct pxa25x_ep *ep; 889 unsigned long flags; 890 891 ep = container_of(_ep, struct pxa25x_ep, ep); 892 if (unlikely(!_ep 893 || (!ep->desc && ep->ep.name != ep0name)) 894 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 895 printf("%s, bad ep\n", __func__); 896 return -EINVAL; 897 } 898 if (value == 0) { 899 /* 900 * this path (reset toggle+halt) is needed to implement 901 * SET_INTERFACE on normal hardware. but it can't be 902 * done from software on the PXA UDC, and the hardware 903 * forgets to do it as part of SET_INTERFACE automagic. 904 */ 905 printf("only host can clear %s halt\n", _ep->name); 906 return -EROFS; 907 } 908 909 local_irq_save(flags); 910 911 if ((ep->bEndpointAddress & USB_DIR_IN) != 0 912 && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0 913 || !list_empty(&ep->queue))) { 914 local_irq_restore(flags); 915 return -EAGAIN; 916 } 917 918 /* FST bit is the same for control, bulk in, bulk out, interrupt in */ 919 writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs); 920 921 /* ep0 needs special care */ 922 if (!ep->desc) { 923 start_watchdog(ep->dev); 924 ep->dev->req_pending = 0; 925 ep->dev->ep0state = EP0_STALL; 926 927 /* and bulk/intr endpoints like dropping stalls too */ 928 } else { 929 unsigned i; 930 for (i = 0; i < 1000; i += 20) { 931 if (readl(ep->reg_udccs) & UDCCS_BI_SST) 932 break; 933 udelay(20); 934 } 935 } 936 local_irq_restore(flags); 937 938 debug("%s halt\n", _ep->name); 939 return 0; 940 } 941 942 static int pxa25x_ep_fifo_status(struct usb_ep *_ep) 943 { 944 struct pxa25x_ep *ep; 945 946 ep = container_of(_ep, struct pxa25x_ep, ep); 947 if (!_ep) { 948 printf("%s, bad ep\n", __func__); 949 return -ENODEV; 950 } 951 /* pxa can't report unclaimed bytes from IN fifos */ 952 if ((ep->bEndpointAddress & USB_DIR_IN) != 0) 953 return -EOPNOTSUPP; 954 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN 955 || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0) 956 return 0; 957 else 958 return (readl(ep->reg_ubcr) & 0xfff) + 1; 959 } 960 961 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) 962 { 963 struct pxa25x_ep *ep; 964 965 ep = container_of(_ep, struct pxa25x_ep, ep); 966 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { 967 printf("%s, bad ep\n", __func__); 968 return; 969 } 970 971 /* toggle and halt bits stay unchanged */ 972 973 /* for OUT, just read and discard the FIFO contents. */ 974 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { 975 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0) 976 (void)readb(ep->reg_uddr); 977 return; 978 } 979 980 /* most IN status is the same, but ISO can't stall */ 981 writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR 982 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 983 ? 0 : UDCCS_BI_SST), ep->reg_udccs); 984 } 985 986 987 static struct usb_ep_ops pxa25x_ep_ops = { 988 .enable = pxa25x_ep_enable, 989 .disable = pxa25x_ep_disable, 990 991 .alloc_request = pxa25x_ep_alloc_request, 992 .free_request = pxa25x_ep_free_request, 993 994 .queue = pxa25x_ep_queue, 995 .dequeue = pxa25x_ep_dequeue, 996 997 .set_halt = pxa25x_ep_set_halt, 998 .fifo_status = pxa25x_ep_fifo_status, 999 .fifo_flush = pxa25x_ep_fifo_flush, 1000 }; 1001 1002 1003 /* --------------------------------------------------------------------------- 1004 * device-scoped parts of the api to the usb controller hardware 1005 * --------------------------------------------------------------------------- 1006 */ 1007 1008 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) 1009 { 1010 return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) | 1011 (readl(&the_controller->regs->ufnrl) & 0xff); 1012 } 1013 1014 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) 1015 { 1016 /* host may not have enabled remote wakeup */ 1017 if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0) 1018 return -EHOSTUNREACH; 1019 udc_set_mask_UDCCR(UDCCR_RSM); 1020 return 0; 1021 } 1022 1023 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); 1024 static void udc_enable(struct pxa25x_udc *); 1025 static void udc_disable(struct pxa25x_udc *); 1026 1027 /* 1028 * We disable the UDC -- and its 48 MHz clock -- whenever it's not 1029 * in active use. 1030 */ 1031 static int pullup(struct pxa25x_udc *udc) 1032 { 1033 if (udc->pullup) 1034 pullup_on(); 1035 else 1036 pullup_off(); 1037 1038 1039 int is_active = udc->pullup; 1040 if (is_active) { 1041 if (!udc->active) { 1042 udc->active = 1; 1043 udc_enable(udc); 1044 } 1045 } else { 1046 if (udc->active) { 1047 if (udc->gadget.speed != USB_SPEED_UNKNOWN) 1048 stop_activity(udc, udc->driver); 1049 udc_disable(udc); 1050 udc->active = 0; 1051 } 1052 1053 } 1054 return 0; 1055 } 1056 1057 /* VBUS reporting logically comes from a transceiver */ 1058 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) 1059 { 1060 struct pxa25x_udc *udc; 1061 1062 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1063 printf("vbus %s\n", is_active ? "supplied" : "inactive"); 1064 pullup(udc); 1065 return 0; 1066 } 1067 1068 /* drivers may have software control over D+ pullup */ 1069 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) 1070 { 1071 struct pxa25x_udc *udc; 1072 1073 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1074 1075 /* not all boards support pullup control */ 1076 if (!udc->mach->udc_command) 1077 return -EOPNOTSUPP; 1078 1079 udc->pullup = (is_active != 0); 1080 pullup(udc); 1081 return 0; 1082 } 1083 1084 /* 1085 * boards may consume current from VBUS, up to 100-500mA based on config. 1086 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs 1087 * violate USB specs. 1088 */ 1089 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) 1090 { 1091 return -EOPNOTSUPP; 1092 } 1093 1094 static const struct usb_gadget_ops pxa25x_udc_ops = { 1095 .get_frame = pxa25x_udc_get_frame, 1096 .wakeup = pxa25x_udc_wakeup, 1097 .vbus_session = pxa25x_udc_vbus_session, 1098 .pullup = pxa25x_udc_pullup, 1099 .vbus_draw = pxa25x_udc_vbus_draw, 1100 }; 1101 1102 /*-------------------------------------------------------------------------*/ 1103 1104 /* 1105 * udc_disable - disable USB device controller 1106 */ 1107 static void udc_disable(struct pxa25x_udc *dev) 1108 { 1109 /* block all irqs */ 1110 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); 1111 writel(0xff, &dev->regs->uicr0); 1112 writel(0xff, &dev->regs->uicr1); 1113 writel(UFNRH_SIM, &dev->regs->ufnrh); 1114 1115 /* if hardware supports it, disconnect from usb */ 1116 pullup_off(); 1117 1118 udc_clear_mask_UDCCR(UDCCR_UDE); 1119 1120 ep0_idle(dev); 1121 dev->gadget.speed = USB_SPEED_UNKNOWN; 1122 } 1123 1124 /* 1125 * udc_reinit - initialize software state 1126 */ 1127 static void udc_reinit(struct pxa25x_udc *dev) 1128 { 1129 u32 i; 1130 1131 /* device/ep0 records init */ 1132 INIT_LIST_HEAD(&dev->gadget.ep_list); 1133 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 1134 dev->ep0state = EP0_IDLE; 1135 1136 /* basic endpoint records init */ 1137 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1138 struct pxa25x_ep *ep = &dev->ep[i]; 1139 1140 if (i != 0) 1141 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); 1142 1143 ep->desc = NULL; 1144 ep->stopped = 0; 1145 INIT_LIST_HEAD(&ep->queue); 1146 ep->pio_irqs = 0; 1147 } 1148 1149 /* the rest was statically initialized, and is read-only */ 1150 } 1151 1152 /* 1153 * until it's enabled, this UDC should be completely invisible 1154 * to any USB host. 1155 */ 1156 static void udc_enable(struct pxa25x_udc *dev) 1157 { 1158 debug("udc: enabling udc\n"); 1159 1160 udc_clear_mask_UDCCR(UDCCR_UDE); 1161 1162 /* 1163 * Try to clear these bits before we enable the udc. 1164 * Do not touch reset ack bit, we would take care of it in 1165 * interrupt handle routine 1166 */ 1167 udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR); 1168 1169 ep0_idle(dev); 1170 dev->gadget.speed = USB_SPEED_UNKNOWN; 1171 dev->stats.irqs = 0; 1172 1173 /* 1174 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: 1175 * - enable UDC 1176 * - if RESET is already in progress, ack interrupt 1177 * - unmask reset interrupt 1178 */ 1179 udc_set_mask_UDCCR(UDCCR_UDE); 1180 if (!(readl(&dev->regs->udccr) & UDCCR_UDA)) 1181 udc_ack_int_UDCCR(UDCCR_RSTIR); 1182 1183 if (dev->has_cfr /* UDC_RES2 is defined */) { 1184 /* 1185 * pxa255 (a0+) can avoid a set_config race that could 1186 * prevent gadget drivers from configuring correctly 1187 */ 1188 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr); 1189 } 1190 1191 /* enable suspend/resume and reset irqs */ 1192 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM); 1193 1194 /* enable ep0 irqs */ 1195 clrbits_le32(&dev->regs->uicr0, UICR0_IM0); 1196 1197 /* if hardware supports it, pullup D+ and wait for reset */ 1198 pullup_on(); 1199 } 1200 1201 static inline void clear_ep_state(struct pxa25x_udc *dev) 1202 { 1203 unsigned i; 1204 1205 /* 1206 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint 1207 * fifos, and pending transactions mustn't be continued in any case. 1208 */ 1209 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) 1210 nuke(&dev->ep[i], -ECONNABORTED); 1211 } 1212 1213 static void handle_ep0(struct pxa25x_udc *dev) 1214 { 1215 u32 udccs0 = readl(&dev->regs->udccs[0]); 1216 struct pxa25x_ep *ep = &dev->ep[0]; 1217 struct pxa25x_request *req; 1218 union { 1219 struct usb_ctrlrequest r; 1220 u8 raw[8]; 1221 u32 word[2]; 1222 } u; 1223 1224 if (list_empty(&ep->queue)) 1225 req = NULL; 1226 else 1227 req = list_entry(ep->queue.next, struct pxa25x_request, queue); 1228 1229 /* clear stall status */ 1230 if (udccs0 & UDCCS0_SST) { 1231 nuke(ep, -EPIPE); 1232 writel(UDCCS0_SST, &dev->regs->udccs[0]); 1233 stop_watchdog(dev); 1234 ep0_idle(dev); 1235 } 1236 1237 /* previous request unfinished? non-error iff back-to-back ... */ 1238 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { 1239 nuke(ep, 0); 1240 stop_watchdog(dev); 1241 ep0_idle(dev); 1242 } 1243 1244 switch (dev->ep0state) { 1245 case EP0_IDLE: 1246 /* late-breaking status? */ 1247 udccs0 = readl(&dev->regs->udccs[0]); 1248 1249 /* start control request? */ 1250 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) 1251 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { 1252 int i; 1253 1254 nuke(ep, -EPROTO); 1255 1256 /* read SETUP packet */ 1257 for (i = 0; i < 8; i++) { 1258 if (unlikely(!(readl(&dev->regs->udccs[0]) & 1259 UDCCS0_RNE))) { 1260 bad_setup: 1261 debug("SETUP %d!\n", i); 1262 goto stall; 1263 } 1264 u.raw[i] = (u8)readb(&dev->regs->uddr0); 1265 } 1266 if (unlikely((readl(&dev->regs->udccs[0]) & 1267 UDCCS0_RNE) != 0)) 1268 goto bad_setup; 1269 1270 got_setup: 1271 debug("SETUP %02x.%02x v%04x i%04x l%04x\n", 1272 u.r.bRequestType, u.r.bRequest, 1273 le16_to_cpu(u.r.wValue), 1274 le16_to_cpu(u.r.wIndex), 1275 le16_to_cpu(u.r.wLength)); 1276 1277 /* cope with automagic for some standard requests. */ 1278 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) 1279 == USB_TYPE_STANDARD; 1280 dev->req_config = 0; 1281 dev->req_pending = 1; 1282 switch (u.r.bRequest) { 1283 /* hardware restricts gadget drivers here! */ 1284 case USB_REQ_SET_CONFIGURATION: 1285 debug("GOT SET_CONFIGURATION\n"); 1286 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1287 /* 1288 * reflect hardware's automagic 1289 * up to the gadget driver. 1290 */ 1291 config_change: 1292 dev->req_config = 1; 1293 clear_ep_state(dev); 1294 /* 1295 * if !has_cfr, there's no synch 1296 * else use AREN (later) not SA|OPR 1297 * USIR0_IR0 acts edge sensitive 1298 */ 1299 } 1300 break; 1301 /* ... and here, even more ... */ 1302 case USB_REQ_SET_INTERFACE: 1303 if (u.r.bRequestType == USB_RECIP_INTERFACE) { 1304 /* 1305 * udc hardware is broken by design: 1306 * - altsetting may only be zero; 1307 * - hw resets all interfaces' eps; 1308 * - ep reset doesn't include halt(?). 1309 */ 1310 printf("broken set_interface (%d/%d)\n", 1311 le16_to_cpu(u.r.wIndex), 1312 le16_to_cpu(u.r.wValue)); 1313 goto config_change; 1314 } 1315 break; 1316 /* hardware was supposed to hide this */ 1317 case USB_REQ_SET_ADDRESS: 1318 debug("GOT SET ADDRESS\n"); 1319 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1320 ep0start(dev, 0, "address"); 1321 return; 1322 } 1323 break; 1324 } 1325 1326 if (u.r.bRequestType & USB_DIR_IN) 1327 dev->ep0state = EP0_IN_DATA_PHASE; 1328 else 1329 dev->ep0state = EP0_OUT_DATA_PHASE; 1330 1331 i = dev->driver->setup(&dev->gadget, &u.r); 1332 if (i < 0) { 1333 /* hardware automagic preventing STALL... */ 1334 if (dev->req_config) { 1335 /* 1336 * hardware sometimes neglects to tell 1337 * tell us about config change events, 1338 * so later ones may fail... 1339 */ 1340 printf("config change %02x fail %d?\n", 1341 u.r.bRequest, i); 1342 return; 1343 /* 1344 * TODO experiment: if has_cfr, 1345 * hardware didn't ACK; maybe we 1346 * could actually STALL! 1347 */ 1348 } 1349 if (0) { 1350 stall: 1351 /* uninitialized when goto stall */ 1352 i = 0; 1353 } 1354 debug("protocol STALL, " 1355 "%02x err %d\n", 1356 readl(&dev->regs->udccs[0]), i); 1357 1358 /* 1359 * the watchdog timer helps deal with cases 1360 * where udc seems to clear FST wrongly, and 1361 * then NAKs instead of STALLing. 1362 */ 1363 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall"); 1364 start_watchdog(dev); 1365 dev->ep0state = EP0_STALL; 1366 1367 /* deferred i/o == no response yet */ 1368 } else if (dev->req_pending) { 1369 if (likely(dev->ep0state == EP0_IN_DATA_PHASE 1370 || dev->req_std || u.r.wLength)) 1371 ep0start(dev, 0, "defer"); 1372 else 1373 ep0start(dev, UDCCS0_IPR, "defer/IPR"); 1374 } 1375 1376 /* expect at least one data or status stage irq */ 1377 return; 1378 1379 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) 1380 == (UDCCS0_OPR|UDCCS0_SA))) { 1381 unsigned i; 1382 1383 /* 1384 * pxa210/250 erratum 131 for B0/B1 says RNE lies. 1385 * still observed on a pxa255 a0. 1386 */ 1387 debug("e131\n"); 1388 nuke(ep, -EPROTO); 1389 1390 /* read SETUP data, but don't trust it too much */ 1391 for (i = 0; i < 8; i++) 1392 u.raw[i] = (u8)readb(&dev->regs->uddr0); 1393 if ((u.r.bRequestType & USB_RECIP_MASK) 1394 > USB_RECIP_OTHER) 1395 goto stall; 1396 if (u.word[0] == 0 && u.word[1] == 0) 1397 goto stall; 1398 goto got_setup; 1399 } else { 1400 /* 1401 * some random early IRQ: 1402 * - we acked FST 1403 * - IPR cleared 1404 * - OPR got set, without SA (likely status stage) 1405 */ 1406 debug("random IRQ %X %X\n", udccs0, 1407 readl(&dev->regs->udccs[0])); 1408 writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR), 1409 &dev->regs->udccs[0]); 1410 } 1411 break; 1412 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ 1413 if (udccs0 & UDCCS0_OPR) { 1414 debug("ep0in premature status\n"); 1415 if (req) 1416 done(ep, req, 0); 1417 ep0_idle(dev); 1418 } else /* irq was IPR clearing */ { 1419 if (req) { 1420 debug("next ep0 in packet\n"); 1421 /* this IN packet might finish the request */ 1422 (void) write_ep0_fifo(ep, req); 1423 } /* else IN token before response was written */ 1424 } 1425 break; 1426 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ 1427 if (udccs0 & UDCCS0_OPR) { 1428 if (req) { 1429 /* this OUT packet might finish the request */ 1430 if (read_ep0_fifo(ep, req)) 1431 done(ep, req, 0); 1432 /* else more OUT packets expected */ 1433 } /* else OUT token before read was issued */ 1434 } else /* irq was IPR clearing */ { 1435 debug("ep0out premature status\n"); 1436 if (req) 1437 done(ep, req, 0); 1438 ep0_idle(dev); 1439 } 1440 break; 1441 case EP0_END_XFER: 1442 if (req) 1443 done(ep, req, 0); 1444 /* 1445 * ack control-IN status (maybe in-zlp was skipped) 1446 * also appears after some config change events. 1447 */ 1448 if (udccs0 & UDCCS0_OPR) 1449 writel(UDCCS0_OPR, &dev->regs->udccs[0]); 1450 ep0_idle(dev); 1451 break; 1452 case EP0_STALL: 1453 writel(UDCCS0_FST, &dev->regs->udccs[0]); 1454 break; 1455 } 1456 1457 writel(USIR0_IR0, &dev->regs->usir0); 1458 } 1459 1460 static void handle_ep(struct pxa25x_ep *ep) 1461 { 1462 struct pxa25x_request *req; 1463 int is_in = ep->bEndpointAddress & USB_DIR_IN; 1464 int completed; 1465 u32 udccs, tmp; 1466 1467 do { 1468 completed = 0; 1469 if (likely(!list_empty(&ep->queue))) 1470 req = list_entry(ep->queue.next, 1471 struct pxa25x_request, queue); 1472 else 1473 req = NULL; 1474 1475 /* TODO check FST handling */ 1476 1477 udccs = readl(ep->reg_udccs); 1478 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ 1479 tmp = UDCCS_BI_TUR; 1480 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1481 tmp |= UDCCS_BI_SST; 1482 tmp &= udccs; 1483 if (likely(tmp)) 1484 writel(tmp, ep->reg_udccs); 1485 if (req && likely((udccs & UDCCS_BI_TFS) != 0)) 1486 completed = write_fifo(ep, req); 1487 1488 } else { /* irq from RPC (or for ISO, ROF) */ 1489 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1490 tmp = UDCCS_BO_SST | UDCCS_BO_DME; 1491 else 1492 tmp = UDCCS_IO_ROF | UDCCS_IO_DME; 1493 tmp &= udccs; 1494 if (likely(tmp)) 1495 writel(tmp, ep->reg_udccs); 1496 1497 /* fifos can hold packets, ready for reading... */ 1498 if (likely(req)) 1499 completed = read_fifo(ep, req); 1500 else 1501 pio_irq_disable(ep->bEndpointAddress); 1502 } 1503 ep->pio_irqs++; 1504 } while (completed); 1505 } 1506 1507 /* 1508 * pxa25x_udc_irq - interrupt handler 1509 * 1510 * avoid delays in ep0 processing. the control handshaking isn't always 1511 * under software control (pxa250c0 and the pxa255 are better), and delays 1512 * could cause usb protocol errors. 1513 */ 1514 static struct pxa25x_udc memory; 1515 static int 1516 pxa25x_udc_irq(void) 1517 { 1518 struct pxa25x_udc *dev = &memory; 1519 int handled; 1520 1521 test_watchdog(dev); 1522 1523 dev->stats.irqs++; 1524 do { 1525 u32 udccr = readl(&dev->regs->udccr); 1526 1527 handled = 0; 1528 1529 /* SUSpend Interrupt Request */ 1530 if (unlikely(udccr & UDCCR_SUSIR)) { 1531 udc_ack_int_UDCCR(UDCCR_SUSIR); 1532 handled = 1; 1533 debug("USB suspend\n"); 1534 1535 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1536 && dev->driver 1537 && dev->driver->suspend) 1538 dev->driver->suspend(&dev->gadget); 1539 ep0_idle(dev); 1540 } 1541 1542 /* RESume Interrupt Request */ 1543 if (unlikely(udccr & UDCCR_RESIR)) { 1544 udc_ack_int_UDCCR(UDCCR_RESIR); 1545 handled = 1; 1546 debug("USB resume\n"); 1547 1548 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1549 && dev->driver 1550 && dev->driver->resume) 1551 dev->driver->resume(&dev->gadget); 1552 } 1553 1554 /* ReSeT Interrupt Request - USB reset */ 1555 if (unlikely(udccr & UDCCR_RSTIR)) { 1556 udc_ack_int_UDCCR(UDCCR_RSTIR); 1557 handled = 1; 1558 1559 if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) { 1560 debug("USB reset start\n"); 1561 1562 /* 1563 * reset driver and endpoints, 1564 * in case that's not yet done 1565 */ 1566 stop_activity(dev, dev->driver); 1567 1568 } else { 1569 debug("USB reset end\n"); 1570 dev->gadget.speed = USB_SPEED_FULL; 1571 memset(&dev->stats, 0, sizeof dev->stats); 1572 /* driver and endpoints are still reset */ 1573 } 1574 1575 } else { 1576 u32 uicr0 = readl(&dev->regs->uicr0); 1577 u32 uicr1 = readl(&dev->regs->uicr1); 1578 u32 usir0 = readl(&dev->regs->usir0); 1579 u32 usir1 = readl(&dev->regs->usir1); 1580 1581 usir0 = usir0 & ~uicr0; 1582 usir1 = usir1 & ~uicr1; 1583 int i; 1584 1585 if (unlikely(!usir0 && !usir1)) 1586 continue; 1587 1588 debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0); 1589 1590 /* control traffic */ 1591 if (usir0 & USIR0_IR0) { 1592 dev->ep[0].pio_irqs++; 1593 handle_ep0(dev); 1594 handled = 1; 1595 } 1596 1597 /* endpoint data transfers */ 1598 for (i = 0; i < 8; i++) { 1599 u32 tmp = 1 << i; 1600 1601 if (i && (usir0 & tmp)) { 1602 handle_ep(&dev->ep[i]); 1603 setbits_le32(&dev->regs->usir0, tmp); 1604 handled = 1; 1605 } 1606 #ifndef CONFIG_USB_PXA25X_SMALL 1607 if (usir1 & tmp) { 1608 handle_ep(&dev->ep[i+8]); 1609 setbits_le32(&dev->regs->usir1, tmp); 1610 handled = 1; 1611 } 1612 #endif 1613 } 1614 } 1615 1616 /* we could also ask for 1 msec SOF (SIR) interrupts */ 1617 1618 } while (handled); 1619 return IRQ_HANDLED; 1620 } 1621 1622 /*-------------------------------------------------------------------------*/ 1623 1624 /* 1625 * this uses load-time allocation and initialization (instead of 1626 * doing it at run-time) to save code, eliminate fault paths, and 1627 * be more obviously correct. 1628 */ 1629 static struct pxa25x_udc memory = { 1630 .regs = UDC_REGS, 1631 1632 .gadget = { 1633 .ops = &pxa25x_udc_ops, 1634 .ep0 = &memory.ep[0].ep, 1635 .name = driver_name, 1636 }, 1637 1638 /* control endpoint */ 1639 .ep[0] = { 1640 .ep = { 1641 .name = ep0name, 1642 .ops = &pxa25x_ep_ops, 1643 .maxpacket = EP0_FIFO_SIZE, 1644 }, 1645 .dev = &memory, 1646 .reg_udccs = &UDC_REGS->udccs[0], 1647 .reg_uddr = &UDC_REGS->uddr0, 1648 }, 1649 1650 /* first group of endpoints */ 1651 .ep[1] = { 1652 .ep = { 1653 .name = "ep1in-bulk", 1654 .ops = &pxa25x_ep_ops, 1655 .maxpacket = BULK_FIFO_SIZE, 1656 }, 1657 .dev = &memory, 1658 .fifo_size = BULK_FIFO_SIZE, 1659 .bEndpointAddress = USB_DIR_IN | 1, 1660 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1661 .reg_udccs = &UDC_REGS->udccs[1], 1662 .reg_uddr = &UDC_REGS->uddr1, 1663 }, 1664 .ep[2] = { 1665 .ep = { 1666 .name = "ep2out-bulk", 1667 .ops = &pxa25x_ep_ops, 1668 .maxpacket = BULK_FIFO_SIZE, 1669 }, 1670 .dev = &memory, 1671 .fifo_size = BULK_FIFO_SIZE, 1672 .bEndpointAddress = 2, 1673 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1674 .reg_udccs = &UDC_REGS->udccs[2], 1675 .reg_ubcr = &UDC_REGS->ubcr2, 1676 .reg_uddr = &UDC_REGS->uddr2, 1677 }, 1678 #ifndef CONFIG_USB_PXA25X_SMALL 1679 .ep[3] = { 1680 .ep = { 1681 .name = "ep3in-iso", 1682 .ops = &pxa25x_ep_ops, 1683 .maxpacket = ISO_FIFO_SIZE, 1684 }, 1685 .dev = &memory, 1686 .fifo_size = ISO_FIFO_SIZE, 1687 .bEndpointAddress = USB_DIR_IN | 3, 1688 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1689 .reg_udccs = &UDC_REGS->udccs[3], 1690 .reg_uddr = &UDC_REGS->uddr3, 1691 }, 1692 .ep[4] = { 1693 .ep = { 1694 .name = "ep4out-iso", 1695 .ops = &pxa25x_ep_ops, 1696 .maxpacket = ISO_FIFO_SIZE, 1697 }, 1698 .dev = &memory, 1699 .fifo_size = ISO_FIFO_SIZE, 1700 .bEndpointAddress = 4, 1701 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1702 .reg_udccs = &UDC_REGS->udccs[4], 1703 .reg_ubcr = &UDC_REGS->ubcr4, 1704 .reg_uddr = &UDC_REGS->uddr4, 1705 }, 1706 .ep[5] = { 1707 .ep = { 1708 .name = "ep5in-int", 1709 .ops = &pxa25x_ep_ops, 1710 .maxpacket = INT_FIFO_SIZE, 1711 }, 1712 .dev = &memory, 1713 .fifo_size = INT_FIFO_SIZE, 1714 .bEndpointAddress = USB_DIR_IN | 5, 1715 .bmAttributes = USB_ENDPOINT_XFER_INT, 1716 .reg_udccs = &UDC_REGS->udccs[5], 1717 .reg_uddr = &UDC_REGS->uddr5, 1718 }, 1719 1720 /* second group of endpoints */ 1721 .ep[6] = { 1722 .ep = { 1723 .name = "ep6in-bulk", 1724 .ops = &pxa25x_ep_ops, 1725 .maxpacket = BULK_FIFO_SIZE, 1726 }, 1727 .dev = &memory, 1728 .fifo_size = BULK_FIFO_SIZE, 1729 .bEndpointAddress = USB_DIR_IN | 6, 1730 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1731 .reg_udccs = &UDC_REGS->udccs[6], 1732 .reg_uddr = &UDC_REGS->uddr6, 1733 }, 1734 .ep[7] = { 1735 .ep = { 1736 .name = "ep7out-bulk", 1737 .ops = &pxa25x_ep_ops, 1738 .maxpacket = BULK_FIFO_SIZE, 1739 }, 1740 .dev = &memory, 1741 .fifo_size = BULK_FIFO_SIZE, 1742 .bEndpointAddress = 7, 1743 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1744 .reg_udccs = &UDC_REGS->udccs[7], 1745 .reg_ubcr = &UDC_REGS->ubcr7, 1746 .reg_uddr = &UDC_REGS->uddr7, 1747 }, 1748 .ep[8] = { 1749 .ep = { 1750 .name = "ep8in-iso", 1751 .ops = &pxa25x_ep_ops, 1752 .maxpacket = ISO_FIFO_SIZE, 1753 }, 1754 .dev = &memory, 1755 .fifo_size = ISO_FIFO_SIZE, 1756 .bEndpointAddress = USB_DIR_IN | 8, 1757 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1758 .reg_udccs = &UDC_REGS->udccs[8], 1759 .reg_uddr = &UDC_REGS->uddr8, 1760 }, 1761 .ep[9] = { 1762 .ep = { 1763 .name = "ep9out-iso", 1764 .ops = &pxa25x_ep_ops, 1765 .maxpacket = ISO_FIFO_SIZE, 1766 }, 1767 .dev = &memory, 1768 .fifo_size = ISO_FIFO_SIZE, 1769 .bEndpointAddress = 9, 1770 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1771 .reg_udccs = &UDC_REGS->udccs[9], 1772 .reg_ubcr = &UDC_REGS->ubcr9, 1773 .reg_uddr = &UDC_REGS->uddr9, 1774 }, 1775 .ep[10] = { 1776 .ep = { 1777 .name = "ep10in-int", 1778 .ops = &pxa25x_ep_ops, 1779 .maxpacket = INT_FIFO_SIZE, 1780 }, 1781 .dev = &memory, 1782 .fifo_size = INT_FIFO_SIZE, 1783 .bEndpointAddress = USB_DIR_IN | 10, 1784 .bmAttributes = USB_ENDPOINT_XFER_INT, 1785 .reg_udccs = &UDC_REGS->udccs[10], 1786 .reg_uddr = &UDC_REGS->uddr10, 1787 }, 1788 1789 /* third group of endpoints */ 1790 .ep[11] = { 1791 .ep = { 1792 .name = "ep11in-bulk", 1793 .ops = &pxa25x_ep_ops, 1794 .maxpacket = BULK_FIFO_SIZE, 1795 }, 1796 .dev = &memory, 1797 .fifo_size = BULK_FIFO_SIZE, 1798 .bEndpointAddress = USB_DIR_IN | 11, 1799 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1800 .reg_udccs = &UDC_REGS->udccs[11], 1801 .reg_uddr = &UDC_REGS->uddr11, 1802 }, 1803 .ep[12] = { 1804 .ep = { 1805 .name = "ep12out-bulk", 1806 .ops = &pxa25x_ep_ops, 1807 .maxpacket = BULK_FIFO_SIZE, 1808 }, 1809 .dev = &memory, 1810 .fifo_size = BULK_FIFO_SIZE, 1811 .bEndpointAddress = 12, 1812 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1813 .reg_udccs = &UDC_REGS->udccs[12], 1814 .reg_ubcr = &UDC_REGS->ubcr12, 1815 .reg_uddr = &UDC_REGS->uddr12, 1816 }, 1817 .ep[13] = { 1818 .ep = { 1819 .name = "ep13in-iso", 1820 .ops = &pxa25x_ep_ops, 1821 .maxpacket = ISO_FIFO_SIZE, 1822 }, 1823 .dev = &memory, 1824 .fifo_size = ISO_FIFO_SIZE, 1825 .bEndpointAddress = USB_DIR_IN | 13, 1826 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1827 .reg_udccs = &UDC_REGS->udccs[13], 1828 .reg_uddr = &UDC_REGS->uddr13, 1829 }, 1830 .ep[14] = { 1831 .ep = { 1832 .name = "ep14out-iso", 1833 .ops = &pxa25x_ep_ops, 1834 .maxpacket = ISO_FIFO_SIZE, 1835 }, 1836 .dev = &memory, 1837 .fifo_size = ISO_FIFO_SIZE, 1838 .bEndpointAddress = 14, 1839 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1840 .reg_udccs = &UDC_REGS->udccs[14], 1841 .reg_ubcr = &UDC_REGS->ubcr14, 1842 .reg_uddr = &UDC_REGS->uddr14, 1843 }, 1844 .ep[15] = { 1845 .ep = { 1846 .name = "ep15in-int", 1847 .ops = &pxa25x_ep_ops, 1848 .maxpacket = INT_FIFO_SIZE, 1849 }, 1850 .dev = &memory, 1851 .fifo_size = INT_FIFO_SIZE, 1852 .bEndpointAddress = USB_DIR_IN | 15, 1853 .bmAttributes = USB_ENDPOINT_XFER_INT, 1854 .reg_udccs = &UDC_REGS->udccs[15], 1855 .reg_uddr = &UDC_REGS->uddr15, 1856 }, 1857 #endif /* !CONFIG_USB_PXA25X_SMALL */ 1858 }; 1859 1860 static void udc_command(int cmd) 1861 { 1862 switch (cmd) { 1863 case PXA2XX_UDC_CMD_CONNECT: 1864 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), 1865 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); 1866 1867 /* enable pullup */ 1868 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), 1869 GPCR(CONFIG_USB_DEV_PULLUP_GPIO)); 1870 1871 debug("Connected to USB\n"); 1872 break; 1873 1874 case PXA2XX_UDC_CMD_DISCONNECT: 1875 /* disable pullup resistor */ 1876 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), 1877 GPSR(CONFIG_USB_DEV_PULLUP_GPIO)); 1878 1879 /* setup pin as input, line will float */ 1880 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), 1881 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); 1882 1883 debug("Disconnected from USB\n"); 1884 break; 1885 } 1886 } 1887 1888 static struct pxa2xx_udc_mach_info mach_info = { 1889 .udc_command = udc_command, 1890 }; 1891 1892 /* 1893 * when a driver is successfully registered, it will receive 1894 * control requests including set_configuration(), which enables 1895 * non-control requests. then usb traffic follows until a 1896 * disconnect is reported. then a host may connect again, or 1897 * the driver might get unbound. 1898 */ 1899 int usb_gadget_register_driver(struct usb_gadget_driver *driver) 1900 { 1901 struct pxa25x_udc *dev = &memory; 1902 int retval; 1903 uint32_t chiprev; 1904 1905 if (!driver 1906 || driver->speed < USB_SPEED_FULL 1907 || !driver->disconnect 1908 || !driver->setup) 1909 return -EINVAL; 1910 if (!dev) 1911 return -ENODEV; 1912 if (dev->driver) 1913 return -EBUSY; 1914 1915 /* Enable clock for usb controller */ 1916 setbits_le32(CKEN, CKEN11_USB); 1917 1918 /* first hook up the driver ... */ 1919 dev->driver = driver; 1920 dev->pullup = 1; 1921 1922 /* trigger chiprev-specific logic */ 1923 switch ((chiprev = pxa_get_cpu_revision())) { 1924 case PXA255_A0: 1925 dev->has_cfr = 1; 1926 break; 1927 case PXA250_A0: 1928 case PXA250_A1: 1929 /* A0/A1 "not released"; ep 13, 15 unusable */ 1930 /* fall through */ 1931 case PXA250_B2: case PXA210_B2: 1932 case PXA250_B1: case PXA210_B1: 1933 case PXA250_B0: case PXA210_B0: 1934 /* OUT-DMA is broken ... */ 1935 /* fall through */ 1936 case PXA250_C0: case PXA210_C0: 1937 break; 1938 default: 1939 printf("%s: unrecognized processor: %08x\n", 1940 DRIVER_NAME, chiprev); 1941 return -ENODEV; 1942 } 1943 1944 the_controller = dev; 1945 1946 /* prepare watchdog timer */ 1947 dev->watchdog.running = 0; 1948 dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */ 1949 dev->watchdog.function = udc_watchdog; 1950 1951 dev->mach = &mach_info; 1952 1953 udc_disable(dev); 1954 udc_reinit(dev); 1955 1956 dev->gadget.name = "pxa2xx_udc"; 1957 retval = driver->bind(&dev->gadget); 1958 if (retval) { 1959 printf("bind to driver %s --> error %d\n", 1960 DRIVER_NAME, retval); 1961 dev->driver = NULL; 1962 return retval; 1963 } 1964 1965 /* 1966 * ... then enable host detection and ep0; and we're ready 1967 * for set_configuration as well as eventual disconnect. 1968 */ 1969 printf("registered gadget driver '%s'\n", DRIVER_NAME); 1970 1971 pullup(dev); 1972 dump_state(dev); 1973 return 0; 1974 } 1975 1976 static void 1977 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) 1978 { 1979 int i; 1980 1981 /* don't disconnect drivers more than once */ 1982 if (dev->gadget.speed == USB_SPEED_UNKNOWN) 1983 driver = NULL; 1984 dev->gadget.speed = USB_SPEED_UNKNOWN; 1985 1986 /* prevent new request submissions, kill any outstanding requests */ 1987 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1988 struct pxa25x_ep *ep = &dev->ep[i]; 1989 1990 ep->stopped = 1; 1991 nuke(ep, -ESHUTDOWN); 1992 } 1993 stop_watchdog(dev); 1994 1995 /* report disconnect; the driver is already quiesced */ 1996 if (driver) 1997 driver->disconnect(&dev->gadget); 1998 1999 /* re-init driver-visible data structures */ 2000 udc_reinit(dev); 2001 } 2002 2003 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 2004 { 2005 struct pxa25x_udc *dev = the_controller; 2006 2007 if (!dev) 2008 return -ENODEV; 2009 if (!driver || driver != dev->driver || !driver->unbind) 2010 return -EINVAL; 2011 2012 local_irq_disable(); 2013 dev->pullup = 0; 2014 pullup(dev); 2015 stop_activity(dev, driver); 2016 local_irq_enable(); 2017 2018 driver->unbind(&dev->gadget); 2019 dev->driver = NULL; 2020 2021 printf("unregistered gadget driver '%s'\n", DRIVER_NAME); 2022 dump_state(dev); 2023 2024 the_controller = NULL; 2025 2026 clrbits_le32(CKEN, CKEN11_USB); 2027 2028 return 0; 2029 } 2030 2031 extern void udc_disconnect(void) 2032 { 2033 setbits_le32(CKEN, CKEN11_USB); 2034 udc_clear_mask_UDCCR(UDCCR_UDE); 2035 udc_command(PXA2XX_UDC_CMD_DISCONNECT); 2036 clrbits_le32(CKEN, CKEN11_USB); 2037 } 2038 2039 /*-------------------------------------------------------------------------*/ 2040 2041 extern int 2042 usb_gadget_handle_interrupts(int index) 2043 { 2044 return pxa25x_udc_irq(); 2045 } 2046