1 /* 2 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers 3 * 4 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) 5 * Copyright (C) 2003 Robert Schwebel, Pengutronix 6 * Copyright (C) 2003 Benedikt Spranger, Pengutronix 7 * Copyright (C) 2003 David Brownell 8 * Copyright (C) 2003 Joshua Wise 9 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 * 25 * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); 26 */ 27 28 #define CONFIG_USB_PXA25X_SMALL 29 #define DRIVER_NAME "pxa25x_udc_linux" 30 #define ARCH_HAS_PREFETCH 31 32 #include <common.h> 33 #include <errno.h> 34 #include <asm/byteorder.h> 35 #include <asm/system.h> 36 #include <asm/mach-types.h> 37 #include <asm/unaligned.h> 38 #include <linux/compat.h> 39 #include <malloc.h> 40 #include <asm/io.h> 41 #include <asm/arch/pxa.h> 42 43 #include <linux/usb/ch9.h> 44 #include <linux/usb/gadget.h> 45 #include <usb/lin_gadget_compat.h> 46 #include <asm/arch/pxa-regs.h> 47 48 #include "pxa25x_udc.h" 49 50 /* 51 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x 52 * series processors. The UDC for the IXP 4xx series is very similar. 53 * There are fifteen endpoints, in addition to ep0. 54 * 55 * Such controller drivers work with a gadget driver. The gadget driver 56 * returns descriptors, implements configuration and data protocols used 57 * by the host to interact with this device, and allocates endpoints to 58 * the different protocol interfaces. The controller driver virtualizes 59 * usb hardware so that the gadget drivers will be more portable. 60 * 61 * This UDC hardware wants to implement a bit too much USB protocol, so 62 * it constrains the sorts of USB configuration change events that work. 63 * The errata for these chips are misleading; some "fixed" bugs from 64 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. 65 * 66 * Note that the UDC hardware supports DMA (except on IXP) but that's 67 * not used here. IN-DMA (to host) is simple enough, when the data is 68 * suitably aligned (16 bytes) ... the network stack doesn't do that, 69 * other software can. OUT-DMA is buggy in most chip versions, as well 70 * as poorly designed (data toggle not automatic). So this driver won't 71 * bother using DMA. (Mostly-working IN-DMA support was available in 72 * kernels before 2.6.23, but was never enabled or well tested.) 73 */ 74 75 #define DRIVER_VERSION "18-August-2012" 76 #define DRIVER_DESC "PXA 25x USB Device Controller driver" 77 78 static const char driver_name[] = "pxa25x_udc"; 79 static const char ep0name[] = "ep0"; 80 81 /* Watchdog */ 82 static inline void start_watchdog(struct pxa25x_udc *udc) 83 { 84 debug("Started watchdog\n"); 85 udc->watchdog.base = get_timer(0); 86 udc->watchdog.running = 1; 87 } 88 89 static inline void stop_watchdog(struct pxa25x_udc *udc) 90 { 91 udc->watchdog.running = 0; 92 debug("Stopped watchdog\n"); 93 } 94 95 static inline void test_watchdog(struct pxa25x_udc *udc) 96 { 97 if (!udc->watchdog.running) 98 return; 99 100 debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base), 101 udc->watchdog.period); 102 103 if (get_timer(udc->watchdog.base) >= udc->watchdog.period) { 104 stop_watchdog(udc); 105 udc->watchdog.function(udc); 106 } 107 } 108 109 static void udc_watchdog(struct pxa25x_udc *dev) 110 { 111 uint32_t udccs0 = readl(&dev->regs->udccs[0]); 112 113 debug("Fired up udc_watchdog\n"); 114 115 local_irq_disable(); 116 if (dev->ep0state == EP0_STALL 117 && (udccs0 & UDCCS0_FST) == 0 118 && (udccs0 & UDCCS0_SST) == 0) { 119 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]); 120 debug("ep0 re-stall\n"); 121 start_watchdog(dev); 122 } 123 local_irq_enable(); 124 } 125 126 #ifdef DEBUG 127 128 static const char * const state_name[] = { 129 "EP0_IDLE", 130 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", 131 "EP0_END_XFER", "EP0_STALL" 132 }; 133 134 static void 135 dump_udccr(const char *label) 136 { 137 u32 udccr = readl(&UDC_REGS->udccr); 138 debug("%s %02X =%s%s%s%s%s%s%s%s\n", 139 label, udccr, 140 (udccr & UDCCR_REM) ? " rem" : "", 141 (udccr & UDCCR_RSTIR) ? " rstir" : "", 142 (udccr & UDCCR_SRM) ? " srm" : "", 143 (udccr & UDCCR_SUSIR) ? " susir" : "", 144 (udccr & UDCCR_RESIR) ? " resir" : "", 145 (udccr & UDCCR_RSM) ? " rsm" : "", 146 (udccr & UDCCR_UDA) ? " uda" : "", 147 (udccr & UDCCR_UDE) ? " ude" : ""); 148 } 149 150 static void 151 dump_udccs0(const char *label) 152 { 153 u32 udccs0 = readl(&UDC_REGS->udccs[0]); 154 155 debug("%s %s %02X =%s%s%s%s%s%s%s%s\n", 156 label, state_name[the_controller->ep0state], udccs0, 157 (udccs0 & UDCCS0_SA) ? " sa" : "", 158 (udccs0 & UDCCS0_RNE) ? " rne" : "", 159 (udccs0 & UDCCS0_FST) ? " fst" : "", 160 (udccs0 & UDCCS0_SST) ? " sst" : "", 161 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "", 162 (udccs0 & UDCCS0_FTF) ? " ftf" : "", 163 (udccs0 & UDCCS0_IPR) ? " ipr" : "", 164 (udccs0 & UDCCS0_OPR) ? " opr" : ""); 165 } 166 167 static void 168 dump_state(struct pxa25x_udc *dev) 169 { 170 u32 tmp; 171 unsigned i; 172 173 debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", 174 state_name[dev->ep0state], 175 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0), 176 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0), 177 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl)); 178 dump_udccr("udccr"); 179 if (dev->has_cfr) { 180 tmp = readl(&UDC_REGS->udccfr); 181 debug("udccfr %02X =%s%s\n", tmp, 182 (tmp & UDCCFR_AREN) ? " aren" : "", 183 (tmp & UDCCFR_ACM) ? " acm" : ""); 184 } 185 186 if (!dev->driver) { 187 debug("no gadget driver bound\n"); 188 return; 189 } else 190 debug("ep0 driver '%s'\n", "ether"); 191 192 dump_udccs0("udccs0"); 193 debug("ep0 IN %lu/%lu, OUT %lu/%lu\n", 194 dev->stats.write.bytes, dev->stats.write.ops, 195 dev->stats.read.bytes, dev->stats.read.ops); 196 197 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { 198 if (dev->ep[i].desc == NULL) 199 continue; 200 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs); 201 } 202 } 203 204 #else /* DEBUG */ 205 206 static inline void dump_udccr(const char *label) { } 207 static inline void dump_udccs0(const char *label) { } 208 static inline void dump_state(struct pxa25x_udc *dev) { } 209 210 #endif /* DEBUG */ 211 212 /* 213 * --------------------------------------------------------------------------- 214 * endpoint related parts of the api to the usb controller hardware, 215 * used by gadget driver; and the inner talker-to-hardware core. 216 * --------------------------------------------------------------------------- 217 */ 218 219 static void pxa25x_ep_fifo_flush(struct usb_ep *ep); 220 static void nuke(struct pxa25x_ep *, int status); 221 222 /* one GPIO should control a D+ pullup, so host sees this device (or not) */ 223 static void pullup_off(void) 224 { 225 struct pxa2xx_udc_mach_info *mach = the_controller->mach; 226 227 if (mach->udc_command) 228 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); 229 } 230 231 static void pullup_on(void) 232 { 233 struct pxa2xx_udc_mach_info *mach = the_controller->mach; 234 235 if (mach->udc_command) 236 mach->udc_command(PXA2XX_UDC_CMD_CONNECT); 237 } 238 239 static void pio_irq_enable(int bEndpointAddress) 240 { 241 bEndpointAddress &= 0xf; 242 if (bEndpointAddress < 8) { 243 clrbits_le32(&the_controller->regs->uicr0, 244 1 << bEndpointAddress); 245 } else { 246 bEndpointAddress -= 8; 247 clrbits_le32(&the_controller->regs->uicr1, 248 1 << bEndpointAddress); 249 } 250 } 251 252 static void pio_irq_disable(int bEndpointAddress) 253 { 254 bEndpointAddress &= 0xf; 255 if (bEndpointAddress < 8) { 256 setbits_le32(&the_controller->regs->uicr0, 257 1 << bEndpointAddress); 258 } else { 259 bEndpointAddress -= 8; 260 setbits_le32(&the_controller->regs->uicr1, 261 1 << bEndpointAddress); 262 } 263 } 264 265 static inline void udc_set_mask_UDCCR(int mask) 266 { 267 /* 268 * The UDCCR reg contains mask and interrupt status bits, 269 * so using '|=' isn't safe as it may ack an interrupt. 270 */ 271 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 272 273 mask &= mask_bits; 274 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); 275 } 276 277 static inline void udc_clear_mask_UDCCR(int mask) 278 { 279 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 280 281 mask = ~mask & mask_bits; 282 clrbits_le32(&the_controller->regs->udccr, ~mask); 283 } 284 285 static inline void udc_ack_int_UDCCR(int mask) 286 { 287 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; 288 289 mask &= ~mask_bits; 290 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); 291 } 292 293 /* 294 * endpoint enable/disable 295 * 296 * we need to verify the descriptors used to enable endpoints. since pxa25x 297 * endpoint configurations are fixed, and are pretty much always enabled, 298 * there's not a lot to manage here. 299 * 300 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, 301 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except 302 * for a single interface (with only the default altsetting) and for gadget 303 * drivers that don't halt endpoints (not reset by set_interface). that also 304 * means that if you use ISO, you must violate the USB spec rule that all 305 * iso endpoints must be in non-default altsettings. 306 */ 307 static int pxa25x_ep_enable(struct usb_ep *_ep, 308 const struct usb_endpoint_descriptor *desc) 309 { 310 struct pxa25x_ep *ep; 311 struct pxa25x_udc *dev; 312 313 ep = container_of(_ep, struct pxa25x_ep, ep); 314 if (!_ep || !desc || ep->desc || _ep->name == ep0name 315 || desc->bDescriptorType != USB_DT_ENDPOINT 316 || ep->bEndpointAddress != desc->bEndpointAddress 317 || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) { 318 printf("%s, bad ep or descriptor\n", __func__); 319 return -EINVAL; 320 } 321 322 /* xfer types must match, except that interrupt ~= bulk */ 323 if (ep->bmAttributes != desc->bmAttributes 324 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 325 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 326 printf("%s, %s type mismatch\n", __func__, _ep->name); 327 return -EINVAL; 328 } 329 330 /* hardware _could_ do smaller, but driver doesn't */ 331 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 332 && le16_to_cpu(desc->wMaxPacketSize) 333 != BULK_FIFO_SIZE) 334 || !desc->wMaxPacketSize) { 335 printf("%s, bad %s maxpacket\n", __func__, _ep->name); 336 return -ERANGE; 337 } 338 339 dev = ep->dev; 340 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { 341 printf("%s, bogus device state\n", __func__); 342 return -ESHUTDOWN; 343 } 344 345 ep->desc = desc; 346 ep->stopped = 0; 347 ep->pio_irqs = 0; 348 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); 349 350 /* flush fifo (mostly for OUT buffers) */ 351 pxa25x_ep_fifo_flush(_ep); 352 353 /* ... reset halt state too, if we could ... */ 354 355 debug("enabled %s\n", _ep->name); 356 return 0; 357 } 358 359 static int pxa25x_ep_disable(struct usb_ep *_ep) 360 { 361 struct pxa25x_ep *ep; 362 unsigned long flags; 363 364 ep = container_of(_ep, struct pxa25x_ep, ep); 365 if (!_ep || !ep->desc) { 366 printf("%s, %s not enabled\n", __func__, 367 _ep ? ep->ep.name : NULL); 368 return -EINVAL; 369 } 370 local_irq_save(flags); 371 372 nuke(ep, -ESHUTDOWN); 373 374 /* flush fifo (mostly for IN buffers) */ 375 pxa25x_ep_fifo_flush(_ep); 376 377 ep->desc = NULL; 378 ep->stopped = 1; 379 380 local_irq_restore(flags); 381 debug("%s disabled\n", _ep->name); 382 return 0; 383 } 384 385 /*-------------------------------------------------------------------------*/ 386 387 /* 388 * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers 389 * must still pass correctly initialized endpoints, since other controller 390 * drivers may care about how it's currently set up (dma issues etc). 391 */ 392 393 /* 394 * pxa25x_ep_alloc_request - allocate a request data structure 395 */ 396 static struct usb_request * 397 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 398 { 399 struct pxa25x_request *req; 400 401 req = kzalloc(sizeof(*req), gfp_flags); 402 if (!req) 403 return NULL; 404 405 INIT_LIST_HEAD(&req->queue); 406 return &req->req; 407 } 408 409 410 /* 411 * pxa25x_ep_free_request - deallocate a request data structure 412 */ 413 static void 414 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) 415 { 416 struct pxa25x_request *req; 417 418 req = container_of(_req, struct pxa25x_request, req); 419 WARN_ON(!list_empty(&req->queue)); 420 kfree(req); 421 } 422 423 /*-------------------------------------------------------------------------*/ 424 425 /* 426 * done - retire a request; caller blocked irqs 427 */ 428 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) 429 { 430 unsigned stopped = ep->stopped; 431 432 list_del_init(&req->queue); 433 434 if (likely(req->req.status == -EINPROGRESS)) 435 req->req.status = status; 436 else 437 status = req->req.status; 438 439 if (status && status != -ESHUTDOWN) 440 debug("complete %s req %p stat %d len %u/%u\n", 441 ep->ep.name, &req->req, status, 442 req->req.actual, req->req.length); 443 444 /* don't modify queue heads during completion callback */ 445 ep->stopped = 1; 446 req->req.complete(&ep->ep, &req->req); 447 ep->stopped = stopped; 448 } 449 450 451 static inline void ep0_idle(struct pxa25x_udc *dev) 452 { 453 dev->ep0state = EP0_IDLE; 454 } 455 456 static int 457 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max) 458 { 459 u8 *buf; 460 unsigned length, count; 461 462 debug("%s(): uddr %p\n", __func__, uddr); 463 464 buf = req->req.buf + req->req.actual; 465 prefetch(buf); 466 467 /* how big will this packet be? */ 468 length = min(req->req.length - req->req.actual, max); 469 req->req.actual += length; 470 471 count = length; 472 while (likely(count--)) 473 writeb(*buf++, uddr); 474 475 return length; 476 } 477 478 /* 479 * write to an IN endpoint fifo, as many packets as possible. 480 * irqs will use this to write the rest later. 481 * caller guarantees at least one packet buffer is ready (or a zlp). 482 */ 483 static int 484 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 485 { 486 unsigned max; 487 488 max = le16_to_cpu(ep->desc->wMaxPacketSize); 489 do { 490 unsigned count; 491 int is_last, is_short; 492 493 count = write_packet(ep->reg_uddr, req, max); 494 495 /* last packet is usually short (or a zlp) */ 496 if (unlikely(count != max)) 497 is_last = is_short = 1; 498 else { 499 if (likely(req->req.length != req->req.actual) 500 || req->req.zero) 501 is_last = 0; 502 else 503 is_last = 1; 504 /* interrupt/iso maxpacket may not fill the fifo */ 505 is_short = unlikely(max < ep->fifo_size); 506 } 507 508 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n", 509 ep->ep.name, count, 510 is_last ? "/L" : "", is_short ? "/S" : "", 511 req->req.length - req->req.actual, req); 512 513 /* 514 * let loose that packet. maybe try writing another one, 515 * double buffering might work. TSP, TPC, and TFS 516 * bit values are the same for all normal IN endpoints. 517 */ 518 writel(UDCCS_BI_TPC, ep->reg_udccs); 519 if (is_short) 520 writel(UDCCS_BI_TSP, ep->reg_udccs); 521 522 /* requests complete when all IN data is in the FIFO */ 523 if (is_last) { 524 done(ep, req, 0); 525 if (list_empty(&ep->queue)) 526 pio_irq_disable(ep->bEndpointAddress); 527 return 1; 528 } 529 530 /* 531 * TODO experiment: how robust can fifo mode tweaking be? 532 * double buffering is off in the default fifo mode, which 533 * prevents TFS from being set here. 534 */ 535 536 } while (readl(ep->reg_udccs) & UDCCS_BI_TFS); 537 return 0; 538 } 539 540 /* 541 * caller asserts req->pending (ep0 irq status nyet cleared); starts 542 * ep0 data stage. these chips want very simple state transitions. 543 */ 544 static inline 545 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) 546 { 547 writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]); 548 writel(USIR0_IR0, &dev->regs->usir0); 549 dev->req_pending = 0; 550 debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n", 551 __func__, tag, readl(&dev->regs->udccs[0]), flags, 552 readl(&dev->regs->usir1), readl(&dev->regs->usir0)); 553 } 554 555 static int 556 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 557 { 558 unsigned count; 559 int is_short; 560 561 count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE); 562 ep->dev->stats.write.bytes += count; 563 564 /* last packet "must be" short (or a zlp) */ 565 is_short = (count != EP0_FIFO_SIZE); 566 567 debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count, 568 req->req.length - req->req.actual, req); 569 570 if (unlikely(is_short)) { 571 if (ep->dev->req_pending) 572 ep0start(ep->dev, UDCCS0_IPR, "short IN"); 573 else 574 writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]); 575 576 count = req->req.length; 577 done(ep, req, 0); 578 ep0_idle(ep->dev); 579 580 /* 581 * This seems to get rid of lost status irqs in some cases: 582 * host responds quickly, or next request involves config 583 * change automagic, or should have been hidden, or ... 584 * 585 * FIXME get rid of all udelays possible... 586 */ 587 if (count >= EP0_FIFO_SIZE) { 588 count = 100; 589 do { 590 if ((readl(&ep->dev->regs->udccs[0]) & 591 UDCCS0_OPR) != 0) { 592 /* clear OPR, generate ack */ 593 writel(UDCCS0_OPR, 594 &ep->dev->regs->udccs[0]); 595 break; 596 } 597 count--; 598 udelay(1); 599 } while (count); 600 } 601 } else if (ep->dev->req_pending) 602 ep0start(ep->dev, 0, "IN"); 603 604 return is_short; 605 } 606 607 608 /* 609 * read_fifo - unload packet(s) from the fifo we use for usb OUT 610 * transfers and put them into the request. caller should have made 611 * sure there's at least one packet ready. 612 * 613 * returns true if the request completed because of short packet or the 614 * request buffer having filled (and maybe overran till end-of-packet). 615 */ 616 static int 617 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 618 { 619 u32 udccs; 620 u8 *buf; 621 unsigned bufferspace, count, is_short; 622 623 for (;;) { 624 /* 625 * make sure there's a packet in the FIFO. 626 * UDCCS_{BO,IO}_RPC are all the same bit value. 627 * UDCCS_{BO,IO}_RNE are all the same bit value. 628 */ 629 udccs = readl(ep->reg_udccs); 630 if (unlikely((udccs & UDCCS_BO_RPC) == 0)) 631 break; 632 buf = req->req.buf + req->req.actual; 633 prefetchw(buf); 634 bufferspace = req->req.length - req->req.actual; 635 636 /* read all bytes from this packet */ 637 if (likely(udccs & UDCCS_BO_RNE)) { 638 count = 1 + (0x0ff & readl(ep->reg_ubcr)); 639 req->req.actual += min(count, bufferspace); 640 } else /* zlp */ 641 count = 0; 642 is_short = (count < ep->ep.maxpacket); 643 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n", 644 ep->ep.name, udccs, count, 645 is_short ? "/S" : "", 646 req, req->req.actual, req->req.length); 647 while (likely(count-- != 0)) { 648 u8 byte = readb(ep->reg_uddr); 649 650 if (unlikely(bufferspace == 0)) { 651 /* 652 * this happens when the driver's buffer 653 * is smaller than what the host sent. 654 * discard the extra data. 655 */ 656 if (req->req.status != -EOVERFLOW) 657 printf("%s overflow %d\n", 658 ep->ep.name, count); 659 req->req.status = -EOVERFLOW; 660 } else { 661 *buf++ = byte; 662 bufferspace--; 663 } 664 } 665 writel(UDCCS_BO_RPC, ep->reg_udccs); 666 /* RPC/RSP/RNE could now reflect the other packet buffer */ 667 668 /* iso is one request per packet */ 669 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 670 if (udccs & UDCCS_IO_ROF) 671 req->req.status = -EHOSTUNREACH; 672 /* more like "is_done" */ 673 is_short = 1; 674 } 675 676 /* completion */ 677 if (is_short || req->req.actual == req->req.length) { 678 done(ep, req, 0); 679 if (list_empty(&ep->queue)) 680 pio_irq_disable(ep->bEndpointAddress); 681 return 1; 682 } 683 684 /* finished that packet. the next one may be waiting... */ 685 } 686 return 0; 687 } 688 689 /* 690 * special ep0 version of the above. no UBCR0 or double buffering; status 691 * handshaking is magic. most device protocols don't need control-OUT. 692 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other 693 * protocols do use them. 694 */ 695 static int 696 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) 697 { 698 u8 *buf, byte; 699 unsigned bufferspace; 700 701 buf = req->req.buf + req->req.actual; 702 bufferspace = req->req.length - req->req.actual; 703 704 while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) { 705 byte = (u8)readb(&ep->dev->regs->uddr0); 706 707 if (unlikely(bufferspace == 0)) { 708 /* 709 * this happens when the driver's buffer 710 * is smaller than what the host sent. 711 * discard the extra data. 712 */ 713 if (req->req.status != -EOVERFLOW) 714 printf("%s overflow\n", ep->ep.name); 715 req->req.status = -EOVERFLOW; 716 } else { 717 *buf++ = byte; 718 req->req.actual++; 719 bufferspace--; 720 } 721 } 722 723 writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]); 724 725 /* completion */ 726 if (req->req.actual >= req->req.length) 727 return 1; 728 729 /* finished that packet. the next one may be waiting... */ 730 return 0; 731 } 732 733 /*-------------------------------------------------------------------------*/ 734 735 static int 736 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 737 { 738 struct pxa25x_request *req; 739 struct pxa25x_ep *ep; 740 struct pxa25x_udc *dev; 741 unsigned long flags; 742 743 req = container_of(_req, struct pxa25x_request, req); 744 if (unlikely(!_req || !_req->complete || !_req->buf 745 || !list_empty(&req->queue))) { 746 printf("%s, bad params\n", __func__); 747 return -EINVAL; 748 } 749 750 ep = container_of(_ep, struct pxa25x_ep, ep); 751 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { 752 printf("%s, bad ep\n", __func__); 753 return -EINVAL; 754 } 755 756 dev = ep->dev; 757 if (unlikely(!dev->driver 758 || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 759 printf("%s, bogus device state\n", __func__); 760 return -ESHUTDOWN; 761 } 762 763 /* 764 * iso is always one packet per request, that's the only way 765 * we can report per-packet status. that also helps with dma. 766 */ 767 if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 768 && req->req.length > 769 le16_to_cpu(ep->desc->wMaxPacketSize))) 770 return -EMSGSIZE; 771 772 debug_cond(NOISY, "%s queue req %p, len %d buf %p\n", 773 _ep->name, _req, _req->length, _req->buf); 774 775 local_irq_save(flags); 776 777 _req->status = -EINPROGRESS; 778 _req->actual = 0; 779 780 /* kickstart this i/o queue? */ 781 if (list_empty(&ep->queue) && !ep->stopped) { 782 if (ep->desc == NULL/* ep0 */) { 783 unsigned length = _req->length; 784 785 switch (dev->ep0state) { 786 case EP0_IN_DATA_PHASE: 787 dev->stats.write.ops++; 788 if (write_ep0_fifo(ep, req)) 789 req = NULL; 790 break; 791 792 case EP0_OUT_DATA_PHASE: 793 dev->stats.read.ops++; 794 /* messy ... */ 795 if (dev->req_config) { 796 debug("ep0 config ack%s\n", 797 dev->has_cfr ? "" : " raced"); 798 if (dev->has_cfr) 799 writel(UDCCFR_AREN|UDCCFR_ACM 800 |UDCCFR_MB1, 801 &ep->dev->regs->udccfr); 802 done(ep, req, 0); 803 dev->ep0state = EP0_END_XFER; 804 local_irq_restore(flags); 805 return 0; 806 } 807 if (dev->req_pending) 808 ep0start(dev, UDCCS0_IPR, "OUT"); 809 if (length == 0 || 810 ((readl( 811 &ep->dev->regs->udccs[0]) 812 & UDCCS0_RNE) != 0 813 && read_ep0_fifo(ep, req))) { 814 ep0_idle(dev); 815 done(ep, req, 0); 816 req = NULL; 817 } 818 break; 819 820 default: 821 printf("ep0 i/o, odd state %d\n", 822 dev->ep0state); 823 local_irq_restore(flags); 824 return -EL2HLT; 825 } 826 /* can the FIFO can satisfy the request immediately? */ 827 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { 828 if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0 829 && write_fifo(ep, req)) 830 req = NULL; 831 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0 832 && read_fifo(ep, req)) { 833 req = NULL; 834 } 835 836 if (likely(req && ep->desc)) 837 pio_irq_enable(ep->bEndpointAddress); 838 } 839 840 /* pio or dma irq handler advances the queue. */ 841 if (likely(req != NULL)) 842 list_add_tail(&req->queue, &ep->queue); 843 local_irq_restore(flags); 844 845 return 0; 846 } 847 848 849 /* 850 * nuke - dequeue ALL requests 851 */ 852 static void nuke(struct pxa25x_ep *ep, int status) 853 { 854 struct pxa25x_request *req; 855 856 /* called with irqs blocked */ 857 while (!list_empty(&ep->queue)) { 858 req = list_entry(ep->queue.next, 859 struct pxa25x_request, 860 queue); 861 done(ep, req, status); 862 } 863 if (ep->desc) 864 pio_irq_disable(ep->bEndpointAddress); 865 } 866 867 868 /* dequeue JUST ONE request */ 869 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 870 { 871 struct pxa25x_ep *ep; 872 struct pxa25x_request *req; 873 unsigned long flags; 874 875 ep = container_of(_ep, struct pxa25x_ep, ep); 876 if (!_ep || ep->ep.name == ep0name) 877 return -EINVAL; 878 879 local_irq_save(flags); 880 881 /* make sure it's actually queued on this endpoint */ 882 list_for_each_entry(req, &ep->queue, queue) { 883 if (&req->req == _req) 884 break; 885 } 886 if (&req->req != _req) { 887 local_irq_restore(flags); 888 return -EINVAL; 889 } 890 891 done(ep, req, -ECONNRESET); 892 893 local_irq_restore(flags); 894 return 0; 895 } 896 897 /*-------------------------------------------------------------------------*/ 898 899 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) 900 { 901 struct pxa25x_ep *ep; 902 unsigned long flags; 903 904 ep = container_of(_ep, struct pxa25x_ep, ep); 905 if (unlikely(!_ep 906 || (!ep->desc && ep->ep.name != ep0name)) 907 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 908 printf("%s, bad ep\n", __func__); 909 return -EINVAL; 910 } 911 if (value == 0) { 912 /* 913 * this path (reset toggle+halt) is needed to implement 914 * SET_INTERFACE on normal hardware. but it can't be 915 * done from software on the PXA UDC, and the hardware 916 * forgets to do it as part of SET_INTERFACE automagic. 917 */ 918 printf("only host can clear %s halt\n", _ep->name); 919 return -EROFS; 920 } 921 922 local_irq_save(flags); 923 924 if ((ep->bEndpointAddress & USB_DIR_IN) != 0 925 && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0 926 || !list_empty(&ep->queue))) { 927 local_irq_restore(flags); 928 return -EAGAIN; 929 } 930 931 /* FST bit is the same for control, bulk in, bulk out, interrupt in */ 932 writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs); 933 934 /* ep0 needs special care */ 935 if (!ep->desc) { 936 start_watchdog(ep->dev); 937 ep->dev->req_pending = 0; 938 ep->dev->ep0state = EP0_STALL; 939 940 /* and bulk/intr endpoints like dropping stalls too */ 941 } else { 942 unsigned i; 943 for (i = 0; i < 1000; i += 20) { 944 if (readl(ep->reg_udccs) & UDCCS_BI_SST) 945 break; 946 udelay(20); 947 } 948 } 949 local_irq_restore(flags); 950 951 debug("%s halt\n", _ep->name); 952 return 0; 953 } 954 955 static int pxa25x_ep_fifo_status(struct usb_ep *_ep) 956 { 957 struct pxa25x_ep *ep; 958 959 ep = container_of(_ep, struct pxa25x_ep, ep); 960 if (!_ep) { 961 printf("%s, bad ep\n", __func__); 962 return -ENODEV; 963 } 964 /* pxa can't report unclaimed bytes from IN fifos */ 965 if ((ep->bEndpointAddress & USB_DIR_IN) != 0) 966 return -EOPNOTSUPP; 967 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN 968 || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0) 969 return 0; 970 else 971 return (readl(ep->reg_ubcr) & 0xfff) + 1; 972 } 973 974 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) 975 { 976 struct pxa25x_ep *ep; 977 978 ep = container_of(_ep, struct pxa25x_ep, ep); 979 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { 980 printf("%s, bad ep\n", __func__); 981 return; 982 } 983 984 /* toggle and halt bits stay unchanged */ 985 986 /* for OUT, just read and discard the FIFO contents. */ 987 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { 988 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0) 989 (void)readb(ep->reg_uddr); 990 return; 991 } 992 993 /* most IN status is the same, but ISO can't stall */ 994 writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR 995 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 996 ? 0 : UDCCS_BI_SST), ep->reg_udccs); 997 } 998 999 1000 static struct usb_ep_ops pxa25x_ep_ops = { 1001 .enable = pxa25x_ep_enable, 1002 .disable = pxa25x_ep_disable, 1003 1004 .alloc_request = pxa25x_ep_alloc_request, 1005 .free_request = pxa25x_ep_free_request, 1006 1007 .queue = pxa25x_ep_queue, 1008 .dequeue = pxa25x_ep_dequeue, 1009 1010 .set_halt = pxa25x_ep_set_halt, 1011 .fifo_status = pxa25x_ep_fifo_status, 1012 .fifo_flush = pxa25x_ep_fifo_flush, 1013 }; 1014 1015 1016 /* --------------------------------------------------------------------------- 1017 * device-scoped parts of the api to the usb controller hardware 1018 * --------------------------------------------------------------------------- 1019 */ 1020 1021 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) 1022 { 1023 return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) | 1024 (readl(&the_controller->regs->ufnrl) & 0xff); 1025 } 1026 1027 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) 1028 { 1029 /* host may not have enabled remote wakeup */ 1030 if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0) 1031 return -EHOSTUNREACH; 1032 udc_set_mask_UDCCR(UDCCR_RSM); 1033 return 0; 1034 } 1035 1036 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); 1037 static void udc_enable(struct pxa25x_udc *); 1038 static void udc_disable(struct pxa25x_udc *); 1039 1040 /* 1041 * We disable the UDC -- and its 48 MHz clock -- whenever it's not 1042 * in active use. 1043 */ 1044 static int pullup(struct pxa25x_udc *udc) 1045 { 1046 if (udc->pullup) 1047 pullup_on(); 1048 else 1049 pullup_off(); 1050 1051 1052 int is_active = udc->pullup; 1053 if (is_active) { 1054 if (!udc->active) { 1055 udc->active = 1; 1056 udc_enable(udc); 1057 } 1058 } else { 1059 if (udc->active) { 1060 if (udc->gadget.speed != USB_SPEED_UNKNOWN) 1061 stop_activity(udc, udc->driver); 1062 udc_disable(udc); 1063 udc->active = 0; 1064 } 1065 1066 } 1067 return 0; 1068 } 1069 1070 /* VBUS reporting logically comes from a transceiver */ 1071 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) 1072 { 1073 struct pxa25x_udc *udc; 1074 1075 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1076 printf("vbus %s\n", is_active ? "supplied" : "inactive"); 1077 pullup(udc); 1078 return 0; 1079 } 1080 1081 /* drivers may have software control over D+ pullup */ 1082 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) 1083 { 1084 struct pxa25x_udc *udc; 1085 1086 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1087 1088 /* not all boards support pullup control */ 1089 if (!udc->mach->udc_command) 1090 return -EOPNOTSUPP; 1091 1092 udc->pullup = (is_active != 0); 1093 pullup(udc); 1094 return 0; 1095 } 1096 1097 /* 1098 * boards may consume current from VBUS, up to 100-500mA based on config. 1099 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs 1100 * violate USB specs. 1101 */ 1102 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) 1103 { 1104 return -EOPNOTSUPP; 1105 } 1106 1107 static const struct usb_gadget_ops pxa25x_udc_ops = { 1108 .get_frame = pxa25x_udc_get_frame, 1109 .wakeup = pxa25x_udc_wakeup, 1110 .vbus_session = pxa25x_udc_vbus_session, 1111 .pullup = pxa25x_udc_pullup, 1112 .vbus_draw = pxa25x_udc_vbus_draw, 1113 }; 1114 1115 /*-------------------------------------------------------------------------*/ 1116 1117 /* 1118 * udc_disable - disable USB device controller 1119 */ 1120 static void udc_disable(struct pxa25x_udc *dev) 1121 { 1122 /* block all irqs */ 1123 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); 1124 writel(0xff, &dev->regs->uicr0); 1125 writel(0xff, &dev->regs->uicr1); 1126 writel(UFNRH_SIM, &dev->regs->ufnrh); 1127 1128 /* if hardware supports it, disconnect from usb */ 1129 pullup_off(); 1130 1131 udc_clear_mask_UDCCR(UDCCR_UDE); 1132 1133 ep0_idle(dev); 1134 dev->gadget.speed = USB_SPEED_UNKNOWN; 1135 } 1136 1137 /* 1138 * udc_reinit - initialize software state 1139 */ 1140 static void udc_reinit(struct pxa25x_udc *dev) 1141 { 1142 u32 i; 1143 1144 /* device/ep0 records init */ 1145 INIT_LIST_HEAD(&dev->gadget.ep_list); 1146 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 1147 dev->ep0state = EP0_IDLE; 1148 1149 /* basic endpoint records init */ 1150 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1151 struct pxa25x_ep *ep = &dev->ep[i]; 1152 1153 if (i != 0) 1154 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); 1155 1156 ep->desc = NULL; 1157 ep->stopped = 0; 1158 INIT_LIST_HEAD(&ep->queue); 1159 ep->pio_irqs = 0; 1160 } 1161 1162 /* the rest was statically initialized, and is read-only */ 1163 } 1164 1165 /* 1166 * until it's enabled, this UDC should be completely invisible 1167 * to any USB host. 1168 */ 1169 static void udc_enable(struct pxa25x_udc *dev) 1170 { 1171 debug("udc: enabling udc\n"); 1172 1173 udc_clear_mask_UDCCR(UDCCR_UDE); 1174 1175 /* 1176 * Try to clear these bits before we enable the udc. 1177 * Do not touch reset ack bit, we would take care of it in 1178 * interrupt handle routine 1179 */ 1180 udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR); 1181 1182 ep0_idle(dev); 1183 dev->gadget.speed = USB_SPEED_UNKNOWN; 1184 dev->stats.irqs = 0; 1185 1186 /* 1187 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: 1188 * - enable UDC 1189 * - if RESET is already in progress, ack interrupt 1190 * - unmask reset interrupt 1191 */ 1192 udc_set_mask_UDCCR(UDCCR_UDE); 1193 if (!(readl(&dev->regs->udccr) & UDCCR_UDA)) 1194 udc_ack_int_UDCCR(UDCCR_RSTIR); 1195 1196 if (dev->has_cfr /* UDC_RES2 is defined */) { 1197 /* 1198 * pxa255 (a0+) can avoid a set_config race that could 1199 * prevent gadget drivers from configuring correctly 1200 */ 1201 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr); 1202 } 1203 1204 /* enable suspend/resume and reset irqs */ 1205 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM); 1206 1207 /* enable ep0 irqs */ 1208 clrbits_le32(&dev->regs->uicr0, UICR0_IM0); 1209 1210 /* if hardware supports it, pullup D+ and wait for reset */ 1211 pullup_on(); 1212 } 1213 1214 static inline void clear_ep_state(struct pxa25x_udc *dev) 1215 { 1216 unsigned i; 1217 1218 /* 1219 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint 1220 * fifos, and pending transactions mustn't be continued in any case. 1221 */ 1222 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) 1223 nuke(&dev->ep[i], -ECONNABORTED); 1224 } 1225 1226 static void handle_ep0(struct pxa25x_udc *dev) 1227 { 1228 u32 udccs0 = readl(&dev->regs->udccs[0]); 1229 struct pxa25x_ep *ep = &dev->ep[0]; 1230 struct pxa25x_request *req; 1231 union { 1232 struct usb_ctrlrequest r; 1233 u8 raw[8]; 1234 u32 word[2]; 1235 } u; 1236 1237 if (list_empty(&ep->queue)) 1238 req = NULL; 1239 else 1240 req = list_entry(ep->queue.next, struct pxa25x_request, queue); 1241 1242 /* clear stall status */ 1243 if (udccs0 & UDCCS0_SST) { 1244 nuke(ep, -EPIPE); 1245 writel(UDCCS0_SST, &dev->regs->udccs[0]); 1246 stop_watchdog(dev); 1247 ep0_idle(dev); 1248 } 1249 1250 /* previous request unfinished? non-error iff back-to-back ... */ 1251 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { 1252 nuke(ep, 0); 1253 stop_watchdog(dev); 1254 ep0_idle(dev); 1255 } 1256 1257 switch (dev->ep0state) { 1258 case EP0_IDLE: 1259 /* late-breaking status? */ 1260 udccs0 = readl(&dev->regs->udccs[0]); 1261 1262 /* start control request? */ 1263 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) 1264 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { 1265 int i; 1266 1267 nuke(ep, -EPROTO); 1268 1269 /* read SETUP packet */ 1270 for (i = 0; i < 8; i++) { 1271 if (unlikely(!(readl(&dev->regs->udccs[0]) & 1272 UDCCS0_RNE))) { 1273 bad_setup: 1274 debug("SETUP %d!\n", i); 1275 goto stall; 1276 } 1277 u.raw[i] = (u8)readb(&dev->regs->uddr0); 1278 } 1279 if (unlikely((readl(&dev->regs->udccs[0]) & 1280 UDCCS0_RNE) != 0)) 1281 goto bad_setup; 1282 1283 got_setup: 1284 debug("SETUP %02x.%02x v%04x i%04x l%04x\n", 1285 u.r.bRequestType, u.r.bRequest, 1286 le16_to_cpu(u.r.wValue), 1287 le16_to_cpu(u.r.wIndex), 1288 le16_to_cpu(u.r.wLength)); 1289 1290 /* cope with automagic for some standard requests. */ 1291 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) 1292 == USB_TYPE_STANDARD; 1293 dev->req_config = 0; 1294 dev->req_pending = 1; 1295 switch (u.r.bRequest) { 1296 /* hardware restricts gadget drivers here! */ 1297 case USB_REQ_SET_CONFIGURATION: 1298 debug("GOT SET_CONFIGURATION\n"); 1299 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1300 /* 1301 * reflect hardware's automagic 1302 * up to the gadget driver. 1303 */ 1304 config_change: 1305 dev->req_config = 1; 1306 clear_ep_state(dev); 1307 /* 1308 * if !has_cfr, there's no synch 1309 * else use AREN (later) not SA|OPR 1310 * USIR0_IR0 acts edge sensitive 1311 */ 1312 } 1313 break; 1314 /* ... and here, even more ... */ 1315 case USB_REQ_SET_INTERFACE: 1316 if (u.r.bRequestType == USB_RECIP_INTERFACE) { 1317 /* 1318 * udc hardware is broken by design: 1319 * - altsetting may only be zero; 1320 * - hw resets all interfaces' eps; 1321 * - ep reset doesn't include halt(?). 1322 */ 1323 printf("broken set_interface (%d/%d)\n", 1324 le16_to_cpu(u.r.wIndex), 1325 le16_to_cpu(u.r.wValue)); 1326 goto config_change; 1327 } 1328 break; 1329 /* hardware was supposed to hide this */ 1330 case USB_REQ_SET_ADDRESS: 1331 debug("GOT SET ADDRESS\n"); 1332 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1333 ep0start(dev, 0, "address"); 1334 return; 1335 } 1336 break; 1337 } 1338 1339 if (u.r.bRequestType & USB_DIR_IN) 1340 dev->ep0state = EP0_IN_DATA_PHASE; 1341 else 1342 dev->ep0state = EP0_OUT_DATA_PHASE; 1343 1344 i = dev->driver->setup(&dev->gadget, &u.r); 1345 if (i < 0) { 1346 /* hardware automagic preventing STALL... */ 1347 if (dev->req_config) { 1348 /* 1349 * hardware sometimes neglects to tell 1350 * tell us about config change events, 1351 * so later ones may fail... 1352 */ 1353 printf("config change %02x fail %d?\n", 1354 u.r.bRequest, i); 1355 return; 1356 /* 1357 * TODO experiment: if has_cfr, 1358 * hardware didn't ACK; maybe we 1359 * could actually STALL! 1360 */ 1361 } 1362 if (0) { 1363 stall: 1364 /* uninitialized when goto stall */ 1365 i = 0; 1366 } 1367 debug("protocol STALL, " 1368 "%02x err %d\n", 1369 readl(&dev->regs->udccs[0]), i); 1370 1371 /* 1372 * the watchdog timer helps deal with cases 1373 * where udc seems to clear FST wrongly, and 1374 * then NAKs instead of STALLing. 1375 */ 1376 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall"); 1377 start_watchdog(dev); 1378 dev->ep0state = EP0_STALL; 1379 1380 /* deferred i/o == no response yet */ 1381 } else if (dev->req_pending) { 1382 if (likely(dev->ep0state == EP0_IN_DATA_PHASE 1383 || dev->req_std || u.r.wLength)) 1384 ep0start(dev, 0, "defer"); 1385 else 1386 ep0start(dev, UDCCS0_IPR, "defer/IPR"); 1387 } 1388 1389 /* expect at least one data or status stage irq */ 1390 return; 1391 1392 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) 1393 == (UDCCS0_OPR|UDCCS0_SA))) { 1394 unsigned i; 1395 1396 /* 1397 * pxa210/250 erratum 131 for B0/B1 says RNE lies. 1398 * still observed on a pxa255 a0. 1399 */ 1400 debug("e131\n"); 1401 nuke(ep, -EPROTO); 1402 1403 /* read SETUP data, but don't trust it too much */ 1404 for (i = 0; i < 8; i++) 1405 u.raw[i] = (u8)readb(&dev->regs->uddr0); 1406 if ((u.r.bRequestType & USB_RECIP_MASK) 1407 > USB_RECIP_OTHER) 1408 goto stall; 1409 if (u.word[0] == 0 && u.word[1] == 0) 1410 goto stall; 1411 goto got_setup; 1412 } else { 1413 /* 1414 * some random early IRQ: 1415 * - we acked FST 1416 * - IPR cleared 1417 * - OPR got set, without SA (likely status stage) 1418 */ 1419 debug("random IRQ %X %X\n", udccs0, 1420 readl(&dev->regs->udccs[0])); 1421 writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR), 1422 &dev->regs->udccs[0]); 1423 } 1424 break; 1425 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ 1426 if (udccs0 & UDCCS0_OPR) { 1427 debug("ep0in premature status\n"); 1428 if (req) 1429 done(ep, req, 0); 1430 ep0_idle(dev); 1431 } else /* irq was IPR clearing */ { 1432 if (req) { 1433 debug("next ep0 in packet\n"); 1434 /* this IN packet might finish the request */ 1435 (void) write_ep0_fifo(ep, req); 1436 } /* else IN token before response was written */ 1437 } 1438 break; 1439 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ 1440 if (udccs0 & UDCCS0_OPR) { 1441 if (req) { 1442 /* this OUT packet might finish the request */ 1443 if (read_ep0_fifo(ep, req)) 1444 done(ep, req, 0); 1445 /* else more OUT packets expected */ 1446 } /* else OUT token before read was issued */ 1447 } else /* irq was IPR clearing */ { 1448 debug("ep0out premature status\n"); 1449 if (req) 1450 done(ep, req, 0); 1451 ep0_idle(dev); 1452 } 1453 break; 1454 case EP0_END_XFER: 1455 if (req) 1456 done(ep, req, 0); 1457 /* 1458 * ack control-IN status (maybe in-zlp was skipped) 1459 * also appears after some config change events. 1460 */ 1461 if (udccs0 & UDCCS0_OPR) 1462 writel(UDCCS0_OPR, &dev->regs->udccs[0]); 1463 ep0_idle(dev); 1464 break; 1465 case EP0_STALL: 1466 writel(UDCCS0_FST, &dev->regs->udccs[0]); 1467 break; 1468 } 1469 1470 writel(USIR0_IR0, &dev->regs->usir0); 1471 } 1472 1473 static void handle_ep(struct pxa25x_ep *ep) 1474 { 1475 struct pxa25x_request *req; 1476 int is_in = ep->bEndpointAddress & USB_DIR_IN; 1477 int completed; 1478 u32 udccs, tmp; 1479 1480 do { 1481 completed = 0; 1482 if (likely(!list_empty(&ep->queue))) 1483 req = list_entry(ep->queue.next, 1484 struct pxa25x_request, queue); 1485 else 1486 req = NULL; 1487 1488 /* TODO check FST handling */ 1489 1490 udccs = readl(ep->reg_udccs); 1491 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ 1492 tmp = UDCCS_BI_TUR; 1493 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1494 tmp |= UDCCS_BI_SST; 1495 tmp &= udccs; 1496 if (likely(tmp)) 1497 writel(tmp, ep->reg_udccs); 1498 if (req && likely((udccs & UDCCS_BI_TFS) != 0)) 1499 completed = write_fifo(ep, req); 1500 1501 } else { /* irq from RPC (or for ISO, ROF) */ 1502 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1503 tmp = UDCCS_BO_SST | UDCCS_BO_DME; 1504 else 1505 tmp = UDCCS_IO_ROF | UDCCS_IO_DME; 1506 tmp &= udccs; 1507 if (likely(tmp)) 1508 writel(tmp, ep->reg_udccs); 1509 1510 /* fifos can hold packets, ready for reading... */ 1511 if (likely(req)) 1512 completed = read_fifo(ep, req); 1513 else 1514 pio_irq_disable(ep->bEndpointAddress); 1515 } 1516 ep->pio_irqs++; 1517 } while (completed); 1518 } 1519 1520 /* 1521 * pxa25x_udc_irq - interrupt handler 1522 * 1523 * avoid delays in ep0 processing. the control handshaking isn't always 1524 * under software control (pxa250c0 and the pxa255 are better), and delays 1525 * could cause usb protocol errors. 1526 */ 1527 static struct pxa25x_udc memory; 1528 static int 1529 pxa25x_udc_irq(void) 1530 { 1531 struct pxa25x_udc *dev = &memory; 1532 int handled; 1533 1534 test_watchdog(dev); 1535 1536 dev->stats.irqs++; 1537 do { 1538 u32 udccr = readl(&dev->regs->udccr); 1539 1540 handled = 0; 1541 1542 /* SUSpend Interrupt Request */ 1543 if (unlikely(udccr & UDCCR_SUSIR)) { 1544 udc_ack_int_UDCCR(UDCCR_SUSIR); 1545 handled = 1; 1546 debug("USB suspend\n"); 1547 1548 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1549 && dev->driver 1550 && dev->driver->suspend) 1551 dev->driver->suspend(&dev->gadget); 1552 ep0_idle(dev); 1553 } 1554 1555 /* RESume Interrupt Request */ 1556 if (unlikely(udccr & UDCCR_RESIR)) { 1557 udc_ack_int_UDCCR(UDCCR_RESIR); 1558 handled = 1; 1559 debug("USB resume\n"); 1560 1561 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1562 && dev->driver 1563 && dev->driver->resume) 1564 dev->driver->resume(&dev->gadget); 1565 } 1566 1567 /* ReSeT Interrupt Request - USB reset */ 1568 if (unlikely(udccr & UDCCR_RSTIR)) { 1569 udc_ack_int_UDCCR(UDCCR_RSTIR); 1570 handled = 1; 1571 1572 if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) { 1573 debug("USB reset start\n"); 1574 1575 /* 1576 * reset driver and endpoints, 1577 * in case that's not yet done 1578 */ 1579 stop_activity(dev, dev->driver); 1580 1581 } else { 1582 debug("USB reset end\n"); 1583 dev->gadget.speed = USB_SPEED_FULL; 1584 memset(&dev->stats, 0, sizeof dev->stats); 1585 /* driver and endpoints are still reset */ 1586 } 1587 1588 } else { 1589 u32 uicr0 = readl(&dev->regs->uicr0); 1590 u32 uicr1 = readl(&dev->regs->uicr1); 1591 u32 usir0 = readl(&dev->regs->usir0); 1592 u32 usir1 = readl(&dev->regs->usir1); 1593 1594 usir0 = usir0 & ~uicr0; 1595 usir1 = usir1 & ~uicr1; 1596 int i; 1597 1598 if (unlikely(!usir0 && !usir1)) 1599 continue; 1600 1601 debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0); 1602 1603 /* control traffic */ 1604 if (usir0 & USIR0_IR0) { 1605 dev->ep[0].pio_irqs++; 1606 handle_ep0(dev); 1607 handled = 1; 1608 } 1609 1610 /* endpoint data transfers */ 1611 for (i = 0; i < 8; i++) { 1612 u32 tmp = 1 << i; 1613 1614 if (i && (usir0 & tmp)) { 1615 handle_ep(&dev->ep[i]); 1616 setbits_le32(&dev->regs->usir0, tmp); 1617 handled = 1; 1618 } 1619 #ifndef CONFIG_USB_PXA25X_SMALL 1620 if (usir1 & tmp) { 1621 handle_ep(&dev->ep[i+8]); 1622 setbits_le32(&dev->regs->usir1, tmp); 1623 handled = 1; 1624 } 1625 #endif 1626 } 1627 } 1628 1629 /* we could also ask for 1 msec SOF (SIR) interrupts */ 1630 1631 } while (handled); 1632 return IRQ_HANDLED; 1633 } 1634 1635 /*-------------------------------------------------------------------------*/ 1636 1637 /* 1638 * this uses load-time allocation and initialization (instead of 1639 * doing it at run-time) to save code, eliminate fault paths, and 1640 * be more obviously correct. 1641 */ 1642 static struct pxa25x_udc memory = { 1643 .regs = UDC_REGS, 1644 1645 .gadget = { 1646 .ops = &pxa25x_udc_ops, 1647 .ep0 = &memory.ep[0].ep, 1648 .name = driver_name, 1649 }, 1650 1651 /* control endpoint */ 1652 .ep[0] = { 1653 .ep = { 1654 .name = ep0name, 1655 .ops = &pxa25x_ep_ops, 1656 .maxpacket = EP0_FIFO_SIZE, 1657 }, 1658 .dev = &memory, 1659 .reg_udccs = &UDC_REGS->udccs[0], 1660 .reg_uddr = &UDC_REGS->uddr0, 1661 }, 1662 1663 /* first group of endpoints */ 1664 .ep[1] = { 1665 .ep = { 1666 .name = "ep1in-bulk", 1667 .ops = &pxa25x_ep_ops, 1668 .maxpacket = BULK_FIFO_SIZE, 1669 }, 1670 .dev = &memory, 1671 .fifo_size = BULK_FIFO_SIZE, 1672 .bEndpointAddress = USB_DIR_IN | 1, 1673 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1674 .reg_udccs = &UDC_REGS->udccs[1], 1675 .reg_uddr = &UDC_REGS->uddr1, 1676 }, 1677 .ep[2] = { 1678 .ep = { 1679 .name = "ep2out-bulk", 1680 .ops = &pxa25x_ep_ops, 1681 .maxpacket = BULK_FIFO_SIZE, 1682 }, 1683 .dev = &memory, 1684 .fifo_size = BULK_FIFO_SIZE, 1685 .bEndpointAddress = 2, 1686 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1687 .reg_udccs = &UDC_REGS->udccs[2], 1688 .reg_ubcr = &UDC_REGS->ubcr2, 1689 .reg_uddr = &UDC_REGS->uddr2, 1690 }, 1691 #ifndef CONFIG_USB_PXA25X_SMALL 1692 .ep[3] = { 1693 .ep = { 1694 .name = "ep3in-iso", 1695 .ops = &pxa25x_ep_ops, 1696 .maxpacket = ISO_FIFO_SIZE, 1697 }, 1698 .dev = &memory, 1699 .fifo_size = ISO_FIFO_SIZE, 1700 .bEndpointAddress = USB_DIR_IN | 3, 1701 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1702 .reg_udccs = &UDC_REGS->udccs[3], 1703 .reg_uddr = &UDC_REGS->uddr3, 1704 }, 1705 .ep[4] = { 1706 .ep = { 1707 .name = "ep4out-iso", 1708 .ops = &pxa25x_ep_ops, 1709 .maxpacket = ISO_FIFO_SIZE, 1710 }, 1711 .dev = &memory, 1712 .fifo_size = ISO_FIFO_SIZE, 1713 .bEndpointAddress = 4, 1714 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1715 .reg_udccs = &UDC_REGS->udccs[4], 1716 .reg_ubcr = &UDC_REGS->ubcr4, 1717 .reg_uddr = &UDC_REGS->uddr4, 1718 }, 1719 .ep[5] = { 1720 .ep = { 1721 .name = "ep5in-int", 1722 .ops = &pxa25x_ep_ops, 1723 .maxpacket = INT_FIFO_SIZE, 1724 }, 1725 .dev = &memory, 1726 .fifo_size = INT_FIFO_SIZE, 1727 .bEndpointAddress = USB_DIR_IN | 5, 1728 .bmAttributes = USB_ENDPOINT_XFER_INT, 1729 .reg_udccs = &UDC_REGS->udccs[5], 1730 .reg_uddr = &UDC_REGS->uddr5, 1731 }, 1732 1733 /* second group of endpoints */ 1734 .ep[6] = { 1735 .ep = { 1736 .name = "ep6in-bulk", 1737 .ops = &pxa25x_ep_ops, 1738 .maxpacket = BULK_FIFO_SIZE, 1739 }, 1740 .dev = &memory, 1741 .fifo_size = BULK_FIFO_SIZE, 1742 .bEndpointAddress = USB_DIR_IN | 6, 1743 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1744 .reg_udccs = &UDC_REGS->udccs[6], 1745 .reg_uddr = &UDC_REGS->uddr6, 1746 }, 1747 .ep[7] = { 1748 .ep = { 1749 .name = "ep7out-bulk", 1750 .ops = &pxa25x_ep_ops, 1751 .maxpacket = BULK_FIFO_SIZE, 1752 }, 1753 .dev = &memory, 1754 .fifo_size = BULK_FIFO_SIZE, 1755 .bEndpointAddress = 7, 1756 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1757 .reg_udccs = &UDC_REGS->udccs[7], 1758 .reg_ubcr = &UDC_REGS->ubcr7, 1759 .reg_uddr = &UDC_REGS->uddr7, 1760 }, 1761 .ep[8] = { 1762 .ep = { 1763 .name = "ep8in-iso", 1764 .ops = &pxa25x_ep_ops, 1765 .maxpacket = ISO_FIFO_SIZE, 1766 }, 1767 .dev = &memory, 1768 .fifo_size = ISO_FIFO_SIZE, 1769 .bEndpointAddress = USB_DIR_IN | 8, 1770 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1771 .reg_udccs = &UDC_REGS->udccs[8], 1772 .reg_uddr = &UDC_REGS->uddr8, 1773 }, 1774 .ep[9] = { 1775 .ep = { 1776 .name = "ep9out-iso", 1777 .ops = &pxa25x_ep_ops, 1778 .maxpacket = ISO_FIFO_SIZE, 1779 }, 1780 .dev = &memory, 1781 .fifo_size = ISO_FIFO_SIZE, 1782 .bEndpointAddress = 9, 1783 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1784 .reg_udccs = &UDC_REGS->udccs[9], 1785 .reg_ubcr = &UDC_REGS->ubcr9, 1786 .reg_uddr = &UDC_REGS->uddr9, 1787 }, 1788 .ep[10] = { 1789 .ep = { 1790 .name = "ep10in-int", 1791 .ops = &pxa25x_ep_ops, 1792 .maxpacket = INT_FIFO_SIZE, 1793 }, 1794 .dev = &memory, 1795 .fifo_size = INT_FIFO_SIZE, 1796 .bEndpointAddress = USB_DIR_IN | 10, 1797 .bmAttributes = USB_ENDPOINT_XFER_INT, 1798 .reg_udccs = &UDC_REGS->udccs[10], 1799 .reg_uddr = &UDC_REGS->uddr10, 1800 }, 1801 1802 /* third group of endpoints */ 1803 .ep[11] = { 1804 .ep = { 1805 .name = "ep11in-bulk", 1806 .ops = &pxa25x_ep_ops, 1807 .maxpacket = BULK_FIFO_SIZE, 1808 }, 1809 .dev = &memory, 1810 .fifo_size = BULK_FIFO_SIZE, 1811 .bEndpointAddress = USB_DIR_IN | 11, 1812 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1813 .reg_udccs = &UDC_REGS->udccs[11], 1814 .reg_uddr = &UDC_REGS->uddr11, 1815 }, 1816 .ep[12] = { 1817 .ep = { 1818 .name = "ep12out-bulk", 1819 .ops = &pxa25x_ep_ops, 1820 .maxpacket = BULK_FIFO_SIZE, 1821 }, 1822 .dev = &memory, 1823 .fifo_size = BULK_FIFO_SIZE, 1824 .bEndpointAddress = 12, 1825 .bmAttributes = USB_ENDPOINT_XFER_BULK, 1826 .reg_udccs = &UDC_REGS->udccs[12], 1827 .reg_ubcr = &UDC_REGS->ubcr12, 1828 .reg_uddr = &UDC_REGS->uddr12, 1829 }, 1830 .ep[13] = { 1831 .ep = { 1832 .name = "ep13in-iso", 1833 .ops = &pxa25x_ep_ops, 1834 .maxpacket = ISO_FIFO_SIZE, 1835 }, 1836 .dev = &memory, 1837 .fifo_size = ISO_FIFO_SIZE, 1838 .bEndpointAddress = USB_DIR_IN | 13, 1839 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1840 .reg_udccs = &UDC_REGS->udccs[13], 1841 .reg_uddr = &UDC_REGS->uddr13, 1842 }, 1843 .ep[14] = { 1844 .ep = { 1845 .name = "ep14out-iso", 1846 .ops = &pxa25x_ep_ops, 1847 .maxpacket = ISO_FIFO_SIZE, 1848 }, 1849 .dev = &memory, 1850 .fifo_size = ISO_FIFO_SIZE, 1851 .bEndpointAddress = 14, 1852 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 1853 .reg_udccs = &UDC_REGS->udccs[14], 1854 .reg_ubcr = &UDC_REGS->ubcr14, 1855 .reg_uddr = &UDC_REGS->uddr14, 1856 }, 1857 .ep[15] = { 1858 .ep = { 1859 .name = "ep15in-int", 1860 .ops = &pxa25x_ep_ops, 1861 .maxpacket = INT_FIFO_SIZE, 1862 }, 1863 .dev = &memory, 1864 .fifo_size = INT_FIFO_SIZE, 1865 .bEndpointAddress = USB_DIR_IN | 15, 1866 .bmAttributes = USB_ENDPOINT_XFER_INT, 1867 .reg_udccs = &UDC_REGS->udccs[15], 1868 .reg_uddr = &UDC_REGS->uddr15, 1869 }, 1870 #endif /* !CONFIG_USB_PXA25X_SMALL */ 1871 }; 1872 1873 static void udc_command(int cmd) 1874 { 1875 switch (cmd) { 1876 case PXA2XX_UDC_CMD_CONNECT: 1877 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), 1878 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); 1879 1880 /* enable pullup */ 1881 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), 1882 GPCR(CONFIG_USB_DEV_PULLUP_GPIO)); 1883 1884 debug("Connected to USB\n"); 1885 break; 1886 1887 case PXA2XX_UDC_CMD_DISCONNECT: 1888 /* disable pullup resistor */ 1889 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), 1890 GPSR(CONFIG_USB_DEV_PULLUP_GPIO)); 1891 1892 /* setup pin as input, line will float */ 1893 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), 1894 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); 1895 1896 debug("Disconnected from USB\n"); 1897 break; 1898 } 1899 } 1900 1901 static struct pxa2xx_udc_mach_info mach_info = { 1902 .udc_command = udc_command, 1903 }; 1904 1905 /* 1906 * when a driver is successfully registered, it will receive 1907 * control requests including set_configuration(), which enables 1908 * non-control requests. then usb traffic follows until a 1909 * disconnect is reported. then a host may connect again, or 1910 * the driver might get unbound. 1911 */ 1912 int usb_gadget_register_driver(struct usb_gadget_driver *driver) 1913 { 1914 struct pxa25x_udc *dev = &memory; 1915 int retval; 1916 uint32_t chiprev; 1917 1918 if (!driver 1919 || driver->speed < USB_SPEED_FULL 1920 || !driver->disconnect 1921 || !driver->setup) 1922 return -EINVAL; 1923 if (!dev) 1924 return -ENODEV; 1925 if (dev->driver) 1926 return -EBUSY; 1927 1928 /* Enable clock for usb controller */ 1929 setbits_le32(CKEN, CKEN11_USB); 1930 1931 /* first hook up the driver ... */ 1932 dev->driver = driver; 1933 dev->pullup = 1; 1934 1935 /* trigger chiprev-specific logic */ 1936 switch ((chiprev = pxa_get_cpu_revision())) { 1937 case PXA255_A0: 1938 dev->has_cfr = 1; 1939 break; 1940 case PXA250_A0: 1941 case PXA250_A1: 1942 /* A0/A1 "not released"; ep 13, 15 unusable */ 1943 /* fall through */ 1944 case PXA250_B2: case PXA210_B2: 1945 case PXA250_B1: case PXA210_B1: 1946 case PXA250_B0: case PXA210_B0: 1947 /* OUT-DMA is broken ... */ 1948 /* fall through */ 1949 case PXA250_C0: case PXA210_C0: 1950 break; 1951 default: 1952 printf("%s: unrecognized processor: %08x\n", 1953 DRIVER_NAME, chiprev); 1954 return -ENODEV; 1955 } 1956 1957 the_controller = dev; 1958 1959 /* prepare watchdog timer */ 1960 dev->watchdog.running = 0; 1961 dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */ 1962 dev->watchdog.function = udc_watchdog; 1963 1964 udc_disable(dev); 1965 udc_reinit(dev); 1966 1967 dev->mach = &mach_info; 1968 1969 dev->gadget.name = "pxa2xx_udc"; 1970 retval = driver->bind(&dev->gadget); 1971 if (retval) { 1972 printf("bind to driver %s --> error %d\n", 1973 DRIVER_NAME, retval); 1974 dev->driver = NULL; 1975 return retval; 1976 } 1977 1978 /* 1979 * ... then enable host detection and ep0; and we're ready 1980 * for set_configuration as well as eventual disconnect. 1981 */ 1982 printf("registered gadget driver '%s'\n", DRIVER_NAME); 1983 1984 pullup(dev); 1985 dump_state(dev); 1986 return 0; 1987 } 1988 1989 static void 1990 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) 1991 { 1992 int i; 1993 1994 /* don't disconnect drivers more than once */ 1995 if (dev->gadget.speed == USB_SPEED_UNKNOWN) 1996 driver = NULL; 1997 dev->gadget.speed = USB_SPEED_UNKNOWN; 1998 1999 /* prevent new request submissions, kill any outstanding requests */ 2000 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 2001 struct pxa25x_ep *ep = &dev->ep[i]; 2002 2003 ep->stopped = 1; 2004 nuke(ep, -ESHUTDOWN); 2005 } 2006 stop_watchdog(dev); 2007 2008 /* report disconnect; the driver is already quiesced */ 2009 if (driver) 2010 driver->disconnect(&dev->gadget); 2011 2012 /* re-init driver-visible data structures */ 2013 udc_reinit(dev); 2014 } 2015 2016 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 2017 { 2018 struct pxa25x_udc *dev = the_controller; 2019 2020 if (!dev) 2021 return -ENODEV; 2022 if (!driver || driver != dev->driver || !driver->unbind) 2023 return -EINVAL; 2024 2025 local_irq_disable(); 2026 dev->pullup = 0; 2027 pullup(dev); 2028 stop_activity(dev, driver); 2029 local_irq_enable(); 2030 2031 driver->unbind(&dev->gadget); 2032 dev->driver = NULL; 2033 2034 printf("unregistered gadget driver '%s'\n", DRIVER_NAME); 2035 dump_state(dev); 2036 2037 the_controller = NULL; 2038 2039 clrbits_le32(CKEN, CKEN11_USB); 2040 2041 return 0; 2042 } 2043 2044 extern void udc_disconnect(void) 2045 { 2046 setbits_le32(CKEN, CKEN11_USB); 2047 udc_clear_mask_UDCCR(UDCCR_UDE); 2048 udc_command(PXA2XX_UDC_CMD_DISCONNECT); 2049 clrbits_le32(CKEN, CKEN11_USB); 2050 } 2051 2052 /*-------------------------------------------------------------------------*/ 2053 2054 extern int 2055 usb_gadget_handle_interrupts(void) 2056 { 2057 return pxa25x_udc_irq(); 2058 } 2059