1 /*
2  * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
3  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
4  *
5  * Copyright (C) 2009 for Samsung Electronics
6  *
7  * BSP Support for Samsung's UDC driver
8  * available at:
9  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
10  *
11  * State machine bugfixes:
12  * Marek Szyprowski <m.szyprowski@samsung.com>
13  *
14  * Ported to u-boot:
15  * Marek Szyprowski <m.szyprowski@samsung.com>
16  * Lukasz Majewski <l.majewski@samsumg.com>
17  *
18  * SPDX-License-Identifier:	GPL-2.0+
19  */
20 
21 static u8 clear_feature_num;
22 int clear_feature_flag;
23 
24 /* Bulk-Only Mass Storage Reset (class-specific request) */
25 #define GET_MAX_LUN_REQUEST	0xFE
26 #define BOT_RESET_REQUEST	0xFF
27 
28 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
29 {
30 	u32 ep_ctrl;
31 
32 	writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
33 	writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
34 
35 	ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
36 	writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
37 	       &reg->in_endp[EP0_CON].diepctl);
38 
39 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
40 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
41 	dev->ep0state = WAIT_FOR_IN_COMPLETE;
42 }
43 
44 static void dwc2_udc_pre_setup(void)
45 {
46 	u32 ep_ctrl;
47 
48 	debug_cond(DEBUG_IN_EP,
49 		   "%s : Prepare Setup packets.\n", __func__);
50 
51 	writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
52 	       &reg->out_endp[EP0_CON].doeptsiz);
53 	writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
54 
55 	ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
56 	writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
57 
58 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
59 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
60 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
61 		__func__, readl(&reg->out_endp[EP0_CON].doepctl));
62 
63 }
64 
65 static inline void dwc2_ep0_complete_out(void)
66 {
67 	u32 ep_ctrl;
68 
69 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
70 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
71 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
72 		__func__, readl(&reg->out_endp[EP0_CON].doepctl));
73 
74 	debug_cond(DEBUG_IN_EP,
75 		"%s : Prepare Complete Out packet.\n", __func__);
76 
77 	writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
78 	       &reg->out_endp[EP0_CON].doeptsiz);
79 	writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
80 
81 	ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
82 	writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
83 	       &reg->out_endp[EP0_CON].doepctl);
84 
85 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
86 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
87 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
88 		__func__, readl(&reg->out_endp[EP0_CON].doepctl));
89 
90 }
91 
92 
93 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
94 {
95 	u32 *buf, ctrl;
96 	u32 length, pktcnt;
97 	u32 ep_num = ep_index(ep);
98 
99 	buf = req->req.buf + req->req.actual;
100 	length = min_t(u32, req->req.length - req->req.actual,
101 		       ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
102 
103 	ep->len = length;
104 	ep->dma_buf = buf;
105 
106 	if (ep_num == EP0_CON || length == 0)
107 		pktcnt = 1;
108 	else
109 		pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
110 
111 	ctrl =  readl(&reg->out_endp[ep_num].doepctl);
112 
113 	invalidate_dcache_range((unsigned long) ep->dma_buf,
114 				(unsigned long) ep->dma_buf +
115 				ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
116 
117 	writel((unsigned long) ep->dma_buf, &reg->out_endp[ep_num].doepdma);
118 	writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
119 	       &reg->out_endp[ep_num].doeptsiz);
120 	writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
121 
122 	debug_cond(DEBUG_OUT_EP != 0,
123 		   "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
124 		   "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
125 		   "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
126 		   __func__, ep_num,
127 		   readl(&reg->out_endp[ep_num].doepdma),
128 		   readl(&reg->out_endp[ep_num].doeptsiz),
129 		   readl(&reg->out_endp[ep_num].doepctl),
130 		   buf, pktcnt, length);
131 	return 0;
132 
133 }
134 
135 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
136 {
137 	u32 *buf, ctrl = 0;
138 	u32 length, pktcnt;
139 	u32 ep_num = ep_index(ep);
140 
141 	buf = req->req.buf + req->req.actual;
142 	length = req->req.length - req->req.actual;
143 
144 	if (ep_num == EP0_CON)
145 		length = min(length, (u32)ep_maxpacket(ep));
146 
147 	ep->len = length;
148 	ep->dma_buf = buf;
149 
150 	flush_dcache_range((unsigned long) ep->dma_buf,
151 			   (unsigned long) ep->dma_buf +
152 			   ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
153 
154 	if (length == 0)
155 		pktcnt = 1;
156 	else
157 		pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
158 
159 	/* Flush the endpoint's Tx FIFO */
160 	writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
161 	writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
162 	while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
163 		;
164 
165 	writel((unsigned long) ep->dma_buf, &reg->in_endp[ep_num].diepdma);
166 	writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
167 	       &reg->in_endp[ep_num].dieptsiz);
168 
169 	ctrl = readl(&reg->in_endp[ep_num].diepctl);
170 
171 	/* Write the FIFO number to be used for this endpoint */
172 	ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
173 	ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
174 
175 	/* Clear reserved (Next EP) bits */
176 	ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
177 
178 	writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
179 
180 	debug_cond(DEBUG_IN_EP,
181 		"%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
182 		"DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
183 		"\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
184 		__func__, ep_num,
185 		readl(&reg->in_endp[ep_num].diepdma),
186 		readl(&reg->in_endp[ep_num].dieptsiz),
187 		readl(&reg->in_endp[ep_num].diepctl),
188 		buf, pktcnt, length);
189 
190 	return length;
191 }
192 
193 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
194 {
195 	struct dwc2_ep *ep = &dev->ep[ep_num];
196 	struct dwc2_request *req = NULL;
197 	u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
198 
199 	if (list_empty(&ep->queue)) {
200 		debug_cond(DEBUG_OUT_EP != 0,
201 			   "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
202 			   __func__, ep_num);
203 		return;
204 
205 	}
206 
207 	req = list_entry(ep->queue.next, struct dwc2_request, queue);
208 	ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
209 
210 	if (ep_num == EP0_CON)
211 		xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
212 	else
213 		xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
214 
215 	xfer_size = ep->len - xfer_size;
216 
217 	/*
218 	 * NOTE:
219 	 *
220 	 * Please be careful with proper buffer allocation for USB request,
221 	 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
222 	 * with starting address, but also its size shall be a cache line
223 	 * multiplication.
224 	 *
225 	 * This will prevent from corruption of data allocated immediatelly
226 	 * before or after the buffer.
227 	 *
228 	 * For armv7, the cache_v7.c provides proper code to emit "ERROR"
229 	 * message to warn users.
230 	 */
231 	invalidate_dcache_range((unsigned long) ep->dma_buf,
232 				(unsigned long) ep->dma_buf +
233 				ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
234 
235 	req->req.actual += min(xfer_size, req->req.length - req->req.actual);
236 	is_short = !!(xfer_size % ep->ep.maxpacket);
237 
238 	debug_cond(DEBUG_OUT_EP != 0,
239 		   "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
240 		   "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
241 		   __func__, ep_num, req->req.actual, req->req.length,
242 		   is_short, ep_tsr, req->req.length - req->req.actual);
243 
244 	if (is_short || req->req.actual == req->req.length) {
245 		if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
246 			debug_cond(DEBUG_OUT_EP != 0, "	=> Send ZLP\n");
247 			dwc2_udc_ep0_zlp(dev);
248 			/* packet will be completed in complete_tx() */
249 			dev->ep0state = WAIT_FOR_IN_COMPLETE;
250 		} else {
251 			done(ep, req, 0);
252 
253 			if (!list_empty(&ep->queue)) {
254 				req = list_entry(ep->queue.next,
255 					struct dwc2_request, queue);
256 				debug_cond(DEBUG_OUT_EP != 0,
257 					   "%s: Next Rx request start...\n",
258 					   __func__);
259 				setdma_rx(ep, req);
260 			}
261 		}
262 	} else
263 		setdma_rx(ep, req);
264 }
265 
266 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
267 {
268 	struct dwc2_ep *ep = &dev->ep[ep_num];
269 	struct dwc2_request *req;
270 	u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
271 	u32 last;
272 
273 	if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
274 		dev->ep0state = WAIT_FOR_OUT_COMPLETE;
275 		dwc2_ep0_complete_out();
276 		return;
277 	}
278 
279 	if (list_empty(&ep->queue)) {
280 		debug_cond(DEBUG_IN_EP,
281 			"%s: TX DMA done : NULL REQ on IN EP-%d\n",
282 			__func__, ep_num);
283 		return;
284 
285 	}
286 
287 	req = list_entry(ep->queue.next, struct dwc2_request, queue);
288 
289 	ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
290 
291 	xfer_size = ep->len;
292 	is_short = (xfer_size < ep->ep.maxpacket);
293 	req->req.actual += min(xfer_size, req->req.length - req->req.actual);
294 
295 	debug_cond(DEBUG_IN_EP,
296 		"%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
297 		"is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
298 		__func__, ep_num, req->req.actual, req->req.length,
299 		is_short, ep_tsr, req->req.length - req->req.actual);
300 
301 	if (ep_num == 0) {
302 		if (dev->ep0state == DATA_STATE_XMIT) {
303 			debug_cond(DEBUG_IN_EP,
304 				"%s: ep_num = %d, ep0stat =="
305 				"DATA_STATE_XMIT\n",
306 				__func__, ep_num);
307 			last = write_fifo_ep0(ep, req);
308 			if (last)
309 				dev->ep0state = WAIT_FOR_COMPLETE;
310 		} else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
311 			debug_cond(DEBUG_IN_EP,
312 				"%s: ep_num = %d, completing request\n",
313 				__func__, ep_num);
314 			done(ep, req, 0);
315 			dev->ep0state = WAIT_FOR_SETUP;
316 		} else if (dev->ep0state == WAIT_FOR_COMPLETE) {
317 			debug_cond(DEBUG_IN_EP,
318 				"%s: ep_num = %d, completing request\n",
319 				__func__, ep_num);
320 			done(ep, req, 0);
321 			dev->ep0state = WAIT_FOR_OUT_COMPLETE;
322 			dwc2_ep0_complete_out();
323 		} else {
324 			debug_cond(DEBUG_IN_EP,
325 				"%s: ep_num = %d, invalid ep state\n",
326 				__func__, ep_num);
327 		}
328 		return;
329 	}
330 
331 	if (req->req.actual == req->req.length)
332 		done(ep, req, 0);
333 
334 	if (!list_empty(&ep->queue)) {
335 		req = list_entry(ep->queue.next, struct dwc2_request, queue);
336 		debug_cond(DEBUG_IN_EP,
337 			"%s: Next Tx request start...\n", __func__);
338 		setdma_tx(ep, req);
339 	}
340 }
341 
342 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
343 {
344 	struct dwc2_ep *ep = &dev->ep[ep_num];
345 	struct dwc2_request *req;
346 
347 	debug_cond(DEBUG_IN_EP,
348 		"%s: Check queue, ep_num = %d\n", __func__, ep_num);
349 
350 	if (!list_empty(&ep->queue)) {
351 		req = list_entry(ep->queue.next, struct dwc2_request, queue);
352 		debug_cond(DEBUG_IN_EP,
353 			"%s: Next Tx request(0x%p) start...\n",
354 			__func__, req);
355 
356 		if (ep_is_in(ep))
357 			setdma_tx(ep, req);
358 		else
359 			setdma_rx(ep, req);
360 	} else {
361 		debug_cond(DEBUG_IN_EP,
362 			"%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
363 
364 		return;
365 	}
366 
367 }
368 
369 static void process_ep_in_intr(struct dwc2_udc *dev)
370 {
371 	u32 ep_intr, ep_intr_status;
372 	u8 ep_num = 0;
373 
374 	ep_intr = readl(&reg->daint);
375 	debug_cond(DEBUG_IN_EP,
376 		"*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
377 
378 	ep_intr &= DAINT_MASK;
379 
380 	while (ep_intr) {
381 		if (ep_intr & DAINT_IN_EP_INT(1)) {
382 			ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
383 			debug_cond(DEBUG_IN_EP,
384 				   "\tEP%d-IN : DIEPINT = 0x%x\n",
385 				   ep_num, ep_intr_status);
386 
387 			/* Interrupt Clear */
388 			writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
389 
390 			if (ep_intr_status & TRANSFER_DONE) {
391 				complete_tx(dev, ep_num);
392 
393 				if (ep_num == 0) {
394 					if (dev->ep0state ==
395 					    WAIT_FOR_IN_COMPLETE)
396 						dev->ep0state = WAIT_FOR_SETUP;
397 
398 					if (dev->ep0state == WAIT_FOR_SETUP)
399 						dwc2_udc_pre_setup();
400 
401 					/* continue transfer after
402 					   set_clear_halt for DMA mode */
403 					if (clear_feature_flag == 1) {
404 						dwc2_udc_check_tx_queue(dev,
405 							clear_feature_num);
406 						clear_feature_flag = 0;
407 					}
408 				}
409 			}
410 		}
411 		ep_num++;
412 		ep_intr >>= 1;
413 	}
414 }
415 
416 static void process_ep_out_intr(struct dwc2_udc *dev)
417 {
418 	u32 ep_intr, ep_intr_status;
419 	u8 ep_num = 0;
420 
421 	ep_intr = readl(&reg->daint);
422 	debug_cond(DEBUG_OUT_EP != 0,
423 		   "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
424 		   __func__, ep_intr);
425 
426 	ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
427 
428 	while (ep_intr) {
429 		if (ep_intr & 0x1) {
430 			ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
431 			debug_cond(DEBUG_OUT_EP != 0,
432 				   "\tEP%d-OUT : DOEPINT = 0x%x\n",
433 				   ep_num, ep_intr_status);
434 
435 			/* Interrupt Clear */
436 			writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
437 
438 			if (ep_num == 0) {
439 				if (ep_intr_status & TRANSFER_DONE) {
440 					if (dev->ep0state !=
441 					    WAIT_FOR_OUT_COMPLETE)
442 						complete_rx(dev, ep_num);
443 					else {
444 						dev->ep0state = WAIT_FOR_SETUP;
445 						dwc2_udc_pre_setup();
446 					}
447 				}
448 
449 				if (ep_intr_status &
450 				    CTRL_OUT_EP_SETUP_PHASE_DONE) {
451 					debug_cond(DEBUG_OUT_EP != 0,
452 						   "SETUP packet arrived\n");
453 					dwc2_handle_ep0(dev);
454 				}
455 			} else {
456 				if (ep_intr_status & TRANSFER_DONE)
457 					complete_rx(dev, ep_num);
458 			}
459 		}
460 		ep_num++;
461 		ep_intr >>= 1;
462 	}
463 }
464 
465 /*
466  *	usb client interrupt handler.
467  */
468 static int dwc2_udc_irq(int irq, void *_dev)
469 {
470 	struct dwc2_udc *dev = _dev;
471 	u32 intr_status;
472 	u32 usb_status, gintmsk;
473 	unsigned long flags = 0;
474 
475 	spin_lock_irqsave(&dev->lock, flags);
476 
477 	intr_status = readl(&reg->gintsts);
478 	gintmsk = readl(&reg->gintmsk);
479 
480 	debug_cond(DEBUG_ISR,
481 		  "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
482 		  "DAINT : 0x%x, DAINTMSK : 0x%x\n",
483 		  __func__, intr_status, state_names[dev->ep0state], gintmsk,
484 		  readl(&reg->daint), readl(&reg->daintmsk));
485 
486 	if (!intr_status) {
487 		spin_unlock_irqrestore(&dev->lock, flags);
488 		return IRQ_HANDLED;
489 	}
490 
491 	if (intr_status & INT_ENUMDONE) {
492 		debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
493 
494 		writel(INT_ENUMDONE, &reg->gintsts);
495 		usb_status = (readl(&reg->dsts) & 0x6);
496 
497 		if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
498 			debug_cond(DEBUG_ISR,
499 				   "\t\tFull Speed Detection\n");
500 			set_max_pktsize(dev, USB_SPEED_FULL);
501 
502 		} else {
503 			debug_cond(DEBUG_ISR,
504 				"\t\tHigh Speed Detection : 0x%x\n",
505 				usb_status);
506 			set_max_pktsize(dev, USB_SPEED_HIGH);
507 		}
508 	}
509 
510 	if (intr_status & INT_EARLY_SUSPEND) {
511 		debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
512 		writel(INT_EARLY_SUSPEND, &reg->gintsts);
513 	}
514 
515 	if (intr_status & INT_SUSPEND) {
516 		usb_status = readl(&reg->dsts);
517 		debug_cond(DEBUG_ISR,
518 			"\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
519 		writel(INT_SUSPEND, &reg->gintsts);
520 
521 		if (dev->gadget.speed != USB_SPEED_UNKNOWN
522 		    && dev->driver) {
523 			if (dev->driver->suspend)
524 				dev->driver->suspend(&dev->gadget);
525 
526 			/* HACK to let gadget detect disconnected state */
527 			if (dev->driver->disconnect) {
528 				spin_unlock_irqrestore(&dev->lock, flags);
529 				dev->driver->disconnect(&dev->gadget);
530 				spin_lock_irqsave(&dev->lock, flags);
531 			}
532 		}
533 	}
534 
535 	if (intr_status & INT_RESUME) {
536 		debug_cond(DEBUG_ISR, "\tResume interrupt\n");
537 		writel(INT_RESUME, &reg->gintsts);
538 
539 		if (dev->gadget.speed != USB_SPEED_UNKNOWN
540 		    && dev->driver
541 		    && dev->driver->resume) {
542 
543 			dev->driver->resume(&dev->gadget);
544 		}
545 	}
546 
547 	if (intr_status & INT_RESET) {
548 		usb_status = readl(&reg->gotgctl);
549 		debug_cond(DEBUG_ISR,
550 			"\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
551 		writel(INT_RESET, &reg->gintsts);
552 
553 		if ((usb_status & 0xc0000) == (0x3 << 18)) {
554 			if (reset_available) {
555 				debug_cond(DEBUG_ISR,
556 					"\t\tOTG core got reset (%d)!!\n",
557 					reset_available);
558 				reconfig_usbd(dev);
559 				dev->ep0state = WAIT_FOR_SETUP;
560 				reset_available = 0;
561 				dwc2_udc_pre_setup();
562 			} else
563 				reset_available = 1;
564 
565 		} else {
566 			reset_available = 1;
567 			debug_cond(DEBUG_ISR,
568 				   "\t\tRESET handling skipped\n");
569 		}
570 	}
571 
572 	if (intr_status & INT_IN_EP)
573 		process_ep_in_intr(dev);
574 
575 	if (intr_status & INT_OUT_EP)
576 		process_ep_out_intr(dev);
577 
578 	spin_unlock_irqrestore(&dev->lock, flags);
579 
580 	return IRQ_HANDLED;
581 }
582 
583 /** Queue one request
584  *  Kickstart transfer if needed
585  */
586 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
587 			 gfp_t gfp_flags)
588 {
589 	struct dwc2_request *req;
590 	struct dwc2_ep *ep;
591 	struct dwc2_udc *dev;
592 	unsigned long flags = 0;
593 	u32 ep_num, gintsts;
594 
595 	req = container_of(_req, struct dwc2_request, req);
596 	if (unlikely(!_req || !_req->complete || !_req->buf
597 		     || !list_empty(&req->queue))) {
598 
599 		debug("%s: bad params\n", __func__);
600 		return -EINVAL;
601 	}
602 
603 	ep = container_of(_ep, struct dwc2_ep, ep);
604 
605 	if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
606 
607 		debug("%s: bad ep: %s, %d, %p\n", __func__,
608 		      ep->ep.name, !ep->desc, _ep);
609 		return -EINVAL;
610 	}
611 
612 	ep_num = ep_index(ep);
613 	dev = ep->dev;
614 	if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
615 
616 		debug("%s: bogus device state %p\n", __func__, dev->driver);
617 		return -ESHUTDOWN;
618 	}
619 
620 	spin_lock_irqsave(&dev->lock, flags);
621 
622 	_req->status = -EINPROGRESS;
623 	_req->actual = 0;
624 
625 	/* kickstart this i/o queue? */
626 	debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
627 		"Q empty = %d, stopped = %d\n",
628 		__func__, _ep->name, ep_is_in(ep) ? "in" : "out",
629 		_req, _req->length, _req->buf,
630 		list_empty(&ep->queue), ep->stopped);
631 
632 #ifdef DEBUG
633 	{
634 		int i, len = _req->length;
635 
636 		printf("pkt = ");
637 		if (len > 64)
638 			len = 64;
639 		for (i = 0; i < len; i++) {
640 			printf("%02x", ((u8 *)_req->buf)[i]);
641 			if ((i & 7) == 7)
642 				printf(" ");
643 		}
644 		printf("\n");
645 	}
646 #endif
647 
648 	if (list_empty(&ep->queue) && !ep->stopped) {
649 
650 		if (ep_num == 0) {
651 			/* EP0 */
652 			list_add_tail(&req->queue, &ep->queue);
653 			dwc2_ep0_kick(dev, ep);
654 			req = 0;
655 
656 		} else if (ep_is_in(ep)) {
657 			gintsts = readl(&reg->gintsts);
658 			debug_cond(DEBUG_IN_EP,
659 				   "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
660 				   __func__, gintsts);
661 
662 			setdma_tx(ep, req);
663 		} else {
664 			gintsts = readl(&reg->gintsts);
665 			debug_cond(DEBUG_OUT_EP != 0,
666 				   "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
667 				   __func__, gintsts);
668 
669 			setdma_rx(ep, req);
670 		}
671 	}
672 
673 	/* pio or dma irq handler advances the queue. */
674 	if (likely(req != 0))
675 		list_add_tail(&req->queue, &ep->queue);
676 
677 	spin_unlock_irqrestore(&dev->lock, flags);
678 
679 	return 0;
680 }
681 
682 /****************************************************************/
683 /* End Point 0 related functions                                */
684 /****************************************************************/
685 
686 /* return:  0 = still running, 1 = completed, negative = errno */
687 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
688 {
689 	u32 max;
690 	unsigned count;
691 	int is_last;
692 
693 	max = ep_maxpacket(ep);
694 
695 	debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
696 
697 	count = setdma_tx(ep, req);
698 
699 	/* last packet is usually short (or a zlp) */
700 	if (likely(count != max))
701 		is_last = 1;
702 	else {
703 		if (likely(req->req.length != req->req.actual + count)
704 		    || req->req.zero)
705 			is_last = 0;
706 		else
707 			is_last = 1;
708 	}
709 
710 	debug_cond(DEBUG_EP0 != 0,
711 		   "%s: wrote %s %d bytes%s %d left %p\n", __func__,
712 		   ep->ep.name, count,
713 		   is_last ? "/L" : "",
714 		   req->req.length - req->req.actual - count, req);
715 
716 	/* requests complete when all IN data is in the FIFO */
717 	if (is_last) {
718 		ep->dev->ep0state = WAIT_FOR_SETUP;
719 		return 1;
720 	}
721 
722 	return 0;
723 }
724 
725 static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max)
726 {
727 	invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
728 				ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
729 
730 	debug_cond(DEBUG_EP0 != 0,
731 		   "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
732 		   max, ep_index(ep), cp);
733 
734 	return max;
735 }
736 
737 /**
738  * udc_set_address - set the USB address for this device
739  * @address:
740  *
741  * Called from control endpoint function
742  * after it decodes a set address setup packet.
743  */
744 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
745 {
746 	u32 ctrl = readl(&reg->dcfg);
747 	writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
748 
749 	dwc2_udc_ep0_zlp(dev);
750 
751 	debug_cond(DEBUG_EP0 != 0,
752 		   "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
753 		   __func__, address, readl(&reg->dcfg));
754 
755 	dev->usb_address = address;
756 }
757 
758 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
759 {
760 	struct dwc2_udc *dev;
761 	u32		ep_ctrl = 0;
762 
763 	dev = ep->dev;
764 	ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
765 
766 	/* set the disable and stall bits */
767 	if (ep_ctrl & DEPCTL_EPENA)
768 		ep_ctrl |= DEPCTL_EPDIS;
769 
770 	ep_ctrl |= DEPCTL_STALL;
771 
772 	writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
773 
774 	debug_cond(DEBUG_EP0 != 0,
775 		   "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
776 		   __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
777 	/*
778 	 * The application can only set this bit, and the core clears it,
779 	 * when a SETUP token is received for this endpoint
780 	 */
781 	dev->ep0state = WAIT_FOR_SETUP;
782 
783 	dwc2_udc_pre_setup();
784 }
785 
786 static void dwc2_ep0_read(struct dwc2_udc *dev)
787 {
788 	struct dwc2_request *req;
789 	struct dwc2_ep *ep = &dev->ep[0];
790 
791 	if (!list_empty(&ep->queue)) {
792 		req = list_entry(ep->queue.next, struct dwc2_request, queue);
793 
794 	} else {
795 		debug("%s: ---> BUG\n", __func__);
796 		BUG();
797 		return;
798 	}
799 
800 	debug_cond(DEBUG_EP0 != 0,
801 		   "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
802 		   __func__, req, req->req.length, req->req.actual);
803 
804 	if (req->req.length == 0) {
805 		/* zlp for Set_configuration, Set_interface,
806 		 * or Bulk-Only mass storge reset */
807 
808 		ep->len = 0;
809 		dwc2_udc_ep0_zlp(dev);
810 
811 		debug_cond(DEBUG_EP0 != 0,
812 			   "%s: req.length = 0, bRequest = %d\n",
813 			   __func__, usb_ctrl->bRequest);
814 		return;
815 	}
816 
817 	setdma_rx(ep, req);
818 }
819 
820 /*
821  * DATA_STATE_XMIT
822  */
823 static int dwc2_ep0_write(struct dwc2_udc *dev)
824 {
825 	struct dwc2_request *req;
826 	struct dwc2_ep *ep = &dev->ep[0];
827 	int ret, need_zlp = 0;
828 
829 	if (list_empty(&ep->queue))
830 		req = 0;
831 	else
832 		req = list_entry(ep->queue.next, struct dwc2_request, queue);
833 
834 	if (!req) {
835 		debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
836 		return 0;
837 	}
838 
839 	debug_cond(DEBUG_EP0 != 0,
840 		   "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
841 		   __func__, req, req->req.length, req->req.actual);
842 
843 	if (req->req.length - req->req.actual == ep0_fifo_size) {
844 		/* Next write will end with the packet size, */
845 		/* so we need Zero-length-packet */
846 		need_zlp = 1;
847 	}
848 
849 	ret = write_fifo_ep0(ep, req);
850 
851 	if ((ret == 1) && !need_zlp) {
852 		/* Last packet */
853 		dev->ep0state = WAIT_FOR_COMPLETE;
854 		debug_cond(DEBUG_EP0 != 0,
855 			   "%s: finished, waiting for status\n", __func__);
856 
857 	} else {
858 		dev->ep0state = DATA_STATE_XMIT;
859 		debug_cond(DEBUG_EP0 != 0,
860 			   "%s: not finished\n", __func__);
861 	}
862 
863 	return 1;
864 }
865 
866 static int dwc2_udc_get_status(struct dwc2_udc *dev,
867 		struct usb_ctrlrequest *crq)
868 {
869 	u8 ep_num = crq->wIndex & 0x7F;
870 	u16 g_status = 0;
871 	u32 ep_ctrl;
872 
873 	debug_cond(DEBUG_SETUP != 0,
874 		   "%s: *** USB_REQ_GET_STATUS\n", __func__);
875 	printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
876 	switch (crq->bRequestType & USB_RECIP_MASK) {
877 	case USB_RECIP_INTERFACE:
878 		g_status = 0;
879 		debug_cond(DEBUG_SETUP != 0,
880 			   "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
881 			   g_status);
882 		break;
883 
884 	case USB_RECIP_DEVICE:
885 		g_status = 0x1; /* Self powered */
886 		debug_cond(DEBUG_SETUP != 0,
887 			   "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
888 			   g_status);
889 		break;
890 
891 	case USB_RECIP_ENDPOINT:
892 		if (crq->wLength > 2) {
893 			debug_cond(DEBUG_SETUP != 0,
894 				   "\tGET_STATUS:Not support EP or wLength\n");
895 			return 1;
896 		}
897 
898 		g_status = dev->ep[ep_num].stopped;
899 		debug_cond(DEBUG_SETUP != 0,
900 			   "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
901 			   g_status);
902 
903 		break;
904 
905 	default:
906 		return 1;
907 	}
908 
909 	memcpy(usb_ctrl, &g_status, sizeof(g_status));
910 
911 	flush_dcache_range((unsigned long) usb_ctrl,
912 			   (unsigned long) usb_ctrl +
913 			   ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
914 
915 	writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
916 	writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
917 	       &reg->in_endp[EP0_CON].dieptsiz);
918 
919 	ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
920 	writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
921 	       &reg->in_endp[EP0_CON].diepctl);
922 	dev->ep0state = WAIT_FOR_NULL_COMPLETE;
923 
924 	return 0;
925 }
926 
927 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
928 {
929 	u8		ep_num;
930 	u32		ep_ctrl = 0;
931 
932 	ep_num = ep_index(ep);
933 	debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
934 
935 	if (ep_is_in(ep)) {
936 		ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
937 		ep_ctrl |= DEPCTL_SNAK;
938 		writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
939 		debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
940 			__func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
941 	} else {
942 		ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
943 		ep_ctrl |= DEPCTL_SNAK;
944 		writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
945 		debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
946 		      __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
947 	}
948 
949 	return;
950 }
951 
952 
953 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
954 {
955 	u8		ep_num;
956 	u32		ep_ctrl = 0;
957 
958 	ep_num = ep_index(ep);
959 	debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
960 
961 	if (ep_is_in(ep)) {
962 		ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
963 
964 		/* set the disable and stall bits */
965 		if (ep_ctrl & DEPCTL_EPENA)
966 			ep_ctrl |= DEPCTL_EPDIS;
967 
968 		ep_ctrl |= DEPCTL_STALL;
969 
970 		writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
971 		debug("%s: set stall, DIEPCTL%d = 0x%x\n",
972 		      __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
973 
974 	} else {
975 		ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
976 
977 		/* set the stall bit */
978 		ep_ctrl |= DEPCTL_STALL;
979 
980 		writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
981 		debug("%s: set stall, DOEPCTL%d = 0x%x\n",
982 		      __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
983 	}
984 
985 	return;
986 }
987 
988 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
989 {
990 	u8		ep_num;
991 	u32		ep_ctrl = 0;
992 
993 	ep_num = ep_index(ep);
994 	debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
995 
996 	if (ep_is_in(ep)) {
997 		ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
998 
999 		/* clear stall bit */
1000 		ep_ctrl &= ~DEPCTL_STALL;
1001 
1002 		/*
1003 		 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1004 		 * of whether an endpoint has the Halt feature set, a
1005 		 * ClearFeature(ENDPOINT_HALT) request always results in the
1006 		 * data toggle being reinitialized to DATA0.
1007 		 */
1008 		if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1009 		    || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1010 			ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1011 		}
1012 
1013 		writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1014 		debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1015 			__func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1016 
1017 	} else {
1018 		ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1019 
1020 		/* clear stall bit */
1021 		ep_ctrl &= ~DEPCTL_STALL;
1022 
1023 		if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1024 		    || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1025 			ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1026 		}
1027 
1028 		writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1029 		debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1030 		      __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1031 	}
1032 
1033 	return;
1034 }
1035 
1036 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1037 {
1038 	struct dwc2_ep	*ep;
1039 	struct dwc2_udc	*dev;
1040 	unsigned long	flags = 0;
1041 	u8		ep_num;
1042 
1043 	ep = container_of(_ep, struct dwc2_ep, ep);
1044 	ep_num = ep_index(ep);
1045 
1046 	if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1047 		     ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1048 		debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1049 		return -EINVAL;
1050 	}
1051 
1052 	/* Attempt to halt IN ep will fail if any transfer requests
1053 	 * are still queue */
1054 	if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1055 		debug("%s: %s queue not empty, req = %p\n",
1056 			__func__, ep->ep.name,
1057 			list_entry(ep->queue.next, struct dwc2_request, queue));
1058 
1059 		return -EAGAIN;
1060 	}
1061 
1062 	dev = ep->dev;
1063 	debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1064 
1065 	spin_lock_irqsave(&dev->lock, flags);
1066 
1067 	if (value == 0) {
1068 		ep->stopped = 0;
1069 		dwc2_udc_ep_clear_stall(ep);
1070 	} else {
1071 		if (ep_num == 0)
1072 			dev->ep0state = WAIT_FOR_SETUP;
1073 
1074 		ep->stopped = 1;
1075 		dwc2_udc_ep_set_stall(ep);
1076 	}
1077 
1078 	spin_unlock_irqrestore(&dev->lock, flags);
1079 
1080 	return 0;
1081 }
1082 
1083 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1084 {
1085 	u8 ep_num;
1086 	u32 ep_ctrl = 0, daintmsk = 0;
1087 
1088 	ep_num = ep_index(ep);
1089 
1090 	/* Read DEPCTLn register */
1091 	if (ep_is_in(ep)) {
1092 		ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1093 		daintmsk = 1 << ep_num;
1094 	} else {
1095 		ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1096 		daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1097 	}
1098 
1099 	debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1100 		__func__, ep_num, ep_ctrl, ep_is_in(ep));
1101 
1102 	/* If the EP is already active don't change the EP Control
1103 	 * register. */
1104 	if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1105 		ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1106 			(ep->bmAttributes << DEPCTL_TYPE_BIT);
1107 		ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1108 			(ep->ep.maxpacket << DEPCTL_MPS_BIT);
1109 		ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1110 
1111 		if (ep_is_in(ep)) {
1112 			writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1113 			debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1114 			      __func__, ep_num, ep_num,
1115 			      readl(&reg->in_endp[ep_num].diepctl));
1116 		} else {
1117 			writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1118 			debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1119 			      __func__, ep_num, ep_num,
1120 			      readl(&reg->out_endp[ep_num].doepctl));
1121 		}
1122 	}
1123 
1124 	/* Unmask EP Interrtupt */
1125 	writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1126 	debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1127 
1128 }
1129 
1130 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1131 {
1132 	struct dwc2_udc	*dev;
1133 	struct dwc2_ep	*ep;
1134 	u8		ep_num;
1135 
1136 	ep = container_of(_ep, struct dwc2_ep, ep);
1137 	ep_num = ep_index(ep);
1138 
1139 	dev = ep->dev;
1140 	debug_cond(DEBUG_SETUP != 0,
1141 		   "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1142 		   __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1143 
1144 	if (usb_ctrl->wLength != 0) {
1145 		debug_cond(DEBUG_SETUP != 0,
1146 			   "\tCLEAR_FEATURE: wLength is not zero.....\n");
1147 		return 1;
1148 	}
1149 
1150 	switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1151 	case USB_RECIP_DEVICE:
1152 		switch (usb_ctrl->wValue) {
1153 		case USB_DEVICE_REMOTE_WAKEUP:
1154 			debug_cond(DEBUG_SETUP != 0,
1155 				   "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1156 			break;
1157 
1158 		case USB_DEVICE_TEST_MODE:
1159 			debug_cond(DEBUG_SETUP != 0,
1160 				   "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1161 			/** @todo Add CLEAR_FEATURE for TEST modes. */
1162 			break;
1163 		}
1164 
1165 		dwc2_udc_ep0_zlp(dev);
1166 		break;
1167 
1168 	case USB_RECIP_ENDPOINT:
1169 		debug_cond(DEBUG_SETUP != 0,
1170 			   "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1171 			   usb_ctrl->wValue);
1172 
1173 		if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1174 			if (ep_num == 0) {
1175 				dwc2_udc_ep0_set_stall(ep);
1176 				return 0;
1177 			}
1178 
1179 			dwc2_udc_ep0_zlp(dev);
1180 
1181 			dwc2_udc_ep_clear_stall(ep);
1182 			dwc2_udc_ep_activate(ep);
1183 			ep->stopped = 0;
1184 
1185 			clear_feature_num = ep_num;
1186 			clear_feature_flag = 1;
1187 		}
1188 		break;
1189 	}
1190 
1191 	return 0;
1192 }
1193 
1194 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1195 {
1196 	struct dwc2_udc	*dev;
1197 	struct dwc2_ep	*ep;
1198 	u8		ep_num;
1199 
1200 	ep = container_of(_ep, struct dwc2_ep, ep);
1201 	ep_num = ep_index(ep);
1202 	dev = ep->dev;
1203 
1204 	debug_cond(DEBUG_SETUP != 0,
1205 		   "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1206 		    __func__, ep_num);
1207 
1208 	if (usb_ctrl->wLength != 0) {
1209 		debug_cond(DEBUG_SETUP != 0,
1210 			   "\tSET_FEATURE: wLength is not zero.....\n");
1211 		return 1;
1212 	}
1213 
1214 	switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1215 	case USB_RECIP_DEVICE:
1216 		switch (usb_ctrl->wValue) {
1217 		case USB_DEVICE_REMOTE_WAKEUP:
1218 			debug_cond(DEBUG_SETUP != 0,
1219 				   "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1220 			break;
1221 		case USB_DEVICE_B_HNP_ENABLE:
1222 			debug_cond(DEBUG_SETUP != 0,
1223 				   "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1224 			break;
1225 
1226 		case USB_DEVICE_A_HNP_SUPPORT:
1227 			/* RH port supports HNP */
1228 			debug_cond(DEBUG_SETUP != 0,
1229 				   "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1230 			break;
1231 
1232 		case USB_DEVICE_A_ALT_HNP_SUPPORT:
1233 			/* other RH port does */
1234 			debug_cond(DEBUG_SETUP != 0,
1235 				   "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1236 			break;
1237 		}
1238 
1239 		dwc2_udc_ep0_zlp(dev);
1240 		return 0;
1241 
1242 	case USB_RECIP_INTERFACE:
1243 		debug_cond(DEBUG_SETUP != 0,
1244 			   "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1245 		break;
1246 
1247 	case USB_RECIP_ENDPOINT:
1248 		debug_cond(DEBUG_SETUP != 0,
1249 			   "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1250 		if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1251 			if (ep_num == 0) {
1252 				dwc2_udc_ep0_set_stall(ep);
1253 				return 0;
1254 			}
1255 			ep->stopped = 1;
1256 			dwc2_udc_ep_set_stall(ep);
1257 		}
1258 
1259 		dwc2_udc_ep0_zlp(dev);
1260 		return 0;
1261 	}
1262 
1263 	return 1;
1264 }
1265 
1266 /*
1267  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1268  */
1269 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1270 {
1271 	struct dwc2_ep *ep = &dev->ep[0];
1272 	int i;
1273 	u8 ep_num;
1274 
1275 	/* Nuke all previous transfers */
1276 	nuke(ep, -EPROTO);
1277 
1278 	/* read control req from fifo (8 bytes) */
1279 	dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8);
1280 
1281 	debug_cond(DEBUG_SETUP != 0,
1282 		   "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1283 		   "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1284 		   __func__, usb_ctrl->bRequestType,
1285 		   (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1286 		   usb_ctrl->bRequest,
1287 		   usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1288 
1289 #ifdef DEBUG
1290 	{
1291 		int i, len = sizeof(*usb_ctrl);
1292 		char *p = (char *)usb_ctrl;
1293 
1294 		printf("pkt = ");
1295 		for (i = 0; i < len; i++) {
1296 			printf("%02x", ((u8 *)p)[i]);
1297 			if ((i & 7) == 7)
1298 				printf(" ");
1299 		}
1300 		printf("\n");
1301 	}
1302 #endif
1303 
1304 	if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1305 	    usb_ctrl->wLength != 1) {
1306 		debug_cond(DEBUG_SETUP != 0,
1307 			   "\t%s:GET_MAX_LUN_REQUEST:invalid",
1308 			   __func__);
1309 		debug_cond(DEBUG_SETUP != 0,
1310 			   "wLength = %d, setup returned\n",
1311 			   usb_ctrl->wLength);
1312 
1313 		dwc2_udc_ep0_set_stall(ep);
1314 		dev->ep0state = WAIT_FOR_SETUP;
1315 
1316 		return;
1317 	} else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1318 		 usb_ctrl->wLength != 0) {
1319 		/* Bulk-Only *mass storge reset of class-specific request */
1320 		debug_cond(DEBUG_SETUP != 0,
1321 			   "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1322 			   __func__, usb_ctrl->wLength);
1323 
1324 		dwc2_udc_ep0_set_stall(ep);
1325 		dev->ep0state = WAIT_FOR_SETUP;
1326 
1327 		return;
1328 	}
1329 
1330 	/* Set direction of EP0 */
1331 	if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1332 		ep->bEndpointAddress |= USB_DIR_IN;
1333 	} else {
1334 		ep->bEndpointAddress &= ~USB_DIR_IN;
1335 	}
1336 	/* cope with automagic for some standard requests. */
1337 	dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1338 		== USB_TYPE_STANDARD;
1339 
1340 	dev->req_pending = 1;
1341 
1342 	/* Handle some SETUP packets ourselves */
1343 	if (dev->req_std) {
1344 		switch (usb_ctrl->bRequest) {
1345 		case USB_REQ_SET_ADDRESS:
1346 		debug_cond(DEBUG_SETUP != 0,
1347 			   "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1348 			   __func__, usb_ctrl->wValue);
1349 			if (usb_ctrl->bRequestType
1350 				!= (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1351 				break;
1352 
1353 			udc_set_address(dev, usb_ctrl->wValue);
1354 			return;
1355 
1356 		case USB_REQ_SET_CONFIGURATION:
1357 			debug_cond(DEBUG_SETUP != 0,
1358 				   "=====================================\n");
1359 			debug_cond(DEBUG_SETUP != 0,
1360 				   "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1361 				   __func__, usb_ctrl->wValue);
1362 
1363 			if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1364 				reset_available = 1;
1365 
1366 			break;
1367 
1368 		case USB_REQ_GET_DESCRIPTOR:
1369 			debug_cond(DEBUG_SETUP != 0,
1370 				   "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1371 				   __func__);
1372 			break;
1373 
1374 		case USB_REQ_SET_INTERFACE:
1375 			debug_cond(DEBUG_SETUP != 0,
1376 				   "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1377 				   __func__, usb_ctrl->wValue);
1378 
1379 			if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1380 				reset_available = 1;
1381 
1382 			break;
1383 
1384 		case USB_REQ_GET_CONFIGURATION:
1385 			debug_cond(DEBUG_SETUP != 0,
1386 				   "%s: *** USB_REQ_GET_CONFIGURATION\n",
1387 				   __func__);
1388 			break;
1389 
1390 		case USB_REQ_GET_STATUS:
1391 			if (!dwc2_udc_get_status(dev, usb_ctrl))
1392 				return;
1393 
1394 			break;
1395 
1396 		case USB_REQ_CLEAR_FEATURE:
1397 			ep_num = usb_ctrl->wIndex & 0x7f;
1398 
1399 			if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1400 				return;
1401 
1402 			break;
1403 
1404 		case USB_REQ_SET_FEATURE:
1405 			ep_num = usb_ctrl->wIndex & 0x7f;
1406 
1407 			if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1408 				return;
1409 
1410 			break;
1411 
1412 		default:
1413 			debug_cond(DEBUG_SETUP != 0,
1414 				   "%s: *** Default of usb_ctrl->bRequest=0x%x"
1415 				   "happened.\n", __func__, usb_ctrl->bRequest);
1416 			break;
1417 		}
1418 	}
1419 
1420 
1421 	if (likely(dev->driver)) {
1422 		/* device-2-host (IN) or no data setup command,
1423 		 * process immediately */
1424 		debug_cond(DEBUG_SETUP != 0,
1425 			   "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1426 			    __func__);
1427 
1428 		spin_unlock(&dev->lock);
1429 		i = dev->driver->setup(&dev->gadget, usb_ctrl);
1430 		spin_lock(&dev->lock);
1431 
1432 		if (i < 0) {
1433 			/* setup processing failed, force stall */
1434 			dwc2_udc_ep0_set_stall(ep);
1435 			dev->ep0state = WAIT_FOR_SETUP;
1436 
1437 			debug_cond(DEBUG_SETUP != 0,
1438 				   "\tdev->driver->setup failed (%d),"
1439 				    " bRequest = %d\n",
1440 				i, usb_ctrl->bRequest);
1441 
1442 
1443 		} else if (dev->req_pending) {
1444 			dev->req_pending = 0;
1445 			debug_cond(DEBUG_SETUP != 0,
1446 				   "\tdev->req_pending...\n");
1447 		}
1448 
1449 		debug_cond(DEBUG_SETUP != 0,
1450 			   "\tep0state = %s\n", state_names[dev->ep0state]);
1451 
1452 	}
1453 }
1454 
1455 /*
1456  * handle ep0 interrupt
1457  */
1458 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1459 {
1460 	if (dev->ep0state == WAIT_FOR_SETUP) {
1461 		debug_cond(DEBUG_OUT_EP != 0,
1462 			   "%s: WAIT_FOR_SETUP\n", __func__);
1463 		dwc2_ep0_setup(dev);
1464 
1465 	} else {
1466 		debug_cond(DEBUG_OUT_EP != 0,
1467 			   "%s: strange state!!(state = %s)\n",
1468 			__func__, state_names[dev->ep0state]);
1469 	}
1470 }
1471 
1472 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1473 {
1474 	debug_cond(DEBUG_EP0 != 0,
1475 		   "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1476 	if (ep_is_in(ep)) {
1477 		dev->ep0state = DATA_STATE_XMIT;
1478 		dwc2_ep0_write(dev);
1479 
1480 	} else {
1481 		dev->ep0state = DATA_STATE_RECV;
1482 		dwc2_ep0_read(dev);
1483 	}
1484 }
1485