1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/usb/gadget/dwc2_udc_otg.c 4 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers 5 * 6 * Copyright (C) 2008 for Samsung Electronics 7 * 8 * BSP Support for Samsung's UDC driver 9 * available at: 10 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git 11 * 12 * State machine bugfixes: 13 * Marek Szyprowski <m.szyprowski@samsung.com> 14 * 15 * Ported to u-boot: 16 * Marek Szyprowski <m.szyprowski@samsung.com> 17 * Lukasz Majewski <l.majewski@samsumg.com> 18 */ 19 #undef DEBUG 20 #include <common.h> 21 #include <linux/errno.h> 22 #include <linux/list.h> 23 #include <malloc.h> 24 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 #include <asm/byteorder.h> 29 #include <asm/unaligned.h> 30 #include <asm/io.h> 31 32 #include <asm/mach-types.h> 33 34 #include "dwc2_udc_otg_regs.h" 35 #include "dwc2_udc_otg_priv.h" 36 #include <usb/lin_gadget_compat.h> 37 38 /***********************************************************/ 39 40 #define OTG_DMA_MODE 1 41 42 #define DEBUG_SETUP 0 43 #define DEBUG_EP0 0 44 #define DEBUG_ISR 0 45 #define DEBUG_OUT_EP 0 46 #define DEBUG_IN_EP 0 47 48 #include <usb/dwc2_udc.h> 49 50 #define EP0_CON 0 51 #define EP_MASK 0xF 52 53 static char *state_names[] = { 54 "WAIT_FOR_SETUP", 55 "DATA_STATE_XMIT", 56 "DATA_STATE_NEED_ZLP", 57 "WAIT_FOR_OUT_STATUS", 58 "DATA_STATE_RECV", 59 "WAIT_FOR_COMPLETE", 60 "WAIT_FOR_OUT_COMPLETE", 61 "WAIT_FOR_IN_COMPLETE", 62 "WAIT_FOR_NULL_COMPLETE", 63 }; 64 65 #define DRIVER_VERSION "15 March 2009" 66 67 struct dwc2_udc *the_controller; 68 69 static const char driver_name[] = "dwc2-udc"; 70 static const char ep0name[] = "ep0-control"; 71 72 /* Max packet size*/ 73 static unsigned int ep0_fifo_size = 64; 74 static unsigned int ep_fifo_size = 512; 75 static unsigned int ep_fifo_size2 = 1024; 76 static int reset_available = 1; 77 78 static struct usb_ctrlrequest *usb_ctrl; 79 static dma_addr_t usb_ctrl_dma_addr; 80 81 /* 82 Local declarations. 83 */ 84 static int dwc2_ep_enable(struct usb_ep *ep, 85 const struct usb_endpoint_descriptor *); 86 static int dwc2_ep_disable(struct usb_ep *ep); 87 static struct usb_request *dwc2_alloc_request(struct usb_ep *ep, 88 gfp_t gfp_flags); 89 static void dwc2_free_request(struct usb_ep *ep, struct usb_request *); 90 91 static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags); 92 static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *); 93 static int dwc2_fifo_status(struct usb_ep *ep); 94 static void dwc2_fifo_flush(struct usb_ep *ep); 95 static void dwc2_ep0_read(struct dwc2_udc *dev); 96 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep); 97 static void dwc2_handle_ep0(struct dwc2_udc *dev); 98 static int dwc2_ep0_write(struct dwc2_udc *dev); 99 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req); 100 static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status); 101 static void stop_activity(struct dwc2_udc *dev, 102 struct usb_gadget_driver *driver); 103 static int udc_enable(struct dwc2_udc *dev); 104 static void udc_set_address(struct dwc2_udc *dev, unsigned char address); 105 static void reconfig_usbd(struct dwc2_udc *dev); 106 static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed); 107 static void nuke(struct dwc2_ep *ep, int status); 108 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value); 109 static void dwc2_udc_set_nak(struct dwc2_ep *ep); 110 111 void set_udc_gadget_private_data(void *p) 112 { 113 debug_cond(DEBUG_SETUP != 0, 114 "%s: the_controller: 0x%p, p: 0x%p\n", __func__, 115 the_controller, p); 116 the_controller->gadget.dev.device_data = p; 117 } 118 119 void *get_udc_gadget_private_data(struct usb_gadget *gadget) 120 { 121 return gadget->dev.device_data; 122 } 123 124 static struct usb_ep_ops dwc2_ep_ops = { 125 .enable = dwc2_ep_enable, 126 .disable = dwc2_ep_disable, 127 128 .alloc_request = dwc2_alloc_request, 129 .free_request = dwc2_free_request, 130 131 .queue = dwc2_queue, 132 .dequeue = dwc2_dequeue, 133 134 .set_halt = dwc2_udc_set_halt, 135 .fifo_status = dwc2_fifo_status, 136 .fifo_flush = dwc2_fifo_flush, 137 }; 138 139 #define create_proc_files() do {} while (0) 140 #define remove_proc_files() do {} while (0) 141 142 /***********************************************************/ 143 144 void __iomem *regs_otg; 145 struct dwc2_usbotg_reg *reg; 146 147 bool dfu_usb_get_reset(void) 148 { 149 return !!(readl(®->gintsts) & INT_RESET); 150 } 151 152 __weak void otg_phy_init(struct dwc2_udc *dev) {} 153 __weak void otg_phy_off(struct dwc2_udc *dev) {} 154 155 /***********************************************************/ 156 157 #include "dwc2_udc_otg_xfer_dma.c" 158 159 /* 160 * udc_disable - disable USB device controller 161 */ 162 static void udc_disable(struct dwc2_udc *dev) 163 { 164 debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); 165 166 udc_set_address(dev, 0); 167 168 dev->ep0state = WAIT_FOR_SETUP; 169 dev->gadget.speed = USB_SPEED_UNKNOWN; 170 dev->usb_address = 0; 171 172 otg_phy_off(dev); 173 } 174 175 /* 176 * udc_reinit - initialize software state 177 */ 178 static void udc_reinit(struct dwc2_udc *dev) 179 { 180 unsigned int i; 181 182 debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); 183 184 /* device/ep0 records init */ 185 INIT_LIST_HEAD(&dev->gadget.ep_list); 186 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 187 dev->ep0state = WAIT_FOR_SETUP; 188 189 /* basic endpoint records init */ 190 for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) { 191 struct dwc2_ep *ep = &dev->ep[i]; 192 193 if (i != 0) 194 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); 195 196 ep->desc = 0; 197 ep->stopped = 0; 198 INIT_LIST_HEAD(&ep->queue); 199 ep->pio_irqs = 0; 200 } 201 202 /* the rest was statically initialized, and is read-only */ 203 } 204 205 #define BYTES2MAXP(x) (x / 8) 206 #define MAXP2BYTES(x) (x * 8) 207 208 /* until it's enabled, this UDC should be completely invisible 209 * to any USB host. 210 */ 211 static int udc_enable(struct dwc2_udc *dev) 212 { 213 debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); 214 215 otg_phy_init(dev); 216 reconfig_usbd(dev); 217 218 debug_cond(DEBUG_SETUP != 0, 219 "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n", 220 readl(®->gintmsk)); 221 222 dev->gadget.speed = USB_SPEED_UNKNOWN; 223 224 return 0; 225 } 226 227 /* 228 Register entry point for the peripheral controller driver. 229 */ 230 int usb_gadget_register_driver(struct usb_gadget_driver *driver) 231 { 232 struct dwc2_udc *dev = the_controller; 233 int retval = 0; 234 unsigned long flags = 0; 235 236 debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name"); 237 238 if (!driver 239 || (driver->speed != USB_SPEED_FULL 240 && driver->speed != USB_SPEED_HIGH) 241 || !driver->bind || !driver->disconnect || !driver->setup) 242 return -EINVAL; 243 if (!dev) 244 return -ENODEV; 245 if (dev->driver) 246 return -EBUSY; 247 248 spin_lock_irqsave(&dev->lock, flags); 249 /* first hook up the driver ... */ 250 dev->driver = driver; 251 spin_unlock_irqrestore(&dev->lock, flags); 252 253 if (retval) { /* TODO */ 254 printf("target device_add failed, error %d\n", retval); 255 return retval; 256 } 257 258 retval = driver->bind(&dev->gadget); 259 if (retval) { 260 debug_cond(DEBUG_SETUP != 0, 261 "%s: bind to driver --> error %d\n", 262 dev->gadget.name, retval); 263 dev->driver = 0; 264 return retval; 265 } 266 267 enable_irq(IRQ_OTG); 268 269 debug_cond(DEBUG_SETUP != 0, 270 "Registered gadget driver %s\n", dev->gadget.name); 271 udc_enable(dev); 272 273 return 0; 274 } 275 276 /* 277 * Unregister entry point for the peripheral controller driver. 278 */ 279 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 280 { 281 struct dwc2_udc *dev = the_controller; 282 unsigned long flags = 0; 283 284 if (!dev) 285 return -ENODEV; 286 if (!driver || driver != dev->driver) 287 return -EINVAL; 288 289 spin_lock_irqsave(&dev->lock, flags); 290 dev->driver = 0; 291 stop_activity(dev, driver); 292 spin_unlock_irqrestore(&dev->lock, flags); 293 294 driver->unbind(&dev->gadget); 295 296 disable_irq(IRQ_OTG); 297 298 udc_disable(dev); 299 return 0; 300 } 301 302 /* 303 * done - retire a request; caller blocked irqs 304 */ 305 static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status) 306 { 307 unsigned int stopped = ep->stopped; 308 309 debug("%s: %s %p, req = %p, stopped = %d\n", 310 __func__, ep->ep.name, ep, &req->req, stopped); 311 312 list_del_init(&req->queue); 313 314 if (likely(req->req.status == -EINPROGRESS)) 315 req->req.status = status; 316 else 317 status = req->req.status; 318 319 if (status && status != -ESHUTDOWN) { 320 debug("complete %s req %p stat %d len %u/%u\n", 321 ep->ep.name, &req->req, status, 322 req->req.actual, req->req.length); 323 } 324 325 /* don't modify queue heads during completion callback */ 326 ep->stopped = 1; 327 328 #ifdef DEBUG 329 printf("calling complete callback\n"); 330 { 331 int i, len = req->req.length; 332 333 printf("pkt[%d] = ", req->req.length); 334 if (len > 64) 335 len = 64; 336 for (i = 0; i < len; i++) { 337 printf("%02x", ((u8 *)req->req.buf)[i]); 338 if ((i & 7) == 7) 339 printf(" "); 340 } 341 printf("\n"); 342 } 343 #endif 344 spin_unlock(&ep->dev->lock); 345 req->req.complete(&ep->ep, &req->req); 346 spin_lock(&ep->dev->lock); 347 348 debug("callback completed\n"); 349 350 ep->stopped = stopped; 351 } 352 353 /* 354 * nuke - dequeue ALL requests 355 */ 356 static void nuke(struct dwc2_ep *ep, int status) 357 { 358 struct dwc2_request *req; 359 360 debug("%s: %s %p\n", __func__, ep->ep.name, ep); 361 362 /* called with irqs blocked */ 363 while (!list_empty(&ep->queue)) { 364 req = list_entry(ep->queue.next, struct dwc2_request, queue); 365 done(ep, req, status); 366 } 367 } 368 369 static void stop_activity(struct dwc2_udc *dev, 370 struct usb_gadget_driver *driver) 371 { 372 int i; 373 374 /* don't disconnect drivers more than once */ 375 if (dev->gadget.speed == USB_SPEED_UNKNOWN) 376 driver = 0; 377 dev->gadget.speed = USB_SPEED_UNKNOWN; 378 379 /* prevent new request submissions, kill any outstanding requests */ 380 for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) { 381 struct dwc2_ep *ep = &dev->ep[i]; 382 ep->stopped = 1; 383 nuke(ep, -ESHUTDOWN); 384 } 385 386 /* report disconnect; the driver is already quiesced */ 387 if (driver) { 388 spin_unlock(&dev->lock); 389 driver->disconnect(&dev->gadget); 390 spin_lock(&dev->lock); 391 } 392 393 /* re-init driver-visible data structures */ 394 udc_reinit(dev); 395 } 396 397 static void reconfig_usbd(struct dwc2_udc *dev) 398 { 399 /* 2. Soft-reset OTG Core and then unreset again. */ 400 int i; 401 unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); 402 uint32_t dflt_gusbcfg; 403 uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz; 404 405 debug("Reseting OTG controller\n"); 406 407 dflt_gusbcfg = 408 0<<15 /* PHY Low Power Clock sel*/ 409 |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/ 410 |0x5<<10 /* Turnaround time*/ 411 |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/ 412 /* 1:SRP enable] H1= 1,1*/ 413 |0<<7 /* Ulpi DDR sel*/ 414 |0<<6 /* 0: high speed utmi+, 1: full speed serial*/ 415 |0<<4 /* 0: utmi+, 1:ulpi*/ 416 #ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 417 |0<<3 /* phy i/f 0:8bit, 1:16bit*/ 418 #else 419 |1<<3 /* phy i/f 0:8bit, 1:16bit*/ 420 #endif 421 |0x7<<0; /* HS/FS Timeout**/ 422 423 if (dev->pdata->usb_gusbcfg) 424 dflt_gusbcfg = dev->pdata->usb_gusbcfg; 425 426 writel(dflt_gusbcfg, ®->gusbcfg); 427 428 /* 3. Put the OTG device core in the disconnected state.*/ 429 uTemp = readl(®->dctl); 430 uTemp |= SOFT_DISCONNECT; 431 writel(uTemp, ®->dctl); 432 433 udelay(20); 434 435 /* 4. Make the OTG device core exit from the disconnected state.*/ 436 uTemp = readl(®->dctl); 437 uTemp = uTemp & ~SOFT_DISCONNECT; 438 writel(uTemp, ®->dctl); 439 440 /* 5. Configure OTG Core to initial settings of device mode.*/ 441 /* [][1: full speed(30Mhz) 0:high speed]*/ 442 writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, ®->dcfg); 443 444 mdelay(1); 445 446 /* 6. Unmask the core interrupts*/ 447 writel(GINTMSK_INIT, ®->gintmsk); 448 449 /* 7. Set NAK bit of EP0, EP1, EP2*/ 450 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[EP0_CON].doepctl); 451 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[EP0_CON].diepctl); 452 453 for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) { 454 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[i].doepctl); 455 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[i].diepctl); 456 } 457 458 /* 8. Unmask EPO interrupts*/ 459 writel(((1 << EP0_CON) << DAINT_OUT_BIT) 460 | (1 << EP0_CON), ®->daintmsk); 461 462 /* 9. Unmask device OUT EP common interrupts*/ 463 writel(DOEPMSK_INIT, ®->doepmsk); 464 465 /* 10. Unmask device IN EP common interrupts*/ 466 writel(DIEPMSK_INIT, ®->diepmsk); 467 468 rx_fifo_sz = RX_FIFO_SIZE; 469 np_tx_fifo_sz = NPTX_FIFO_SIZE; 470 tx_fifo_sz = PTX_FIFO_SIZE; 471 472 if (dev->pdata->rx_fifo_sz) 473 rx_fifo_sz = dev->pdata->rx_fifo_sz; 474 if (dev->pdata->np_tx_fifo_sz) 475 np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz; 476 if (dev->pdata->tx_fifo_sz) 477 tx_fifo_sz = dev->pdata->tx_fifo_sz; 478 479 /* 11. Set Rx FIFO Size (in 32-bit words) */ 480 writel(rx_fifo_sz, ®->grxfsiz); 481 482 /* 12. Set Non Periodic Tx FIFO Size */ 483 writel((np_tx_fifo_sz << 16) | rx_fifo_sz, 484 ®->gnptxfsiz); 485 486 for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++) 487 writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) | 488 tx_fifo_sz << 16, ®->dieptxf[i-1]); 489 490 /* Flush the RX FIFO */ 491 writel(RX_FIFO_FLUSH, ®->grstctl); 492 while (readl(®->grstctl) & RX_FIFO_FLUSH) 493 debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__); 494 495 /* Flush all the Tx FIFO's */ 496 writel(TX_FIFO_FLUSH_ALL, ®->grstctl); 497 writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, ®->grstctl); 498 while (readl(®->grstctl) & TX_FIFO_FLUSH) 499 debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__); 500 501 /* 13. Clear NAK bit of EP0, EP1, EP2*/ 502 /* For Slave mode*/ 503 /* EP0: Control OUT */ 504 writel(DEPCTL_EPDIS | DEPCTL_CNAK, 505 ®->out_endp[EP0_CON].doepctl); 506 507 /* 14. Initialize OTG Link Core.*/ 508 writel(GAHBCFG_INIT, ®->gahbcfg); 509 } 510 511 static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed) 512 { 513 unsigned int ep_ctrl; 514 int i; 515 516 if (speed == USB_SPEED_HIGH) { 517 ep0_fifo_size = 64; 518 ep_fifo_size = 512; 519 ep_fifo_size2 = 1024; 520 dev->gadget.speed = USB_SPEED_HIGH; 521 } else { 522 ep0_fifo_size = 64; 523 ep_fifo_size = 64; 524 ep_fifo_size2 = 64; 525 dev->gadget.speed = USB_SPEED_FULL; 526 } 527 528 dev->ep[0].ep.maxpacket = ep0_fifo_size; 529 for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) 530 dev->ep[i].ep.maxpacket = ep_fifo_size; 531 532 /* EP0 - Control IN (64 bytes)*/ 533 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 534 writel(ep_ctrl|(0<<0), ®->in_endp[EP0_CON].diepctl); 535 536 /* EP0 - Control OUT (64 bytes)*/ 537 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); 538 writel(ep_ctrl|(0<<0), ®->out_endp[EP0_CON].doepctl); 539 } 540 541 static int dwc2_ep_enable(struct usb_ep *_ep, 542 const struct usb_endpoint_descriptor *desc) 543 { 544 struct dwc2_ep *ep; 545 struct dwc2_udc *dev; 546 unsigned long flags = 0; 547 548 debug("%s: %p\n", __func__, _ep); 549 550 ep = container_of(_ep, struct dwc2_ep, ep); 551 if (!_ep || !desc || ep->desc || _ep->name == ep0name 552 || desc->bDescriptorType != USB_DT_ENDPOINT 553 || ep->bEndpointAddress != desc->bEndpointAddress 554 || ep_maxpacket(ep) < 555 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) { 556 557 debug("%s: bad ep or descriptor\n", __func__); 558 return -EINVAL; 559 } 560 561 /* xfer types must match, except that interrupt ~= bulk */ 562 if (ep->bmAttributes != desc->bmAttributes 563 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 564 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 565 566 debug("%s: %s type mismatch\n", __func__, _ep->name); 567 return -EINVAL; 568 } 569 570 /* hardware _could_ do smaller, but driver doesn't */ 571 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK && 572 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) > 573 ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) { 574 575 debug("%s: bad %s maxpacket\n", __func__, _ep->name); 576 return -ERANGE; 577 } 578 579 dev = ep->dev; 580 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { 581 582 debug("%s: bogus device state\n", __func__); 583 return -ESHUTDOWN; 584 } 585 586 ep->stopped = 0; 587 ep->desc = desc; 588 ep->pio_irqs = 0; 589 ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)); 590 591 /* Reset halt state */ 592 dwc2_udc_set_nak(ep); 593 dwc2_udc_set_halt(_ep, 0); 594 595 spin_lock_irqsave(&ep->dev->lock, flags); 596 dwc2_udc_ep_activate(ep); 597 spin_unlock_irqrestore(&ep->dev->lock, flags); 598 599 debug("%s: enabled %s, stopped = %d, maxpacket = %d\n", 600 __func__, _ep->name, ep->stopped, ep->ep.maxpacket); 601 return 0; 602 } 603 604 /* 605 * Disable EP 606 */ 607 static int dwc2_ep_disable(struct usb_ep *_ep) 608 { 609 struct dwc2_ep *ep; 610 unsigned long flags = 0; 611 612 debug("%s: %p\n", __func__, _ep); 613 614 ep = container_of(_ep, struct dwc2_ep, ep); 615 if (!_ep || !ep->desc) { 616 debug("%s: %s not enabled\n", __func__, 617 _ep ? ep->ep.name : NULL); 618 return -EINVAL; 619 } 620 621 spin_lock_irqsave(&ep->dev->lock, flags); 622 623 /* Nuke all pending requests */ 624 nuke(ep, -ESHUTDOWN); 625 626 ep->desc = 0; 627 ep->stopped = 1; 628 629 spin_unlock_irqrestore(&ep->dev->lock, flags); 630 631 debug("%s: disabled %s\n", __func__, _ep->name); 632 return 0; 633 } 634 635 static struct usb_request *dwc2_alloc_request(struct usb_ep *ep, 636 gfp_t gfp_flags) 637 { 638 struct dwc2_request *req; 639 640 debug("%s: %s %p\n", __func__, ep->name, ep); 641 642 req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req)); 643 if (!req) 644 return 0; 645 646 memset(req, 0, sizeof *req); 647 INIT_LIST_HEAD(&req->queue); 648 649 return &req->req; 650 } 651 652 static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req) 653 { 654 struct dwc2_request *req; 655 656 debug("%s: %p\n", __func__, ep); 657 658 req = container_of(_req, struct dwc2_request, req); 659 WARN_ON(!list_empty(&req->queue)); 660 kfree(req); 661 } 662 663 /* dequeue JUST ONE request */ 664 static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req) 665 { 666 struct dwc2_ep *ep; 667 struct dwc2_request *req; 668 unsigned long flags = 0; 669 670 debug("%s: %p\n", __func__, _ep); 671 672 ep = container_of(_ep, struct dwc2_ep, ep); 673 if (!_ep || ep->ep.name == ep0name) 674 return -EINVAL; 675 676 spin_lock_irqsave(&ep->dev->lock, flags); 677 678 /* make sure it's actually queued on this endpoint */ 679 list_for_each_entry(req, &ep->queue, queue) { 680 if (&req->req == _req) 681 break; 682 } 683 if (&req->req != _req) { 684 spin_unlock_irqrestore(&ep->dev->lock, flags); 685 return -EINVAL; 686 } 687 688 done(ep, req, -ECONNRESET); 689 690 spin_unlock_irqrestore(&ep->dev->lock, flags); 691 return 0; 692 } 693 694 /* 695 * Return bytes in EP FIFO 696 */ 697 static int dwc2_fifo_status(struct usb_ep *_ep) 698 { 699 int count = 0; 700 struct dwc2_ep *ep; 701 702 ep = container_of(_ep, struct dwc2_ep, ep); 703 if (!_ep) { 704 debug("%s: bad ep\n", __func__); 705 return -ENODEV; 706 } 707 708 debug("%s: %d\n", __func__, ep_index(ep)); 709 710 /* LPD can't report unclaimed bytes from IN fifos */ 711 if (ep_is_in(ep)) 712 return -EOPNOTSUPP; 713 714 return count; 715 } 716 717 /* 718 * Flush EP FIFO 719 */ 720 static void dwc2_fifo_flush(struct usb_ep *_ep) 721 { 722 struct dwc2_ep *ep; 723 724 ep = container_of(_ep, struct dwc2_ep, ep); 725 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { 726 debug("%s: bad ep\n", __func__); 727 return; 728 } 729 730 debug("%s: %d\n", __func__, ep_index(ep)); 731 } 732 733 static const struct usb_gadget_ops dwc2_udc_ops = { 734 /* current versions must always be self-powered */ 735 }; 736 737 static struct dwc2_udc memory = { 738 .usb_address = 0, 739 .gadget = { 740 .ops = &dwc2_udc_ops, 741 .ep0 = &memory.ep[0].ep, 742 .name = driver_name, 743 }, 744 745 /* control endpoint */ 746 .ep[0] = { 747 .ep = { 748 .name = ep0name, 749 .ops = &dwc2_ep_ops, 750 .maxpacket = EP0_FIFO_SIZE, 751 }, 752 .dev = &memory, 753 754 .bEndpointAddress = 0, 755 .bmAttributes = 0, 756 757 .ep_type = ep_control, 758 }, 759 760 /* first group of endpoints */ 761 .ep[1] = { 762 .ep = { 763 .name = "ep1in-bulk", 764 .ops = &dwc2_ep_ops, 765 .maxpacket = EP_FIFO_SIZE, 766 }, 767 .dev = &memory, 768 769 .bEndpointAddress = USB_DIR_IN | 1, 770 .bmAttributes = USB_ENDPOINT_XFER_BULK, 771 772 .ep_type = ep_bulk_out, 773 .fifo_num = 1, 774 }, 775 776 .ep[2] = { 777 .ep = { 778 .name = "ep2out-bulk", 779 .ops = &dwc2_ep_ops, 780 .maxpacket = EP_FIFO_SIZE, 781 }, 782 .dev = &memory, 783 784 .bEndpointAddress = USB_DIR_OUT | 2, 785 .bmAttributes = USB_ENDPOINT_XFER_BULK, 786 787 .ep_type = ep_bulk_in, 788 .fifo_num = 2, 789 }, 790 791 .ep[3] = { 792 .ep = { 793 .name = "ep3in-int", 794 .ops = &dwc2_ep_ops, 795 .maxpacket = EP_FIFO_SIZE, 796 }, 797 .dev = &memory, 798 799 .bEndpointAddress = USB_DIR_IN | 3, 800 .bmAttributes = USB_ENDPOINT_XFER_INT, 801 802 .ep_type = ep_interrupt, 803 .fifo_num = 3, 804 }, 805 }; 806 807 /* 808 * probe - binds to the platform device 809 */ 810 811 int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata) 812 { 813 struct dwc2_udc *dev = &memory; 814 int retval = 0; 815 816 debug("%s: %p\n", __func__, pdata); 817 818 dev->pdata = pdata; 819 820 reg = (struct dwc2_usbotg_reg *)pdata->regs_otg; 821 822 /* regs_otg = (void *)pdata->regs_otg; */ 823 824 dev->gadget.is_dualspeed = 1; /* Hack only*/ 825 dev->gadget.is_otg = 0; 826 dev->gadget.is_a_peripheral = 0; 827 dev->gadget.b_hnp_enable = 0; 828 dev->gadget.a_hnp_support = 0; 829 dev->gadget.a_alt_hnp_support = 0; 830 831 the_controller = dev; 832 833 usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE, 834 ROUND(sizeof(struct usb_ctrlrequest), 835 CONFIG_SYS_CACHELINE_SIZE)); 836 if (!usb_ctrl) { 837 pr_err("No memory available for UDC!\n"); 838 return -ENOMEM; 839 } 840 841 usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl; 842 843 udc_reinit(dev); 844 845 return retval; 846 } 847 848 int usb_gadget_handle_interrupts(int index) 849 { 850 u32 intr_status = readl(®->gintsts); 851 u32 gintmsk = readl(®->gintmsk); 852 853 if (intr_status & gintmsk) 854 return dwc2_udc_irq(1, (void *)the_controller); 855 return 0; 856 } 857