1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * drivers/usb/gadget/dwc2_udc_otg.c
4  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
5  *
6  * Copyright (C) 2008 for Samsung Electronics
7  *
8  * BSP Support for Samsung's UDC driver
9  * available at:
10  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11  *
12  * State machine bugfixes:
13  * Marek Szyprowski <m.szyprowski@samsung.com>
14  *
15  * Ported to u-boot:
16  * Marek Szyprowski <m.szyprowski@samsung.com>
17  * Lukasz Majewski <l.majewski@samsumg.com>
18  */
19 #undef DEBUG
20 #include <common.h>
21 #include <linux/errno.h>
22 #include <linux/list.h>
23 #include <malloc.h>
24 
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27 
28 #include <asm/byteorder.h>
29 #include <asm/unaligned.h>
30 #include <asm/io.h>
31 
32 #include <asm/mach-types.h>
33 
34 #include "dwc2_udc_otg_regs.h"
35 #include "dwc2_udc_otg_priv.h"
36 
37 /***********************************************************/
38 
39 #define OTG_DMA_MODE		1
40 
41 #define DEBUG_SETUP 0
42 #define DEBUG_EP0 0
43 #define DEBUG_ISR 0
44 #define DEBUG_OUT_EP 0
45 #define DEBUG_IN_EP 0
46 
47 #include <usb/dwc2_udc.h>
48 
49 #define EP0_CON		0
50 #define EP_MASK		0xF
51 
52 static char *state_names[] = {
53 	"WAIT_FOR_SETUP",
54 	"DATA_STATE_XMIT",
55 	"DATA_STATE_NEED_ZLP",
56 	"WAIT_FOR_OUT_STATUS",
57 	"DATA_STATE_RECV",
58 	"WAIT_FOR_COMPLETE",
59 	"WAIT_FOR_OUT_COMPLETE",
60 	"WAIT_FOR_IN_COMPLETE",
61 	"WAIT_FOR_NULL_COMPLETE",
62 };
63 
64 #define DRIVER_VERSION "15 March 2009"
65 
66 struct dwc2_udc	*the_controller;
67 
68 static const char driver_name[] = "dwc2-udc";
69 static const char ep0name[] = "ep0-control";
70 
71 /* Max packet size*/
72 static unsigned int ep0_fifo_size = 64;
73 static unsigned int ep_fifo_size =  512;
74 static unsigned int ep_fifo_size2 = 1024;
75 static int reset_available = 1;
76 
77 static struct usb_ctrlrequest *usb_ctrl;
78 static dma_addr_t usb_ctrl_dma_addr;
79 
80 /*
81   Local declarations.
82 */
83 static int dwc2_ep_enable(struct usb_ep *ep,
84 			 const struct usb_endpoint_descriptor *);
85 static int dwc2_ep_disable(struct usb_ep *ep);
86 static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
87 					     gfp_t gfp_flags);
88 static void dwc2_free_request(struct usb_ep *ep, struct usb_request *);
89 
90 static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
91 static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *);
92 static int dwc2_fifo_status(struct usb_ep *ep);
93 static void dwc2_fifo_flush(struct usb_ep *ep);
94 static void dwc2_ep0_read(struct dwc2_udc *dev);
95 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep);
96 static void dwc2_handle_ep0(struct dwc2_udc *dev);
97 static int dwc2_ep0_write(struct dwc2_udc *dev);
98 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req);
99 static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status);
100 static void stop_activity(struct dwc2_udc *dev,
101 			  struct usb_gadget_driver *driver);
102 static int udc_enable(struct dwc2_udc *dev);
103 static void udc_set_address(struct dwc2_udc *dev, unsigned char address);
104 static void reconfig_usbd(struct dwc2_udc *dev);
105 static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed);
106 static void nuke(struct dwc2_ep *ep, int status);
107 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value);
108 static void dwc2_udc_set_nak(struct dwc2_ep *ep);
109 
110 void set_udc_gadget_private_data(void *p)
111 {
112 	debug_cond(DEBUG_SETUP != 0,
113 		   "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
114 		   the_controller, p);
115 	the_controller->gadget.dev.device_data = p;
116 }
117 
118 void *get_udc_gadget_private_data(struct usb_gadget *gadget)
119 {
120 	return gadget->dev.device_data;
121 }
122 
123 static struct usb_ep_ops dwc2_ep_ops = {
124 	.enable = dwc2_ep_enable,
125 	.disable = dwc2_ep_disable,
126 
127 	.alloc_request = dwc2_alloc_request,
128 	.free_request = dwc2_free_request,
129 
130 	.queue = dwc2_queue,
131 	.dequeue = dwc2_dequeue,
132 
133 	.set_halt = dwc2_udc_set_halt,
134 	.fifo_status = dwc2_fifo_status,
135 	.fifo_flush = dwc2_fifo_flush,
136 };
137 
138 #define create_proc_files() do {} while (0)
139 #define remove_proc_files() do {} while (0)
140 
141 /***********************************************************/
142 
143 void __iomem		*regs_otg;
144 struct dwc2_usbotg_reg *reg;
145 
146 bool dfu_usb_get_reset(void)
147 {
148 	return !!(readl(&reg->gintsts) & INT_RESET);
149 }
150 
151 __weak void otg_phy_init(struct dwc2_udc *dev) {}
152 __weak void otg_phy_off(struct dwc2_udc *dev) {}
153 
154 /***********************************************************/
155 
156 #include "dwc2_udc_otg_xfer_dma.c"
157 
158 /*
159  *	udc_disable - disable USB device controller
160  */
161 static void udc_disable(struct dwc2_udc *dev)
162 {
163 	debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
164 
165 	udc_set_address(dev, 0);
166 
167 	dev->ep0state = WAIT_FOR_SETUP;
168 	dev->gadget.speed = USB_SPEED_UNKNOWN;
169 	dev->usb_address = 0;
170 
171 	otg_phy_off(dev);
172 }
173 
174 /*
175  *	udc_reinit - initialize software state
176  */
177 static void udc_reinit(struct dwc2_udc *dev)
178 {
179 	unsigned int i;
180 
181 	debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
182 
183 	/* device/ep0 records init */
184 	INIT_LIST_HEAD(&dev->gadget.ep_list);
185 	INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
186 	dev->ep0state = WAIT_FOR_SETUP;
187 
188 	/* basic endpoint records init */
189 	for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
190 		struct dwc2_ep *ep = &dev->ep[i];
191 
192 		if (i != 0)
193 			list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
194 
195 		ep->desc = 0;
196 		ep->stopped = 0;
197 		INIT_LIST_HEAD(&ep->queue);
198 		ep->pio_irqs = 0;
199 	}
200 
201 	/* the rest was statically initialized, and is read-only */
202 }
203 
204 #define BYTES2MAXP(x)	(x / 8)
205 #define MAXP2BYTES(x)	(x * 8)
206 
207 /* until it's enabled, this UDC should be completely invisible
208  * to any USB host.
209  */
210 static int udc_enable(struct dwc2_udc *dev)
211 {
212 	debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
213 
214 	otg_phy_init(dev);
215 	reconfig_usbd(dev);
216 
217 	debug_cond(DEBUG_SETUP != 0,
218 		   "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n",
219 		    readl(&reg->gintmsk));
220 
221 	dev->gadget.speed = USB_SPEED_UNKNOWN;
222 
223 	return 0;
224 }
225 
226 /*
227   Register entry point for the peripheral controller driver.
228 */
229 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
230 {
231 	struct dwc2_udc *dev = the_controller;
232 	int retval = 0;
233 	unsigned long flags = 0;
234 
235 	debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
236 
237 	if (!driver
238 	    || (driver->speed != USB_SPEED_FULL
239 		&& driver->speed != USB_SPEED_HIGH)
240 	    || !driver->bind || !driver->disconnect || !driver->setup)
241 		return -EINVAL;
242 	if (!dev)
243 		return -ENODEV;
244 	if (dev->driver)
245 		return -EBUSY;
246 
247 	spin_lock_irqsave(&dev->lock, flags);
248 	/* first hook up the driver ... */
249 	dev->driver = driver;
250 	spin_unlock_irqrestore(&dev->lock, flags);
251 
252 	if (retval) { /* TODO */
253 		printf("target device_add failed, error %d\n", retval);
254 		return retval;
255 	}
256 
257 	retval = driver->bind(&dev->gadget);
258 	if (retval) {
259 		debug_cond(DEBUG_SETUP != 0,
260 			   "%s: bind to driver --> error %d\n",
261 			    dev->gadget.name, retval);
262 		dev->driver = 0;
263 		return retval;
264 	}
265 
266 	enable_irq(IRQ_OTG);
267 
268 	debug_cond(DEBUG_SETUP != 0,
269 		   "Registered gadget driver %s\n", dev->gadget.name);
270 	udc_enable(dev);
271 
272 	return 0;
273 }
274 
275 /*
276  * Unregister entry point for the peripheral controller driver.
277  */
278 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
279 {
280 	struct dwc2_udc *dev = the_controller;
281 	unsigned long flags = 0;
282 
283 	if (!dev)
284 		return -ENODEV;
285 	if (!driver || driver != dev->driver)
286 		return -EINVAL;
287 
288 	spin_lock_irqsave(&dev->lock, flags);
289 	dev->driver = 0;
290 	stop_activity(dev, driver);
291 	spin_unlock_irqrestore(&dev->lock, flags);
292 
293 	driver->unbind(&dev->gadget);
294 
295 	disable_irq(IRQ_OTG);
296 
297 	udc_disable(dev);
298 	return 0;
299 }
300 
301 /*
302  *	done - retire a request; caller blocked irqs
303  */
304 static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status)
305 {
306 	unsigned int stopped = ep->stopped;
307 
308 	debug("%s: %s %p, req = %p, stopped = %d\n",
309 	      __func__, ep->ep.name, ep, &req->req, stopped);
310 
311 	list_del_init(&req->queue);
312 
313 	if (likely(req->req.status == -EINPROGRESS))
314 		req->req.status = status;
315 	else
316 		status = req->req.status;
317 
318 	if (status && status != -ESHUTDOWN) {
319 		debug("complete %s req %p stat %d len %u/%u\n",
320 		      ep->ep.name, &req->req, status,
321 		      req->req.actual, req->req.length);
322 	}
323 
324 	/* don't modify queue heads during completion callback */
325 	ep->stopped = 1;
326 
327 #ifdef DEBUG
328 	printf("calling complete callback\n");
329 	{
330 		int i, len = req->req.length;
331 
332 		printf("pkt[%d] = ", req->req.length);
333 		if (len > 64)
334 			len = 64;
335 		for (i = 0; i < len; i++) {
336 			printf("%02x", ((u8 *)req->req.buf)[i]);
337 			if ((i & 7) == 7)
338 				printf(" ");
339 		}
340 		printf("\n");
341 	}
342 #endif
343 	spin_unlock(&ep->dev->lock);
344 	req->req.complete(&ep->ep, &req->req);
345 	spin_lock(&ep->dev->lock);
346 
347 	debug("callback completed\n");
348 
349 	ep->stopped = stopped;
350 }
351 
352 /*
353  *	nuke - dequeue ALL requests
354  */
355 static void nuke(struct dwc2_ep *ep, int status)
356 {
357 	struct dwc2_request *req;
358 
359 	debug("%s: %s %p\n", __func__, ep->ep.name, ep);
360 
361 	/* called with irqs blocked */
362 	while (!list_empty(&ep->queue)) {
363 		req = list_entry(ep->queue.next, struct dwc2_request, queue);
364 		done(ep, req, status);
365 	}
366 }
367 
368 static void stop_activity(struct dwc2_udc *dev,
369 			  struct usb_gadget_driver *driver)
370 {
371 	int i;
372 
373 	/* don't disconnect drivers more than once */
374 	if (dev->gadget.speed == USB_SPEED_UNKNOWN)
375 		driver = 0;
376 	dev->gadget.speed = USB_SPEED_UNKNOWN;
377 
378 	/* prevent new request submissions, kill any outstanding requests  */
379 	for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
380 		struct dwc2_ep *ep = &dev->ep[i];
381 		ep->stopped = 1;
382 		nuke(ep, -ESHUTDOWN);
383 	}
384 
385 	/* report disconnect; the driver is already quiesced */
386 	if (driver) {
387 		spin_unlock(&dev->lock);
388 		driver->disconnect(&dev->gadget);
389 		spin_lock(&dev->lock);
390 	}
391 
392 	/* re-init driver-visible data structures */
393 	udc_reinit(dev);
394 }
395 
396 static void reconfig_usbd(struct dwc2_udc *dev)
397 {
398 	/* 2. Soft-reset OTG Core and then unreset again. */
399 	int i;
400 	unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
401 	uint32_t dflt_gusbcfg;
402 	uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
403 
404 	debug("Reseting OTG controller\n");
405 
406 	dflt_gusbcfg =
407 		0<<15		/* PHY Low Power Clock sel*/
408 		|1<<14		/* Non-Periodic TxFIFO Rewind Enable*/
409 		|0x5<<10	/* Turnaround time*/
410 		|0<<9 | 0<<8	/* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
411 				/* 1:SRP enable] H1= 1,1*/
412 		|0<<7		/* Ulpi DDR sel*/
413 		|0<<6		/* 0: high speed utmi+, 1: full speed serial*/
414 		|0<<4		/* 0: utmi+, 1:ulpi*/
415 #ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
416 		|0<<3		/* phy i/f  0:8bit, 1:16bit*/
417 #else
418 		|1<<3		/* phy i/f  0:8bit, 1:16bit*/
419 #endif
420 		|0x7<<0;	/* HS/FS Timeout**/
421 
422 	if (dev->pdata->usb_gusbcfg)
423 		dflt_gusbcfg = dev->pdata->usb_gusbcfg;
424 
425 	writel(dflt_gusbcfg, &reg->gusbcfg);
426 
427 	/* 3. Put the OTG device core in the disconnected state.*/
428 	uTemp = readl(&reg->dctl);
429 	uTemp |= SOFT_DISCONNECT;
430 	writel(uTemp, &reg->dctl);
431 
432 	udelay(20);
433 
434 	/* 4. Make the OTG device core exit from the disconnected state.*/
435 	uTemp = readl(&reg->dctl);
436 	uTemp = uTemp & ~SOFT_DISCONNECT;
437 	writel(uTemp, &reg->dctl);
438 
439 	/* 5. Configure OTG Core to initial settings of device mode.*/
440 	/* [][1: full speed(30Mhz) 0:high speed]*/
441 	writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
442 
443 	mdelay(1);
444 
445 	/* 6. Unmask the core interrupts*/
446 	writel(GINTMSK_INIT, &reg->gintmsk);
447 
448 	/* 7. Set NAK bit of EP0, EP1, EP2*/
449 	writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
450 	writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
451 
452 	for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
453 		writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
454 		writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
455 	}
456 
457 	/* 8. Unmask EPO interrupts*/
458 	writel(((1 << EP0_CON) << DAINT_OUT_BIT)
459 	       | (1 << EP0_CON), &reg->daintmsk);
460 
461 	/* 9. Unmask device OUT EP common interrupts*/
462 	writel(DOEPMSK_INIT, &reg->doepmsk);
463 
464 	/* 10. Unmask device IN EP common interrupts*/
465 	writel(DIEPMSK_INIT, &reg->diepmsk);
466 
467 	rx_fifo_sz = RX_FIFO_SIZE;
468 	np_tx_fifo_sz = NPTX_FIFO_SIZE;
469 	tx_fifo_sz = PTX_FIFO_SIZE;
470 
471 	if (dev->pdata->rx_fifo_sz)
472 		rx_fifo_sz = dev->pdata->rx_fifo_sz;
473 	if (dev->pdata->np_tx_fifo_sz)
474 		np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
475 	if (dev->pdata->tx_fifo_sz)
476 		tx_fifo_sz = dev->pdata->tx_fifo_sz;
477 
478 	/* 11. Set Rx FIFO Size (in 32-bit words) */
479 	writel(rx_fifo_sz, &reg->grxfsiz);
480 
481 	/* 12. Set Non Periodic Tx FIFO Size */
482 	writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
483 	       &reg->gnptxfsiz);
484 
485 	for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
486 		writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
487 			tx_fifo_sz << 16, &reg->dieptxf[i-1]);
488 
489 	/* Flush the RX FIFO */
490 	writel(RX_FIFO_FLUSH, &reg->grstctl);
491 	while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
492 		debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
493 
494 	/* Flush all the Tx FIFO's */
495 	writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
496 	writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
497 	while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
498 		debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
499 
500 	/* 13. Clear NAK bit of EP0, EP1, EP2*/
501 	/* For Slave mode*/
502 	/* EP0: Control OUT */
503 	writel(DEPCTL_EPDIS | DEPCTL_CNAK,
504 	       &reg->out_endp[EP0_CON].doepctl);
505 
506 	/* 14. Initialize OTG Link Core.*/
507 	writel(GAHBCFG_INIT, &reg->gahbcfg);
508 }
509 
510 static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
511 {
512 	unsigned int ep_ctrl;
513 	int i;
514 
515 	if (speed == USB_SPEED_HIGH) {
516 		ep0_fifo_size = 64;
517 		ep_fifo_size = 512;
518 		ep_fifo_size2 = 1024;
519 		dev->gadget.speed = USB_SPEED_HIGH;
520 	} else {
521 		ep0_fifo_size = 64;
522 		ep_fifo_size = 64;
523 		ep_fifo_size2 = 64;
524 		dev->gadget.speed = USB_SPEED_FULL;
525 	}
526 
527 	dev->ep[0].ep.maxpacket = ep0_fifo_size;
528 	for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
529 		dev->ep[i].ep.maxpacket = ep_fifo_size;
530 
531 	/* EP0 - Control IN (64 bytes)*/
532 	ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
533 	writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
534 
535 	/* EP0 - Control OUT (64 bytes)*/
536 	ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
537 	writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
538 }
539 
540 static int dwc2_ep_enable(struct usb_ep *_ep,
541 			 const struct usb_endpoint_descriptor *desc)
542 {
543 	struct dwc2_ep *ep;
544 	struct dwc2_udc *dev;
545 	unsigned long flags = 0;
546 
547 	debug("%s: %p\n", __func__, _ep);
548 
549 	ep = container_of(_ep, struct dwc2_ep, ep);
550 	if (!_ep || !desc || ep->desc || _ep->name == ep0name
551 	    || desc->bDescriptorType != USB_DT_ENDPOINT
552 	    || ep->bEndpointAddress != desc->bEndpointAddress
553 	    || ep_maxpacket(ep) <
554 	    le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
555 
556 		debug("%s: bad ep or descriptor\n", __func__);
557 		return -EINVAL;
558 	}
559 
560 	/* xfer types must match, except that interrupt ~= bulk */
561 	if (ep->bmAttributes != desc->bmAttributes
562 	    && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
563 	    && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
564 
565 		debug("%s: %s type mismatch\n", __func__, _ep->name);
566 		return -EINVAL;
567 	}
568 
569 	/* hardware _could_ do smaller, but driver doesn't */
570 	if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
571 	     le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
572 	     ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
573 
574 		debug("%s: bad %s maxpacket\n", __func__, _ep->name);
575 		return -ERANGE;
576 	}
577 
578 	dev = ep->dev;
579 	if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
580 
581 		debug("%s: bogus device state\n", __func__);
582 		return -ESHUTDOWN;
583 	}
584 
585 	ep->stopped = 0;
586 	ep->desc = desc;
587 	ep->pio_irqs = 0;
588 	ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
589 
590 	/* Reset halt state */
591 	dwc2_udc_set_nak(ep);
592 	dwc2_udc_set_halt(_ep, 0);
593 
594 	spin_lock_irqsave(&ep->dev->lock, flags);
595 	dwc2_udc_ep_activate(ep);
596 	spin_unlock_irqrestore(&ep->dev->lock, flags);
597 
598 	debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
599 	      __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
600 	return 0;
601 }
602 
603 /*
604  * Disable EP
605  */
606 static int dwc2_ep_disable(struct usb_ep *_ep)
607 {
608 	struct dwc2_ep *ep;
609 	unsigned long flags = 0;
610 
611 	debug("%s: %p\n", __func__, _ep);
612 
613 	ep = container_of(_ep, struct dwc2_ep, ep);
614 	if (!_ep || !ep->desc) {
615 		debug("%s: %s not enabled\n", __func__,
616 		      _ep ? ep->ep.name : NULL);
617 		return -EINVAL;
618 	}
619 
620 	spin_lock_irqsave(&ep->dev->lock, flags);
621 
622 	/* Nuke all pending requests */
623 	nuke(ep, -ESHUTDOWN);
624 
625 	ep->desc = 0;
626 	ep->stopped = 1;
627 
628 	spin_unlock_irqrestore(&ep->dev->lock, flags);
629 
630 	debug("%s: disabled %s\n", __func__, _ep->name);
631 	return 0;
632 }
633 
634 static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
635 					     gfp_t gfp_flags)
636 {
637 	struct dwc2_request *req;
638 
639 	debug("%s: %s %p\n", __func__, ep->name, ep);
640 
641 	req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
642 	if (!req)
643 		return 0;
644 
645 	memset(req, 0, sizeof *req);
646 	INIT_LIST_HEAD(&req->queue);
647 
648 	return &req->req;
649 }
650 
651 static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req)
652 {
653 	struct dwc2_request *req;
654 
655 	debug("%s: %p\n", __func__, ep);
656 
657 	req = container_of(_req, struct dwc2_request, req);
658 	WARN_ON(!list_empty(&req->queue));
659 	kfree(req);
660 }
661 
662 /* dequeue JUST ONE request */
663 static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req)
664 {
665 	struct dwc2_ep *ep;
666 	struct dwc2_request *req;
667 	unsigned long flags = 0;
668 
669 	debug("%s: %p\n", __func__, _ep);
670 
671 	ep = container_of(_ep, struct dwc2_ep, ep);
672 	if (!_ep || ep->ep.name == ep0name)
673 		return -EINVAL;
674 
675 	spin_lock_irqsave(&ep->dev->lock, flags);
676 
677 	/* make sure it's actually queued on this endpoint */
678 	list_for_each_entry(req, &ep->queue, queue) {
679 		if (&req->req == _req)
680 			break;
681 	}
682 	if (&req->req != _req) {
683 		spin_unlock_irqrestore(&ep->dev->lock, flags);
684 		return -EINVAL;
685 	}
686 
687 	done(ep, req, -ECONNRESET);
688 
689 	spin_unlock_irqrestore(&ep->dev->lock, flags);
690 	return 0;
691 }
692 
693 /*
694  * Return bytes in EP FIFO
695  */
696 static int dwc2_fifo_status(struct usb_ep *_ep)
697 {
698 	int count = 0;
699 	struct dwc2_ep *ep;
700 
701 	ep = container_of(_ep, struct dwc2_ep, ep);
702 	if (!_ep) {
703 		debug("%s: bad ep\n", __func__);
704 		return -ENODEV;
705 	}
706 
707 	debug("%s: %d\n", __func__, ep_index(ep));
708 
709 	/* LPD can't report unclaimed bytes from IN fifos */
710 	if (ep_is_in(ep))
711 		return -EOPNOTSUPP;
712 
713 	return count;
714 }
715 
716 /*
717  * Flush EP FIFO
718  */
719 static void dwc2_fifo_flush(struct usb_ep *_ep)
720 {
721 	struct dwc2_ep *ep;
722 
723 	ep = container_of(_ep, struct dwc2_ep, ep);
724 	if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
725 		debug("%s: bad ep\n", __func__);
726 		return;
727 	}
728 
729 	debug("%s: %d\n", __func__, ep_index(ep));
730 }
731 
732 static const struct usb_gadget_ops dwc2_udc_ops = {
733 	/* current versions must always be self-powered */
734 };
735 
736 static struct dwc2_udc memory = {
737 	.usb_address = 0,
738 	.gadget = {
739 		.ops = &dwc2_udc_ops,
740 		.ep0 = &memory.ep[0].ep,
741 		.name = driver_name,
742 	},
743 
744 	/* control endpoint */
745 	.ep[0] = {
746 		.ep = {
747 			.name = ep0name,
748 			.ops = &dwc2_ep_ops,
749 			.maxpacket = EP0_FIFO_SIZE,
750 		},
751 		.dev = &memory,
752 
753 		.bEndpointAddress = 0,
754 		.bmAttributes = 0,
755 
756 		.ep_type = ep_control,
757 	},
758 
759 	/* first group of endpoints */
760 	.ep[1] = {
761 		.ep = {
762 			.name = "ep1in-bulk",
763 			.ops = &dwc2_ep_ops,
764 			.maxpacket = EP_FIFO_SIZE,
765 		},
766 		.dev = &memory,
767 
768 		.bEndpointAddress = USB_DIR_IN | 1,
769 		.bmAttributes = USB_ENDPOINT_XFER_BULK,
770 
771 		.ep_type = ep_bulk_out,
772 		.fifo_num = 1,
773 	},
774 
775 	.ep[2] = {
776 		.ep = {
777 			.name = "ep2out-bulk",
778 			.ops = &dwc2_ep_ops,
779 			.maxpacket = EP_FIFO_SIZE,
780 		},
781 		.dev = &memory,
782 
783 		.bEndpointAddress = USB_DIR_OUT | 2,
784 		.bmAttributes = USB_ENDPOINT_XFER_BULK,
785 
786 		.ep_type = ep_bulk_in,
787 		.fifo_num = 2,
788 	},
789 
790 	.ep[3] = {
791 		.ep = {
792 			.name = "ep3in-int",
793 			.ops = &dwc2_ep_ops,
794 			.maxpacket = EP_FIFO_SIZE,
795 		},
796 		.dev = &memory,
797 
798 		.bEndpointAddress = USB_DIR_IN | 3,
799 		.bmAttributes = USB_ENDPOINT_XFER_INT,
800 
801 		.ep_type = ep_interrupt,
802 		.fifo_num = 3,
803 	},
804 };
805 
806 /*
807  *	probe - binds to the platform device
808  */
809 
810 int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
811 {
812 	struct dwc2_udc *dev = &memory;
813 	int retval = 0;
814 
815 	debug("%s: %p\n", __func__, pdata);
816 
817 	dev->pdata = pdata;
818 
819 	reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
820 
821 	/* regs_otg = (void *)pdata->regs_otg; */
822 
823 	dev->gadget.is_dualspeed = 1;	/* Hack only*/
824 	dev->gadget.is_otg = 0;
825 	dev->gadget.is_a_peripheral = 0;
826 	dev->gadget.b_hnp_enable = 0;
827 	dev->gadget.a_hnp_support = 0;
828 	dev->gadget.a_alt_hnp_support = 0;
829 
830 	the_controller = dev;
831 
832 	usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
833 			    ROUND(sizeof(struct usb_ctrlrequest),
834 				  CONFIG_SYS_CACHELINE_SIZE));
835 	if (!usb_ctrl) {
836 		pr_err("No memory available for UDC!\n");
837 		return -ENOMEM;
838 	}
839 
840 	usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
841 
842 	udc_reinit(dev);
843 
844 	return retval;
845 }
846 
847 int usb_gadget_handle_interrupts(int index)
848 {
849 	u32 intr_status = readl(&reg->gintsts);
850 	u32 gintmsk = readl(&reg->gintmsk);
851 
852 	if (intr_status & gintmsk)
853 		return dwc2_udc_irq(1, (void *)the_controller);
854 	return 0;
855 }
856