1 /*
2  * Based on drivers/usb/gadget/omap1510_udc.c
3  * TI OMAP1510 USB bus interface driver
4  *
5  * (C) Copyright 2009
6  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <asm/io.h>
13 
14 #include <usbdevice.h>
15 #include "ep0.h"
16 #include <usb/designware_udc.h>
17 #include <asm/arch/hardware.h>
18 
19 #define UDC_INIT_MDELAY		80	/* Device settle delay */
20 
21 /* Some kind of debugging output... */
22 #ifndef DEBUG_DWUSBTTY
23 #define UDCDBG(str)
24 #define UDCDBGA(fmt, args...)
25 #else
26 #define UDCDBG(str) serial_printf(str "\n")
27 #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
28 #endif
29 
30 static struct urb *ep0_urb;
31 static struct usb_device_instance *udc_device;
32 
33 static struct plug_regs *const plug_regs_p =
34     (struct plug_regs * const)CONFIG_SYS_PLUG_BASE;
35 static struct udc_regs *const udc_regs_p =
36     (struct udc_regs * const)CONFIG_SYS_USBD_BASE;
37 static struct udc_endp_regs *const outep_regs_p =
38     &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0];
39 static struct udc_endp_regs *const inep_regs_p =
40     &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0];
41 
42 /*
43  * udc_state_transition - Write the next packet to TxFIFO.
44  * @initial:	Initial state.
45  * @final:	Final state.
46  *
47  * Helper function to implement device state changes. The device states and
48  * the events that transition between them are:
49  *
50  *				STATE_ATTACHED
51  *				||	/\
52  *				\/	||
53  *	DEVICE_HUB_CONFIGURED			DEVICE_HUB_RESET
54  *				||	/\
55  *				\/	||
56  *				STATE_POWERED
57  *				||	/\
58  *				\/	||
59  *	DEVICE_RESET				DEVICE_POWER_INTERRUPTION
60  *				||	/\
61  *				\/	||
62  *				STATE_DEFAULT
63  *				||	/\
64  *				\/	||
65  *	DEVICE_ADDRESS_ASSIGNED			DEVICE_RESET
66  *				||	/\
67  *				\/	||
68  *				STATE_ADDRESSED
69  *				||	/\
70  *				\/	||
71  *	DEVICE_CONFIGURED			DEVICE_DE_CONFIGURED
72  *				||	/\
73  *				\/	||
74  *				STATE_CONFIGURED
75  *
76  * udc_state_transition transitions up (in the direction from STATE_ATTACHED
77  * to STATE_CONFIGURED) from the specified initial state to the specified final
78  * state, passing through each intermediate state on the way. If the initial
79  * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
80  * no state transitions will take place.
81  *
82  * udc_state_transition also transitions down (in the direction from
83  * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
84  * specified final state, passing through each intermediate state on the way.
85  * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
86  * state, then no state transitions will take place.
87  *
88  * This function must only be called with interrupts disabled.
89  */
90 static void udc_state_transition(usb_device_state_t initial,
91 				 usb_device_state_t final)
92 {
93 	if (initial < final) {
94 		switch (initial) {
95 		case STATE_ATTACHED:
96 			usbd_device_event_irq(udc_device,
97 					      DEVICE_HUB_CONFIGURED, 0);
98 			if (final == STATE_POWERED)
99 				break;
100 		case STATE_POWERED:
101 			usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
102 			if (final == STATE_DEFAULT)
103 				break;
104 		case STATE_DEFAULT:
105 			usbd_device_event_irq(udc_device,
106 					      DEVICE_ADDRESS_ASSIGNED, 0);
107 			if (final == STATE_ADDRESSED)
108 				break;
109 		case STATE_ADDRESSED:
110 			usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
111 		case STATE_CONFIGURED:
112 			break;
113 		default:
114 			break;
115 		}
116 	} else if (initial > final) {
117 		switch (initial) {
118 		case STATE_CONFIGURED:
119 			usbd_device_event_irq(udc_device,
120 					      DEVICE_DE_CONFIGURED, 0);
121 			if (final == STATE_ADDRESSED)
122 				break;
123 		case STATE_ADDRESSED:
124 			usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
125 			if (final == STATE_DEFAULT)
126 				break;
127 		case STATE_DEFAULT:
128 			usbd_device_event_irq(udc_device,
129 					      DEVICE_POWER_INTERRUPTION, 0);
130 			if (final == STATE_POWERED)
131 				break;
132 		case STATE_POWERED:
133 			usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
134 		case STATE_ATTACHED:
135 			break;
136 		default:
137 			break;
138 		}
139 	}
140 }
141 
142 /* Stall endpoint */
143 static void udc_stall_ep(u32 ep_num)
144 {
145 	writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
146 	       &inep_regs_p[ep_num].endp_cntl);
147 
148 	writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
149 	       &outep_regs_p[ep_num].endp_cntl);
150 }
151 
152 static void *get_fifo(int ep_num, int in)
153 {
154 	u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE;
155 
156 	switch (ep_num) {
157 	case UDC_EP3:
158 		fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn);
159 		/* break intentionally left out */
160 
161 	case UDC_EP1:
162 		fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn);
163 		/* break intentionally left out */
164 
165 	case UDC_EP0:
166 	default:
167 		if (in) {
168 			fifo_ptr +=
169 			    readl(&outep_regs_p[2].endp_maxpacksize) >> 16;
170 			/* break intentionally left out */
171 		} else {
172 			break;
173 		}
174 
175 	case UDC_EP2:
176 		fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16;
177 		/* break intentionally left out */
178 	}
179 
180 	return (void *)fifo_ptr;
181 }
182 
183 static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)
184 {
185 	u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0);
186 	u32 i, nw, nb;
187 	u32 *wrdp;
188 	u8 *bytp;
189 	u32 tmp[128];
190 
191 	if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY)
192 		return -1;
193 
194 	nw = len / sizeof(u32);
195 	nb = len % sizeof(u32);
196 
197 	/* use tmp buf if bufp is not word aligned */
198 	if ((int)bufp & 0x3)
199 		wrdp = (u32 *)&tmp[0];
200 	else
201 		wrdp = (u32 *)bufp;
202 
203 	for (i = 0; i < nw; i++) {
204 		writel(readl(fifo_ptr), wrdp);
205 		wrdp++;
206 	}
207 
208 	bytp = (u8 *)wrdp;
209 	for (i = 0; i < nb; i++) {
210 		writeb(readb(fifo_ptr), bytp);
211 		fifo_ptr++;
212 		bytp++;
213 	}
214 	readl(&outep_regs_p[epNum].write_done);
215 
216 	/* copy back tmp buffer to bufp if bufp is not word aligned */
217 	if ((int)bufp & 0x3)
218 		memcpy(bufp, tmp, len);
219 
220 	return 0;
221 }
222 
223 static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)
224 {
225 	u32 i, nw, nb;
226 	u32 *wrdp;
227 	u8 *bytp;
228 	u8 *fifo_ptr = get_fifo(epNum, 1);
229 
230 	nw = len / sizeof(int);
231 	nb = len % sizeof(int);
232 	wrdp = (u32 *)bufp;
233 	for (i = 0; i < nw; i++) {
234 		writel(*wrdp, fifo_ptr);
235 		wrdp++;
236 	}
237 
238 	bytp = (u8 *)wrdp;
239 	for (i = 0; i < nb; i++) {
240 		writeb(*bytp, fifo_ptr);
241 		fifo_ptr++;
242 		bytp++;
243 	}
244 }
245 
246 /*
247  * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO.
248  * @endpoint:		Endpoint pointer.
249  *
250  * If the endpoint has an active tx_urb, then the next packet of data from the
251  * URB is written to the tx FIFO.  The total amount of data in the urb is given
252  * by urb->actual_length.  The maximum amount of data that can be sent in any
253  * one packet is given by endpoint->tx_packetSize.  The number of data bytes
254  * from this URB that have already been transmitted is given by endpoint->sent.
255  * endpoint->last is updated by this routine with the number of data bytes
256  * transmitted in this packet.
257  *
258  */
259 static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
260 				       *endpoint)
261 {
262 	struct urb *urb = endpoint->tx_urb;
263 	int align;
264 
265 	if (urb) {
266 		u32 last;
267 
268 		UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
269 			urb->buffer, urb->buffer_length, urb->actual_length);
270 
271 		last = MIN(urb->actual_length - endpoint->sent,
272 			   endpoint->tx_packetSize);
273 
274 		if (last) {
275 			u8 *cp = urb->buffer + endpoint->sent;
276 
277 			/*
278 			 * This ensures that USBD packet fifo is accessed
279 			 * - through word aligned pointer or
280 			 * - through non word aligned pointer but only
281 			 *   with a max length to make the next packet
282 			 *   word aligned
283 			 */
284 
285 			align = ((ulong)cp % sizeof(int));
286 			if (align)
287 				last = MIN(last, sizeof(int) - align);
288 
289 			UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
290 				endpoint->sent, endpoint->tx_packetSize, last);
291 
292 			usbputpcktofifo(endpoint->endpoint_address &
293 					USB_ENDPOINT_NUMBER_MASK, cp, last);
294 		}
295 		endpoint->last = last;
296 	}
297 }
298 
299 /*
300  * Handle SETUP USB interrupt.
301  * This function implements TRM Figure 14-14.
302  */
303 static void dw_udc_setup(struct usb_endpoint_instance *endpoint)
304 {
305 	u8 *datap = (u8 *)&ep0_urb->device_request;
306 	int ep_addr = endpoint->endpoint_address;
307 
308 	UDCDBG("-> Entering device setup");
309 	usbgetpckfromfifo(ep_addr, datap, 8);
310 
311 	/* Try to process setup packet */
312 	if (ep0_recv_setup(ep0_urb)) {
313 		/* Not a setup packet, stall next EP0 transaction */
314 		udc_stall_ep(0);
315 		UDCDBG("can't parse setup packet, still waiting for setup");
316 		return;
317 	}
318 
319 	/* Check direction */
320 	if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
321 	    == USB_REQ_HOST2DEVICE) {
322 		UDCDBG("control write on EP0");
323 		if (le16_to_cpu(ep0_urb->device_request.wLength)) {
324 			/* Stall this request */
325 			UDCDBG("Stalling unsupported EP0 control write data "
326 			       "stage.");
327 			udc_stall_ep(0);
328 		}
329 	} else {
330 
331 		UDCDBG("control read on EP0");
332 		/*
333 		 * The ep0_recv_setup function has already placed our response
334 		 * packet data in ep0_urb->buffer and the packet length in
335 		 * ep0_urb->actual_length.
336 		 */
337 		endpoint->tx_urb = ep0_urb;
338 		endpoint->sent = 0;
339 		/*
340 		 * Write packet data to the FIFO.  dw_write_noniso_tx_fifo
341 		 * will update endpoint->last with the number of bytes written
342 		 * to the FIFO.
343 		 */
344 		dw_write_noniso_tx_fifo(endpoint);
345 
346 		writel(0x0, &inep_regs_p[ep_addr].write_done);
347 	}
348 
349 	udc_unset_nak(endpoint->endpoint_address);
350 
351 	UDCDBG("<- Leaving device setup");
352 }
353 
354 /*
355  * Handle endpoint 0 RX interrupt
356  */
357 static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
358 {
359 	u8 dummy[64];
360 
361 	UDCDBG("RX on EP0");
362 
363 	/* Check direction */
364 	if ((ep0_urb->device_request.bmRequestType
365 	     & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
366 		/*
367 		 * This rx interrupt must be for a control write data
368 		 * stage packet.
369 		 *
370 		 * We don't support control write data stages.
371 		 * We should never end up here.
372 		 */
373 
374 		UDCDBG("Stalling unexpected EP0 control write "
375 		       "data stage packet");
376 		udc_stall_ep(0);
377 	} else {
378 		/*
379 		 * This rx interrupt must be for a control read status
380 		 * stage packet.
381 		 */
382 		UDCDBG("ACK on EP0 control read status stage packet");
383 		u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff;
384 		usbgetpckfromfifo(0, dummy, len);
385 	}
386 }
387 
388 /*
389  * Handle endpoint 0 TX interrupt
390  */
391 static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
392 {
393 	struct usb_device_request *request = &ep0_urb->device_request;
394 	int ep_addr;
395 
396 	UDCDBG("TX on EP0");
397 
398 	/* Check direction */
399 	if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
400 	    USB_REQ_HOST2DEVICE) {
401 		/*
402 		 * This tx interrupt must be for a control write status
403 		 * stage packet.
404 		 */
405 		UDCDBG("ACK on EP0 control write status stage packet");
406 	} else {
407 		/*
408 		 * This tx interrupt must be for a control read data
409 		 * stage packet.
410 		 */
411 		int wLength = le16_to_cpu(request->wLength);
412 
413 		/*
414 		 * Update our count of bytes sent so far in this
415 		 * transfer.
416 		 */
417 		endpoint->sent += endpoint->last;
418 
419 		/*
420 		 * We are finished with this transfer if we have sent
421 		 * all of the bytes in our tx urb (urb->actual_length)
422 		 * unless we need a zero-length terminating packet.  We
423 		 * need a zero-length terminating packet if we returned
424 		 * fewer bytes than were requested (wLength) by the host,
425 		 * and the number of bytes we returned is an exact
426 		 * multiple of the packet size endpoint->tx_packetSize.
427 		 */
428 		if ((endpoint->sent == ep0_urb->actual_length) &&
429 		    ((ep0_urb->actual_length == wLength) ||
430 		     (endpoint->last != endpoint->tx_packetSize))) {
431 			/* Done with control read data stage. */
432 			UDCDBG("control read data stage complete");
433 		} else {
434 			/*
435 			 * We still have another packet of data to send
436 			 * in this control read data stage or else we
437 			 * need a zero-length terminating packet.
438 			 */
439 			UDCDBG("ACK control read data stage packet");
440 			dw_write_noniso_tx_fifo(endpoint);
441 
442 			ep_addr = endpoint->endpoint_address;
443 			writel(0x0, &inep_regs_p[ep_addr].write_done);
444 		}
445 	}
446 }
447 
448 static struct usb_endpoint_instance *dw_find_ep(int ep)
449 {
450 	int i;
451 
452 	for (i = 0; i < udc_device->bus->max_endpoints; i++) {
453 		if ((udc_device->bus->endpoint_array[i].endpoint_address &
454 		     USB_ENDPOINT_NUMBER_MASK) == ep)
455 			return &udc_device->bus->endpoint_array[i];
456 	}
457 	return NULL;
458 }
459 
460 /*
461  * Handle RX transaction on non-ISO endpoint.
462  * The ep argument is a physical endpoint number for a non-ISO IN endpoint
463  * in the range 1 to 15.
464  */
465 static void dw_udc_epn_rx(int ep)
466 {
467 	int nbytes = 0;
468 	struct urb *urb;
469 	struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
470 
471 	if (endpoint) {
472 		urb = endpoint->rcv_urb;
473 
474 		if (urb) {
475 			u8 *cp = urb->buffer + urb->actual_length;
476 
477 			nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) &
478 			    0xfff;
479 			usbgetpckfromfifo(ep, cp, nbytes);
480 			usbd_rcv_complete(endpoint, nbytes, 0);
481 		}
482 	}
483 }
484 
485 /*
486  * Handle TX transaction on non-ISO endpoint.
487  * The ep argument is a physical endpoint number for a non-ISO IN endpoint
488  * in the range 16 to 30.
489  */
490 static void dw_udc_epn_tx(int ep)
491 {
492 	struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
493 
494 	if (!endpoint)
495 		return;
496 
497 	/*
498 	 * We need to transmit a terminating zero-length packet now if
499 	 * we have sent all of the data in this URB and the transfer
500 	 * size was an exact multiple of the packet size.
501 	 */
502 	if (endpoint->tx_urb &&
503 	    (endpoint->last == endpoint->tx_packetSize) &&
504 	    (endpoint->tx_urb->actual_length - endpoint->sent -
505 	     endpoint->last == 0)) {
506 		/* handle zero length packet here */
507 		writel(0x0, &inep_regs_p[ep].write_done);
508 
509 	}
510 
511 	if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
512 		/* retire the data that was just sent */
513 		usbd_tx_complete(endpoint);
514 		/*
515 		 * Check to see if we have more data ready to transmit
516 		 * now.
517 		 */
518 		if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
519 			/* write data to FIFO */
520 			dw_write_noniso_tx_fifo(endpoint);
521 			writel(0x0, &inep_regs_p[ep].write_done);
522 
523 		} else if (endpoint->tx_urb
524 			   && (endpoint->tx_urb->actual_length == 0)) {
525 			/* udc_set_nak(ep); */
526 		}
527 	}
528 }
529 
530 /*
531  * Start of public functions.
532  */
533 
534 /* Called to start packet transmission. */
535 int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
536 {
537 	udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
538 	return 0;
539 }
540 
541 /* Start to initialize h/w stuff */
542 int udc_init(void)
543 {
544 	int i;
545 	u32 plug_st;
546 
547 	udc_device = NULL;
548 
549 	UDCDBG("starting");
550 
551 	readl(&plug_regs_p->plug_pending);
552 
553 	for (i = 0; i < UDC_INIT_MDELAY; i++)
554 		udelay(1000);
555 
556 	plug_st = readl(&plug_regs_p->plug_state);
557 	writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state);
558 
559 	writel(~0x0, &udc_regs_p->endp_int);
560 	writel(~0x0, &udc_regs_p->dev_int_mask);
561 	writel(~0x0, &udc_regs_p->endp_int_mask);
562 
563 #ifndef CONFIG_USBD_HS
564 	writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
565 	       DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
566 #else
567 	writel(DEV_CONF_HS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
568 			DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
569 #endif
570 
571 	writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
572 
573 	/* Clear all interrupts pending */
574 	writel(DEV_INT_MSK, &udc_regs_p->dev_int);
575 
576 	return 0;
577 }
578 
579 int is_usbd_high_speed(void)
580 {
581 	return (readl(&udc_regs_p->dev_stat) & DEV_STAT_ENUM) ? 0 : 1;
582 }
583 
584 /*
585  * udc_setup_ep - setup endpoint
586  * Associate a physical endpoint with endpoint_instance
587  */
588 void udc_setup_ep(struct usb_device_instance *device,
589 		  u32 ep, struct usb_endpoint_instance *endpoint)
590 {
591 	UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address);
592 	int ep_addr;
593 	int ep_num, ep_type;
594 	int packet_size;
595 	int buffer_size;
596 	int attributes;
597 	char *tt;
598 	u32 endp_intmask;
599 
600 	if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED))
601 		return;
602 
603 	tt = getenv("usbtty");
604 	if (!tt)
605 		tt = "generic";
606 
607 	ep_addr = endpoint->endpoint_address;
608 	ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
609 
610 	if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
611 		/* IN endpoint */
612 		packet_size = endpoint->tx_packetSize;
613 		buffer_size = packet_size * 2;
614 		attributes = endpoint->tx_attributes;
615 	} else {
616 		/* OUT endpoint */
617 		packet_size = endpoint->rcv_packetSize;
618 		buffer_size = packet_size * 2;
619 		attributes = endpoint->rcv_attributes;
620 	}
621 
622 	switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
623 	case USB_ENDPOINT_XFER_CONTROL:
624 		ep_type = ENDP_EPTYPE_CNTL;
625 		break;
626 	case USB_ENDPOINT_XFER_BULK:
627 	default:
628 		ep_type = ENDP_EPTYPE_BULK;
629 		break;
630 	case USB_ENDPOINT_XFER_INT:
631 		ep_type = ENDP_EPTYPE_INT;
632 		break;
633 	case USB_ENDPOINT_XFER_ISOC:
634 		ep_type = ENDP_EPTYPE_ISO;
635 		break;
636 	}
637 
638 	struct udc_endp_regs *out_p = &outep_regs_p[ep_num];
639 	struct udc_endp_regs *in_p = &inep_regs_p[ep_num];
640 
641 	if (!ep_addr) {
642 		/* Setup endpoint 0 */
643 		buffer_size = packet_size;
644 
645 		writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK,
646 		       &in_p->endp_cntl);
647 
648 		writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK,
649 		       &out_p->endp_cntl);
650 
651 		writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl);
652 
653 		writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
654 
655 		writel(packet_size, &in_p->endp_maxpacksize);
656 
657 		writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl);
658 
659 		writel(packet_size | ((buffer_size / sizeof(int)) << 16),
660 		       &out_p->endp_maxpacksize);
661 
662 	} else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
663 		/* Setup the IN endpoint */
664 		writel(0x0, &in_p->endp_status);
665 		writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl);
666 		writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
667 		writel(packet_size, &in_p->endp_maxpacksize);
668 
669 		if (!strcmp(tt, "cdc_acm")) {
670 			if (ep_type == ENDP_EPTYPE_INT) {
671 				/* Conf no. 1 Interface no. 0 */
672 				writel((packet_size << 19) |
673 				       ENDP_EPDIR_IN | (1 << 7) |
674 				       (0 << 11) | (ep_type << 5) | ep_num,
675 				       &udc_regs_p->udc_endp_reg[ep_num]);
676 			} else {
677 				/* Conf no. 1 Interface no. 1 */
678 				writel((packet_size << 19) |
679 				       ENDP_EPDIR_IN | (1 << 7) |
680 				       (1 << 11) | (ep_type << 5) | ep_num,
681 				       &udc_regs_p->udc_endp_reg[ep_num]);
682 			}
683 		} else {
684 			/* Conf no. 1 Interface no. 0 */
685 			writel((packet_size << 19) |
686 			       ENDP_EPDIR_IN | (1 << 7) |
687 			       (0 << 11) | (ep_type << 5) | ep_num,
688 			       &udc_regs_p->udc_endp_reg[ep_num]);
689 		}
690 
691 	} else {
692 		/* Setup the OUT endpoint */
693 		writel(0x0, &out_p->endp_status);
694 		writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl);
695 		writel(packet_size | ((buffer_size / sizeof(int)) << 16),
696 		       &out_p->endp_maxpacksize);
697 
698 		if (!strcmp(tt, "cdc_acm")) {
699 			writel((packet_size << 19) |
700 			       ENDP_EPDIR_OUT | (1 << 7) |
701 			       (1 << 11) | (ep_type << 5) | ep_num,
702 			       &udc_regs_p->udc_endp_reg[ep_num]);
703 		} else {
704 			writel((packet_size << 19) |
705 			       ENDP_EPDIR_OUT | (1 << 7) |
706 			       (0 << 11) | (ep_type << 5) | ep_num,
707 			       &udc_regs_p->udc_endp_reg[ep_num]);
708 		}
709 
710 	}
711 
712 	endp_intmask = readl(&udc_regs_p->endp_int_mask);
713 	endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num);
714 	writel(endp_intmask, &udc_regs_p->endp_int_mask);
715 }
716 
717 /* Turn on the USB connection by enabling the pullup resistor */
718 void udc_connect(void)
719 {
720 	u32 plug_st, dev_cntl;
721 
722 	dev_cntl = readl(&udc_regs_p->dev_cntl);
723 	dev_cntl |= DEV_CNTL_SOFTDISCONNECT;
724 	writel(dev_cntl, &udc_regs_p->dev_cntl);
725 
726 	udelay(1000);
727 
728 	dev_cntl = readl(&udc_regs_p->dev_cntl);
729 	dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT;
730 	writel(dev_cntl, &udc_regs_p->dev_cntl);
731 
732 	plug_st = readl(&plug_regs_p->plug_state);
733 	plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
734 	writel(plug_st, &plug_regs_p->plug_state);
735 }
736 
737 /* Turn off the USB connection by disabling the pullup resistor */
738 void udc_disconnect(void)
739 {
740 	u32 plug_st;
741 
742 	writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
743 
744 	plug_st = readl(&plug_regs_p->plug_state);
745 	plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
746 	writel(plug_st, &plug_regs_p->plug_state);
747 }
748 
749 /* Switch on the UDC */
750 void udc_enable(struct usb_device_instance *device)
751 {
752 	UDCDBGA("enable device %p, status %d", device, device->status);
753 
754 	/* Save the device structure pointer */
755 	udc_device = device;
756 
757 	/* Setup ep0 urb */
758 	if (!ep0_urb) {
759 		ep0_urb =
760 		    usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array);
761 	} else {
762 		serial_printf("udc_enable: ep0_urb already allocated %p\n",
763 			      ep0_urb);
764 	}
765 
766 	writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
767 }
768 
769 /**
770  * udc_startup - allow udc code to do any additional startup
771  */
772 void udc_startup_events(struct usb_device_instance *device)
773 {
774 	/* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
775 	usbd_device_event_irq(device, DEVICE_INIT, 0);
776 
777 	/*
778 	 * The DEVICE_CREATE event puts the USB device in the state
779 	 * STATE_ATTACHED.
780 	 */
781 	usbd_device_event_irq(device, DEVICE_CREATE, 0);
782 
783 	/*
784 	 * Some USB controller driver implementations signal
785 	 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
786 	 * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
787 	 * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
788 	 * The DW USB client controller has the capability to detect when the
789 	 * USB cable is connected to a powered USB bus, so we will defer the
790 	 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
791 	 */
792 
793 	udc_enable(device);
794 }
795 
796 /*
797  * Plug detection interrupt handling
798  */
799 static void dw_udc_plug_irq(void)
800 {
801 	if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
802 		/*
803 		 * USB cable attached
804 		 * Turn off PHY reset bit (PLUG detect).
805 		 * Switch PHY opmode to normal operation (PLUG detect).
806 		 */
807 		udc_connect();
808 		writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
809 
810 		UDCDBG("device attached and powered");
811 		udc_state_transition(udc_device->device_state, STATE_POWERED);
812 	} else {
813 		writel(~0x0, &udc_regs_p->dev_int_mask);
814 
815 		UDCDBG("device detached or unpowered");
816 		udc_state_transition(udc_device->device_state, STATE_ATTACHED);
817 	}
818 }
819 
820 /*
821  * Device interrupt handling
822  */
823 static void dw_udc_dev_irq(void)
824 {
825 	if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
826 		writel(~0x0, &udc_regs_p->endp_int_mask);
827 
828 		writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH,
829 		       &inep_regs_p[0].endp_cntl);
830 
831 		writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);
832 
833 		/*
834 		 * This endpoint0 specific register can be programmed only
835 		 * after the phy clock is initialized
836 		 */
837 		writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL,
838 				&udc_regs_p->udc_endp_reg[0]);
839 
840 		UDCDBG("device reset in progess");
841 		udc_state_transition(udc_device->device_state, STATE_DEFAULT);
842 	}
843 
844 	/* Device Enumeration completed */
845 	if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) {
846 		writel(DEV_INT_ENUM, &udc_regs_p->dev_int);
847 
848 		/* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
849 		writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001,
850 		       &udc_regs_p->endp_int_mask);
851 
852 		UDCDBG("default -> addressed");
853 		udc_state_transition(udc_device->device_state, STATE_ADDRESSED);
854 	}
855 
856 	/* The USB will be in SUSPEND in 3 ms */
857 	if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) {
858 		writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int);
859 
860 		UDCDBG("entering inactive state");
861 		/* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
862 	}
863 
864 	/* SetConfiguration command received */
865 	if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) {
866 		writel(DEV_INT_SETCFG, &udc_regs_p->dev_int);
867 
868 		UDCDBG("entering configured state");
869 		udc_state_transition(udc_device->device_state,
870 				     STATE_CONFIGURED);
871 	}
872 
873 	/* SetInterface command received */
874 	if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF)
875 		writel(DEV_INT_SETINTF, &udc_regs_p->dev_int);
876 
877 	/* USB Suspend detected on cable */
878 	if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) {
879 		writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int);
880 
881 		UDCDBG("entering suspended state");
882 		usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0);
883 	}
884 
885 	/* USB Start-Of-Frame detected on cable */
886 	if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF)
887 		writel(DEV_INT_SOF, &udc_regs_p->dev_int);
888 }
889 
890 /*
891  * Endpoint interrupt handling
892  */
893 static void dw_udc_endpoint_irq(void)
894 {
895 	while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
896 
897 		writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int);
898 
899 		if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
900 		    == ENDP_STATUS_OUT_SETUP) {
901 			dw_udc_setup(udc_device->bus->endpoint_array + 0);
902 			writel(ENDP_STATUS_OUT_SETUP,
903 			       &outep_regs_p[0].endp_status);
904 
905 		} else if ((readl(&outep_regs_p[0].endp_status) &
906 			    ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
907 			dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
908 			writel(ENDP_STATUS_OUT_DATA,
909 			       &outep_regs_p[0].endp_status);
910 
911 		} else if ((readl(&outep_regs_p[0].endp_status) &
912 			    ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
913 			/* NONE received */
914 		}
915 
916 		writel(0x0, &outep_regs_p[0].endp_status);
917 	}
918 
919 	if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
920 		dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
921 
922 		writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
923 		writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
924 	}
925 
926 	if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) {
927 		u32 epnum = 0;
928 		u32 ep_int = readl(&udc_regs_p->endp_int) &
929 		    ENDP_INT_NONISOOUT_MSK;
930 
931 		ep_int >>= 16;
932 		while (0x0 == (ep_int & 0x1)) {
933 			ep_int >>= 1;
934 			epnum++;
935 		}
936 
937 		writel((1 << 16) << epnum, &udc_regs_p->endp_int);
938 
939 		if ((readl(&outep_regs_p[epnum].endp_status) &
940 		     ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
941 
942 			dw_udc_epn_rx(epnum);
943 			writel(ENDP_STATUS_OUT_DATA,
944 			       &outep_regs_p[epnum].endp_status);
945 		} else if ((readl(&outep_regs_p[epnum].endp_status) &
946 			    ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
947 			writel(0x0, &outep_regs_p[epnum].endp_status);
948 		}
949 	}
950 
951 	if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) {
952 		u32 epnum = 0;
953 		u32 ep_int = readl(&udc_regs_p->endp_int) &
954 		    ENDP_INT_NONISOIN_MSK;
955 
956 		while (0x0 == (ep_int & 0x1)) {
957 			ep_int >>= 1;
958 			epnum++;
959 		}
960 
961 		if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
962 			writel(ENDP_STATUS_IN,
963 			       &outep_regs_p[epnum].endp_status);
964 			dw_udc_epn_tx(epnum);
965 
966 			writel(ENDP_STATUS_IN,
967 			       &outep_regs_p[epnum].endp_status);
968 		}
969 
970 		writel((1 << epnum), &udc_regs_p->endp_int);
971 	}
972 }
973 
974 /*
975  * UDC interrupts
976  */
977 void udc_irq(void)
978 {
979 	/*
980 	 * Loop while we have interrupts.
981 	 * If we don't do this, the input chain
982 	 * polling delay is likely to miss
983 	 * host requests.
984 	 */
985 	while (readl(&plug_regs_p->plug_pending))
986 		dw_udc_plug_irq();
987 
988 	while (readl(&udc_regs_p->dev_int))
989 		dw_udc_dev_irq();
990 
991 	if (readl(&udc_regs_p->endp_int))
992 		dw_udc_endpoint_irq();
993 }
994 
995 /* Flow control */
996 void udc_set_nak(int epid)
997 {
998 	writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
999 	       &inep_regs_p[epid].endp_cntl);
1000 
1001 	writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
1002 	       &outep_regs_p[epid].endp_cntl);
1003 }
1004 
1005 void udc_unset_nak(int epid)
1006 {
1007 	u32 val;
1008 
1009 	val = readl(&inep_regs_p[epid].endp_cntl);
1010 	val &= ~ENDP_CNTL_SNAK;
1011 	val |= ENDP_CNTL_CNAK;
1012 	writel(val, &inep_regs_p[epid].endp_cntl);
1013 
1014 	val = readl(&outep_regs_p[epid].endp_cntl);
1015 	val &= ~ENDP_CNTL_SNAK;
1016 	val |= ENDP_CNTL_CNAK;
1017 	writel(val, &outep_regs_p[epid].endp_cntl);
1018 }
1019