1 /* 2 * Based on drivers/usb/gadget/omap1510_udc.c 3 * TI OMAP1510 USB bus interface driver 4 * 5 * (C) Copyright 2009 6 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/io.h> 29 30 #include <usbdevice.h> 31 #include "ep0.h" 32 #include <usb/designware_udc.h> 33 #include <asm/arch/hardware.h> 34 35 #define UDC_INIT_MDELAY 80 /* Device settle delay */ 36 37 /* Some kind of debugging output... */ 38 #ifndef DEBUG_DWUSBTTY 39 #define UDCDBG(str) 40 #define UDCDBGA(fmt, args...) 41 #else 42 #define UDCDBG(str) serial_printf(str "\n") 43 #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args) 44 #endif 45 46 static struct urb *ep0_urb; 47 static struct usb_device_instance *udc_device; 48 49 static struct plug_regs *const plug_regs_p = 50 (struct plug_regs * const)CONFIG_SYS_PLUG_BASE; 51 static struct udc_regs *const udc_regs_p = 52 (struct udc_regs * const)CONFIG_SYS_USBD_BASE; 53 static struct udc_endp_regs *const outep_regs_p = 54 &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0]; 55 static struct udc_endp_regs *const inep_regs_p = 56 &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0]; 57 58 /* 59 * udc_state_transition - Write the next packet to TxFIFO. 60 * @initial: Initial state. 61 * @final: Final state. 62 * 63 * Helper function to implement device state changes. The device states and 64 * the events that transition between them are: 65 * 66 * STATE_ATTACHED 67 * || /\ 68 * \/ || 69 * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET 70 * || /\ 71 * \/ || 72 * STATE_POWERED 73 * || /\ 74 * \/ || 75 * DEVICE_RESET DEVICE_POWER_INTERRUPTION 76 * || /\ 77 * \/ || 78 * STATE_DEFAULT 79 * || /\ 80 * \/ || 81 * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET 82 * || /\ 83 * \/ || 84 * STATE_ADDRESSED 85 * || /\ 86 * \/ || 87 * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED 88 * || /\ 89 * \/ || 90 * STATE_CONFIGURED 91 * 92 * udc_state_transition transitions up (in the direction from STATE_ATTACHED 93 * to STATE_CONFIGURED) from the specified initial state to the specified final 94 * state, passing through each intermediate state on the way. If the initial 95 * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then 96 * no state transitions will take place. 97 * 98 * udc_state_transition also transitions down (in the direction from 99 * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the 100 * specified final state, passing through each intermediate state on the way. 101 * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final 102 * state, then no state transitions will take place. 103 * 104 * This function must only be called with interrupts disabled. 105 */ 106 static void udc_state_transition(usb_device_state_t initial, 107 usb_device_state_t final) 108 { 109 if (initial < final) { 110 switch (initial) { 111 case STATE_ATTACHED: 112 usbd_device_event_irq(udc_device, 113 DEVICE_HUB_CONFIGURED, 0); 114 if (final == STATE_POWERED) 115 break; 116 case STATE_POWERED: 117 usbd_device_event_irq(udc_device, DEVICE_RESET, 0); 118 if (final == STATE_DEFAULT) 119 break; 120 case STATE_DEFAULT: 121 usbd_device_event_irq(udc_device, 122 DEVICE_ADDRESS_ASSIGNED, 0); 123 if (final == STATE_ADDRESSED) 124 break; 125 case STATE_ADDRESSED: 126 usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); 127 case STATE_CONFIGURED: 128 break; 129 default: 130 break; 131 } 132 } else if (initial > final) { 133 switch (initial) { 134 case STATE_CONFIGURED: 135 usbd_device_event_irq(udc_device, 136 DEVICE_DE_CONFIGURED, 0); 137 if (final == STATE_ADDRESSED) 138 break; 139 case STATE_ADDRESSED: 140 usbd_device_event_irq(udc_device, DEVICE_RESET, 0); 141 if (final == STATE_DEFAULT) 142 break; 143 case STATE_DEFAULT: 144 usbd_device_event_irq(udc_device, 145 DEVICE_POWER_INTERRUPTION, 0); 146 if (final == STATE_POWERED) 147 break; 148 case STATE_POWERED: 149 usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); 150 case STATE_ATTACHED: 151 break; 152 default: 153 break; 154 } 155 } 156 } 157 158 /* Stall endpoint */ 159 static void udc_stall_ep(u32 ep_num) 160 { 161 writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, 162 &inep_regs_p[ep_num].endp_cntl); 163 164 writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, 165 &outep_regs_p[ep_num].endp_cntl); 166 } 167 168 static void *get_fifo(int ep_num, int in) 169 { 170 u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE; 171 172 switch (ep_num) { 173 case UDC_EP3: 174 fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); 175 /* break intentionally left out */ 176 177 case UDC_EP1: 178 fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); 179 /* break intentionally left out */ 180 181 case UDC_EP0: 182 default: 183 if (in) { 184 fifo_ptr += 185 readl(&outep_regs_p[2].endp_maxpacksize) >> 16; 186 /* break intentionally left out */ 187 } else { 188 break; 189 } 190 191 case UDC_EP2: 192 fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; 193 /* break intentionally left out */ 194 } 195 196 return (void *)fifo_ptr; 197 } 198 199 static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len) 200 { 201 u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0); 202 u32 i, nw, nb; 203 u32 *wrdp; 204 u8 *bytp; 205 u32 tmp[128]; 206 207 if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) 208 return -1; 209 210 nw = len / sizeof(u32); 211 nb = len % sizeof(u32); 212 213 /* use tmp buf if bufp is not word aligned */ 214 if ((int)bufp & 0x3) 215 wrdp = (u32 *)&tmp[0]; 216 else 217 wrdp = (u32 *)bufp; 218 219 for (i = 0; i < nw; i++) { 220 writel(readl(fifo_ptr), wrdp); 221 wrdp++; 222 } 223 224 bytp = (u8 *)wrdp; 225 for (i = 0; i < nb; i++) { 226 writeb(readb(fifo_ptr), bytp); 227 fifo_ptr++; 228 bytp++; 229 } 230 readl(&outep_regs_p[epNum].write_done); 231 232 /* copy back tmp buffer to bufp if bufp is not word aligned */ 233 if ((int)bufp & 0x3) 234 memcpy(bufp, tmp, len); 235 236 return 0; 237 } 238 239 static void usbputpcktofifo(int epNum, u8 *bufp, u32 len) 240 { 241 u32 i, nw, nb; 242 u32 *wrdp; 243 u8 *bytp; 244 u8 *fifo_ptr = get_fifo(epNum, 1); 245 246 nw = len / sizeof(int); 247 nb = len % sizeof(int); 248 wrdp = (u32 *)bufp; 249 for (i = 0; i < nw; i++) { 250 writel(*wrdp, fifo_ptr); 251 wrdp++; 252 } 253 254 bytp = (u8 *)wrdp; 255 for (i = 0; i < nb; i++) { 256 writeb(*bytp, fifo_ptr); 257 fifo_ptr++; 258 bytp++; 259 } 260 } 261 262 /* 263 * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO. 264 * @endpoint: Endpoint pointer. 265 * 266 * If the endpoint has an active tx_urb, then the next packet of data from the 267 * URB is written to the tx FIFO. The total amount of data in the urb is given 268 * by urb->actual_length. The maximum amount of data that can be sent in any 269 * one packet is given by endpoint->tx_packetSize. The number of data bytes 270 * from this URB that have already been transmitted is given by endpoint->sent. 271 * endpoint->last is updated by this routine with the number of data bytes 272 * transmitted in this packet. 273 * 274 */ 275 static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance 276 *endpoint) 277 { 278 struct urb *urb = endpoint->tx_urb; 279 int align; 280 281 if (urb) { 282 u32 last; 283 284 UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d", 285 urb->buffer, urb->buffer_length, urb->actual_length); 286 287 last = MIN(urb->actual_length - endpoint->sent, 288 endpoint->tx_packetSize); 289 290 if (last) { 291 u8 *cp = urb->buffer + endpoint->sent; 292 293 /* 294 * This ensures that USBD packet fifo is accessed 295 * - through word aligned pointer or 296 * - through non word aligned pointer but only 297 * with a max length to make the next packet 298 * word aligned 299 */ 300 301 align = ((ulong)cp % sizeof(int)); 302 if (align) 303 last = MIN(last, sizeof(int) - align); 304 305 UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d", 306 endpoint->sent, endpoint->tx_packetSize, last); 307 308 usbputpcktofifo(endpoint->endpoint_address & 309 USB_ENDPOINT_NUMBER_MASK, cp, last); 310 } 311 endpoint->last = last; 312 } 313 } 314 315 /* 316 * Handle SETUP USB interrupt. 317 * This function implements TRM Figure 14-14. 318 */ 319 static void dw_udc_setup(struct usb_endpoint_instance *endpoint) 320 { 321 u8 *datap = (u8 *)&ep0_urb->device_request; 322 int ep_addr = endpoint->endpoint_address; 323 324 UDCDBG("-> Entering device setup"); 325 usbgetpckfromfifo(ep_addr, datap, 8); 326 327 /* Try to process setup packet */ 328 if (ep0_recv_setup(ep0_urb)) { 329 /* Not a setup packet, stall next EP0 transaction */ 330 udc_stall_ep(0); 331 UDCDBG("can't parse setup packet, still waiting for setup"); 332 return; 333 } 334 335 /* Check direction */ 336 if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) 337 == USB_REQ_HOST2DEVICE) { 338 UDCDBG("control write on EP0"); 339 if (le16_to_cpu(ep0_urb->device_request.wLength)) { 340 /* Stall this request */ 341 UDCDBG("Stalling unsupported EP0 control write data " 342 "stage."); 343 udc_stall_ep(0); 344 } 345 } else { 346 347 UDCDBG("control read on EP0"); 348 /* 349 * The ep0_recv_setup function has already placed our response 350 * packet data in ep0_urb->buffer and the packet length in 351 * ep0_urb->actual_length. 352 */ 353 endpoint->tx_urb = ep0_urb; 354 endpoint->sent = 0; 355 /* 356 * Write packet data to the FIFO. dw_write_noniso_tx_fifo 357 * will update endpoint->last with the number of bytes written 358 * to the FIFO. 359 */ 360 dw_write_noniso_tx_fifo(endpoint); 361 362 writel(0x0, &inep_regs_p[ep_addr].write_done); 363 } 364 365 udc_unset_nak(endpoint->endpoint_address); 366 367 UDCDBG("<- Leaving device setup"); 368 } 369 370 /* 371 * Handle endpoint 0 RX interrupt 372 */ 373 static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint) 374 { 375 u8 dummy[64]; 376 377 UDCDBG("RX on EP0"); 378 379 /* Check direction */ 380 if ((ep0_urb->device_request.bmRequestType 381 & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { 382 /* 383 * This rx interrupt must be for a control write data 384 * stage packet. 385 * 386 * We don't support control write data stages. 387 * We should never end up here. 388 */ 389 390 UDCDBG("Stalling unexpected EP0 control write " 391 "data stage packet"); 392 udc_stall_ep(0); 393 } else { 394 /* 395 * This rx interrupt must be for a control read status 396 * stage packet. 397 */ 398 UDCDBG("ACK on EP0 control read status stage packet"); 399 u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; 400 usbgetpckfromfifo(0, dummy, len); 401 } 402 } 403 404 /* 405 * Handle endpoint 0 TX interrupt 406 */ 407 static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint) 408 { 409 struct usb_device_request *request = &ep0_urb->device_request; 410 int ep_addr; 411 412 UDCDBG("TX on EP0"); 413 414 /* Check direction */ 415 if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == 416 USB_REQ_HOST2DEVICE) { 417 /* 418 * This tx interrupt must be for a control write status 419 * stage packet. 420 */ 421 UDCDBG("ACK on EP0 control write status stage packet"); 422 } else { 423 /* 424 * This tx interrupt must be for a control read data 425 * stage packet. 426 */ 427 int wLength = le16_to_cpu(request->wLength); 428 429 /* 430 * Update our count of bytes sent so far in this 431 * transfer. 432 */ 433 endpoint->sent += endpoint->last; 434 435 /* 436 * We are finished with this transfer if we have sent 437 * all of the bytes in our tx urb (urb->actual_length) 438 * unless we need a zero-length terminating packet. We 439 * need a zero-length terminating packet if we returned 440 * fewer bytes than were requested (wLength) by the host, 441 * and the number of bytes we returned is an exact 442 * multiple of the packet size endpoint->tx_packetSize. 443 */ 444 if ((endpoint->sent == ep0_urb->actual_length) && 445 ((ep0_urb->actual_length == wLength) || 446 (endpoint->last != endpoint->tx_packetSize))) { 447 /* Done with control read data stage. */ 448 UDCDBG("control read data stage complete"); 449 } else { 450 /* 451 * We still have another packet of data to send 452 * in this control read data stage or else we 453 * need a zero-length terminating packet. 454 */ 455 UDCDBG("ACK control read data stage packet"); 456 dw_write_noniso_tx_fifo(endpoint); 457 458 ep_addr = endpoint->endpoint_address; 459 writel(0x0, &inep_regs_p[ep_addr].write_done); 460 } 461 } 462 } 463 464 static struct usb_endpoint_instance *dw_find_ep(int ep) 465 { 466 int i; 467 468 for (i = 0; i < udc_device->bus->max_endpoints; i++) { 469 if ((udc_device->bus->endpoint_array[i].endpoint_address & 470 USB_ENDPOINT_NUMBER_MASK) == ep) 471 return &udc_device->bus->endpoint_array[i]; 472 } 473 return NULL; 474 } 475 476 /* 477 * Handle RX transaction on non-ISO endpoint. 478 * The ep argument is a physical endpoint number for a non-ISO IN endpoint 479 * in the range 1 to 15. 480 */ 481 static void dw_udc_epn_rx(int ep) 482 { 483 int nbytes = 0; 484 struct urb *urb; 485 struct usb_endpoint_instance *endpoint = dw_find_ep(ep); 486 487 if (endpoint) { 488 urb = endpoint->rcv_urb; 489 490 if (urb) { 491 u8 *cp = urb->buffer + urb->actual_length; 492 493 nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) & 494 0xfff; 495 usbgetpckfromfifo(ep, cp, nbytes); 496 usbd_rcv_complete(endpoint, nbytes, 0); 497 } 498 } 499 } 500 501 /* 502 * Handle TX transaction on non-ISO endpoint. 503 * The ep argument is a physical endpoint number for a non-ISO IN endpoint 504 * in the range 16 to 30. 505 */ 506 static void dw_udc_epn_tx(int ep) 507 { 508 struct usb_endpoint_instance *endpoint = dw_find_ep(ep); 509 510 if (!endpoint) 511 return; 512 513 /* 514 * We need to transmit a terminating zero-length packet now if 515 * we have sent all of the data in this URB and the transfer 516 * size was an exact multiple of the packet size. 517 */ 518 if (endpoint->tx_urb && 519 (endpoint->last == endpoint->tx_packetSize) && 520 (endpoint->tx_urb->actual_length - endpoint->sent - 521 endpoint->last == 0)) { 522 /* handle zero length packet here */ 523 writel(0x0, &inep_regs_p[ep].write_done); 524 525 } 526 527 if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { 528 /* retire the data that was just sent */ 529 usbd_tx_complete(endpoint); 530 /* 531 * Check to see if we have more data ready to transmit 532 * now. 533 */ 534 if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { 535 /* write data to FIFO */ 536 dw_write_noniso_tx_fifo(endpoint); 537 writel(0x0, &inep_regs_p[ep].write_done); 538 539 } else if (endpoint->tx_urb 540 && (endpoint->tx_urb->actual_length == 0)) { 541 /* udc_set_nak(ep); */ 542 } 543 } 544 } 545 546 /* 547 * Start of public functions. 548 */ 549 550 /* Called to start packet transmission. */ 551 int udc_endpoint_write(struct usb_endpoint_instance *endpoint) 552 { 553 udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK); 554 return 0; 555 } 556 557 /* Start to initialize h/w stuff */ 558 int udc_init(void) 559 { 560 int i; 561 u32 plug_st; 562 563 udc_device = NULL; 564 565 UDCDBG("starting"); 566 567 readl(&plug_regs_p->plug_pending); 568 569 for (i = 0; i < UDC_INIT_MDELAY; i++) 570 udelay(1000); 571 572 plug_st = readl(&plug_regs_p->plug_state); 573 writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state); 574 575 writel(~0x0, &udc_regs_p->endp_int); 576 writel(~0x0, &udc_regs_p->dev_int_mask); 577 writel(~0x0, &udc_regs_p->endp_int_mask); 578 579 #ifndef CONFIG_USBD_HS 580 writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | 581 DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf); 582 #else 583 writel(DEV_CONF_HS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | 584 DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf); 585 #endif 586 587 writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl); 588 589 /* Clear all interrupts pending */ 590 writel(DEV_INT_MSK, &udc_regs_p->dev_int); 591 592 return 0; 593 } 594 595 int is_usbd_high_speed(void) 596 { 597 return (readl(&udc_regs_p->dev_stat) & DEV_STAT_ENUM) ? 0 : 1; 598 } 599 600 /* 601 * udc_setup_ep - setup endpoint 602 * Associate a physical endpoint with endpoint_instance 603 */ 604 void udc_setup_ep(struct usb_device_instance *device, 605 u32 ep, struct usb_endpoint_instance *endpoint) 606 { 607 UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address); 608 int ep_addr; 609 int ep_num, ep_type; 610 int packet_size; 611 int buffer_size; 612 int attributes; 613 char *tt; 614 u32 endp_intmask; 615 616 if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED)) 617 return; 618 619 tt = getenv("usbtty"); 620 if (!tt) 621 tt = "generic"; 622 623 ep_addr = endpoint->endpoint_address; 624 ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; 625 626 if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { 627 /* IN endpoint */ 628 packet_size = endpoint->tx_packetSize; 629 buffer_size = packet_size * 2; 630 attributes = endpoint->tx_attributes; 631 } else { 632 /* OUT endpoint */ 633 packet_size = endpoint->rcv_packetSize; 634 buffer_size = packet_size * 2; 635 attributes = endpoint->rcv_attributes; 636 } 637 638 switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { 639 case USB_ENDPOINT_XFER_CONTROL: 640 ep_type = ENDP_EPTYPE_CNTL; 641 break; 642 case USB_ENDPOINT_XFER_BULK: 643 default: 644 ep_type = ENDP_EPTYPE_BULK; 645 break; 646 case USB_ENDPOINT_XFER_INT: 647 ep_type = ENDP_EPTYPE_INT; 648 break; 649 case USB_ENDPOINT_XFER_ISOC: 650 ep_type = ENDP_EPTYPE_ISO; 651 break; 652 } 653 654 struct udc_endp_regs *out_p = &outep_regs_p[ep_num]; 655 struct udc_endp_regs *in_p = &inep_regs_p[ep_num]; 656 657 if (!ep_addr) { 658 /* Setup endpoint 0 */ 659 buffer_size = packet_size; 660 661 writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK, 662 &in_p->endp_cntl); 663 664 writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK, 665 &out_p->endp_cntl); 666 667 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl); 668 669 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); 670 671 writel(packet_size, &in_p->endp_maxpacksize); 672 673 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl); 674 675 writel(packet_size | ((buffer_size / sizeof(int)) << 16), 676 &out_p->endp_maxpacksize); 677 678 } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { 679 /* Setup the IN endpoint */ 680 writel(0x0, &in_p->endp_status); 681 writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl); 682 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); 683 writel(packet_size, &in_p->endp_maxpacksize); 684 685 if (!strcmp(tt, "cdc_acm")) { 686 if (ep_type == ENDP_EPTYPE_INT) { 687 /* Conf no. 1 Interface no. 0 */ 688 writel((packet_size << 19) | 689 ENDP_EPDIR_IN | (1 << 7) | 690 (0 << 11) | (ep_type << 5) | ep_num, 691 &udc_regs_p->udc_endp_reg[ep_num]); 692 } else { 693 /* Conf no. 1 Interface no. 1 */ 694 writel((packet_size << 19) | 695 ENDP_EPDIR_IN | (1 << 7) | 696 (1 << 11) | (ep_type << 5) | ep_num, 697 &udc_regs_p->udc_endp_reg[ep_num]); 698 } 699 } else { 700 /* Conf no. 1 Interface no. 0 */ 701 writel((packet_size << 19) | 702 ENDP_EPDIR_IN | (1 << 7) | 703 (0 << 11) | (ep_type << 5) | ep_num, 704 &udc_regs_p->udc_endp_reg[ep_num]); 705 } 706 707 } else { 708 /* Setup the OUT endpoint */ 709 writel(0x0, &out_p->endp_status); 710 writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl); 711 writel(packet_size | ((buffer_size / sizeof(int)) << 16), 712 &out_p->endp_maxpacksize); 713 714 if (!strcmp(tt, "cdc_acm")) { 715 writel((packet_size << 19) | 716 ENDP_EPDIR_OUT | (1 << 7) | 717 (1 << 11) | (ep_type << 5) | ep_num, 718 &udc_regs_p->udc_endp_reg[ep_num]); 719 } else { 720 writel((packet_size << 19) | 721 ENDP_EPDIR_OUT | (1 << 7) | 722 (0 << 11) | (ep_type << 5) | ep_num, 723 &udc_regs_p->udc_endp_reg[ep_num]); 724 } 725 726 } 727 728 endp_intmask = readl(&udc_regs_p->endp_int_mask); 729 endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num); 730 writel(endp_intmask, &udc_regs_p->endp_int_mask); 731 } 732 733 /* Turn on the USB connection by enabling the pullup resistor */ 734 void udc_connect(void) 735 { 736 u32 plug_st, dev_cntl; 737 738 dev_cntl = readl(&udc_regs_p->dev_cntl); 739 dev_cntl |= DEV_CNTL_SOFTDISCONNECT; 740 writel(dev_cntl, &udc_regs_p->dev_cntl); 741 742 udelay(1000); 743 744 dev_cntl = readl(&udc_regs_p->dev_cntl); 745 dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT; 746 writel(dev_cntl, &udc_regs_p->dev_cntl); 747 748 plug_st = readl(&plug_regs_p->plug_state); 749 plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); 750 writel(plug_st, &plug_regs_p->plug_state); 751 } 752 753 /* Turn off the USB connection by disabling the pullup resistor */ 754 void udc_disconnect(void) 755 { 756 u32 plug_st; 757 758 writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl); 759 760 plug_st = readl(&plug_regs_p->plug_state); 761 plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); 762 writel(plug_st, &plug_regs_p->plug_state); 763 } 764 765 /* Switch on the UDC */ 766 void udc_enable(struct usb_device_instance *device) 767 { 768 UDCDBGA("enable device %p, status %d", device, device->status); 769 770 /* Save the device structure pointer */ 771 udc_device = device; 772 773 /* Setup ep0 urb */ 774 if (!ep0_urb) { 775 ep0_urb = 776 usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array); 777 } else { 778 serial_printf("udc_enable: ep0_urb already allocated %p\n", 779 ep0_urb); 780 } 781 782 writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); 783 } 784 785 /** 786 * udc_startup - allow udc code to do any additional startup 787 */ 788 void udc_startup_events(struct usb_device_instance *device) 789 { 790 /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ 791 usbd_device_event_irq(device, DEVICE_INIT, 0); 792 793 /* 794 * The DEVICE_CREATE event puts the USB device in the state 795 * STATE_ATTACHED. 796 */ 797 usbd_device_event_irq(device, DEVICE_CREATE, 0); 798 799 /* 800 * Some USB controller driver implementations signal 801 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. 802 * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, 803 * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. 804 * The DW USB client controller has the capability to detect when the 805 * USB cable is connected to a powered USB bus, so we will defer the 806 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later. 807 */ 808 809 udc_enable(device); 810 } 811 812 /* 813 * Plug detection interrupt handling 814 */ 815 static void dw_udc_plug_irq(void) 816 { 817 if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) { 818 /* 819 * USB cable attached 820 * Turn off PHY reset bit (PLUG detect). 821 * Switch PHY opmode to normal operation (PLUG detect). 822 */ 823 udc_connect(); 824 writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); 825 826 UDCDBG("device attached and powered"); 827 udc_state_transition(udc_device->device_state, STATE_POWERED); 828 } else { 829 writel(~0x0, &udc_regs_p->dev_int_mask); 830 831 UDCDBG("device detached or unpowered"); 832 udc_state_transition(udc_device->device_state, STATE_ATTACHED); 833 } 834 } 835 836 /* 837 * Device interrupt handling 838 */ 839 static void dw_udc_dev_irq(void) 840 { 841 if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { 842 writel(~0x0, &udc_regs_p->endp_int_mask); 843 844 writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH, 845 &inep_regs_p[0].endp_cntl); 846 847 writel(DEV_INT_USBRESET, &udc_regs_p->dev_int); 848 849 /* 850 * This endpoint0 specific register can be programmed only 851 * after the phy clock is initialized 852 */ 853 writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL, 854 &udc_regs_p->udc_endp_reg[0]); 855 856 UDCDBG("device reset in progess"); 857 udc_state_transition(udc_device->device_state, STATE_DEFAULT); 858 } 859 860 /* Device Enumeration completed */ 861 if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) { 862 writel(DEV_INT_ENUM, &udc_regs_p->dev_int); 863 864 /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */ 865 writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001, 866 &udc_regs_p->endp_int_mask); 867 868 UDCDBG("default -> addressed"); 869 udc_state_transition(udc_device->device_state, STATE_ADDRESSED); 870 } 871 872 /* The USB will be in SUSPEND in 3 ms */ 873 if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) { 874 writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int); 875 876 UDCDBG("entering inactive state"); 877 /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */ 878 } 879 880 /* SetConfiguration command received */ 881 if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) { 882 writel(DEV_INT_SETCFG, &udc_regs_p->dev_int); 883 884 UDCDBG("entering configured state"); 885 udc_state_transition(udc_device->device_state, 886 STATE_CONFIGURED); 887 } 888 889 /* SetInterface command received */ 890 if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF) 891 writel(DEV_INT_SETINTF, &udc_regs_p->dev_int); 892 893 /* USB Suspend detected on cable */ 894 if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) { 895 writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int); 896 897 UDCDBG("entering suspended state"); 898 usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); 899 } 900 901 /* USB Start-Of-Frame detected on cable */ 902 if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF) 903 writel(DEV_INT_SOF, &udc_regs_p->dev_int); 904 } 905 906 /* 907 * Endpoint interrupt handling 908 */ 909 static void dw_udc_endpoint_irq(void) 910 { 911 while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) { 912 913 writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int); 914 915 if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) 916 == ENDP_STATUS_OUT_SETUP) { 917 dw_udc_setup(udc_device->bus->endpoint_array + 0); 918 writel(ENDP_STATUS_OUT_SETUP, 919 &outep_regs_p[0].endp_status); 920 921 } else if ((readl(&outep_regs_p[0].endp_status) & 922 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { 923 dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0); 924 writel(ENDP_STATUS_OUT_DATA, 925 &outep_regs_p[0].endp_status); 926 927 } else if ((readl(&outep_regs_p[0].endp_status) & 928 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { 929 /* NONE received */ 930 } 931 932 writel(0x0, &outep_regs_p[0].endp_status); 933 } 934 935 if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) { 936 dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0); 937 938 writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status); 939 writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); 940 } 941 942 if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { 943 u32 epnum = 0; 944 u32 ep_int = readl(&udc_regs_p->endp_int) & 945 ENDP_INT_NONISOOUT_MSK; 946 947 ep_int >>= 16; 948 while (0x0 == (ep_int & 0x1)) { 949 ep_int >>= 1; 950 epnum++; 951 } 952 953 writel((1 << 16) << epnum, &udc_regs_p->endp_int); 954 955 if ((readl(&outep_regs_p[epnum].endp_status) & 956 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { 957 958 dw_udc_epn_rx(epnum); 959 writel(ENDP_STATUS_OUT_DATA, 960 &outep_regs_p[epnum].endp_status); 961 } else if ((readl(&outep_regs_p[epnum].endp_status) & 962 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { 963 writel(0x0, &outep_regs_p[epnum].endp_status); 964 } 965 } 966 967 if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) { 968 u32 epnum = 0; 969 u32 ep_int = readl(&udc_regs_p->endp_int) & 970 ENDP_INT_NONISOIN_MSK; 971 972 while (0x0 == (ep_int & 0x1)) { 973 ep_int >>= 1; 974 epnum++; 975 } 976 977 if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) { 978 writel(ENDP_STATUS_IN, 979 &outep_regs_p[epnum].endp_status); 980 dw_udc_epn_tx(epnum); 981 982 writel(ENDP_STATUS_IN, 983 &outep_regs_p[epnum].endp_status); 984 } 985 986 writel((1 << epnum), &udc_regs_p->endp_int); 987 } 988 } 989 990 /* 991 * UDC interrupts 992 */ 993 void udc_irq(void) 994 { 995 /* 996 * Loop while we have interrupts. 997 * If we don't do this, the input chain 998 * polling delay is likely to miss 999 * host requests. 1000 */ 1001 while (readl(&plug_regs_p->plug_pending)) 1002 dw_udc_plug_irq(); 1003 1004 while (readl(&udc_regs_p->dev_int)) 1005 dw_udc_dev_irq(); 1006 1007 if (readl(&udc_regs_p->endp_int)) 1008 dw_udc_endpoint_irq(); 1009 } 1010 1011 /* Flow control */ 1012 void udc_set_nak(int epid) 1013 { 1014 writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, 1015 &inep_regs_p[epid].endp_cntl); 1016 1017 writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, 1018 &outep_regs_p[epid].endp_cntl); 1019 } 1020 1021 void udc_unset_nak(int epid) 1022 { 1023 u32 val; 1024 1025 val = readl(&inep_regs_p[epid].endp_cntl); 1026 val &= ~ENDP_CNTL_SNAK; 1027 val |= ENDP_CNTL_CNAK; 1028 writel(val, &inep_regs_p[epid].endp_cntl); 1029 1030 val = readl(&outep_regs_p[epid].endp_cntl); 1031 val &= ~ENDP_CNTL_SNAK; 1032 val |= ENDP_CNTL_CNAK; 1033 writel(val, &outep_regs_p[epid].endp_cntl); 1034 } 1035