xref: /openbmc/u-boot/drivers/usb/gadget/ci_udc.c (revision 7ca6f363)
1 /*
2  * Copyright 2011, Marvell Semiconductor Inc.
3  * Lei Wen <leiwen@marvell.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  *
7  * Back ported to the 8xx platform (from the 8260 platform) by
8  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9  */
10 
11 #include <common.h>
12 #include <command.h>
13 #include <config.h>
14 #include <net.h>
15 #include <malloc.h>
16 #include <asm/byteorder.h>
17 #include <asm/errno.h>
18 #include <asm/io.h>
19 #include <asm/unaligned.h>
20 #include <linux/types.h>
21 #include <linux/usb/ch9.h>
22 #include <linux/usb/gadget.h>
23 #include <usb/ci_udc.h>
24 #include "../host/ehci.h"
25 #include "ci_udc.h"
26 
27 /*
28  * Check if the system has too long cachelines. If the cachelines are
29  * longer then 128b, the driver will not be able flush/invalidate data
30  * cache over separate QH entries. We use 128b because one QH entry is
31  * 64b long and there are always two QH list entries for each endpoint.
32  */
33 #if ARCH_DMA_MINALIGN > 128
34 #error This driver can not work on systems with caches longer than 128b
35 #endif
36 
37 #ifndef DEBUG
38 #define DBG(x...) do {} while (0)
39 #else
40 #define DBG(x...) printf(x)
41 static const char *reqname(unsigned r)
42 {
43 	switch (r) {
44 	case USB_REQ_GET_STATUS: return "GET_STATUS";
45 	case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
46 	case USB_REQ_SET_FEATURE: return "SET_FEATURE";
47 	case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
48 	case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
49 	case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
50 	case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
51 	case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
52 	case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
53 	case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
54 	default: return "*UNKNOWN*";
55 	}
56 }
57 #endif
58 
59 static struct usb_endpoint_descriptor ep0_out_desc = {
60 	.bLength = sizeof(struct usb_endpoint_descriptor),
61 	.bDescriptorType = USB_DT_ENDPOINT,
62 	.bEndpointAddress = 0,
63 	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
64 };
65 
66 static struct usb_endpoint_descriptor ep0_in_desc = {
67 	.bLength = sizeof(struct usb_endpoint_descriptor),
68 	.bDescriptorType = USB_DT_ENDPOINT,
69 	.bEndpointAddress = USB_DIR_IN,
70 	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
71 };
72 
73 static int ci_pullup(struct usb_gadget *gadget, int is_on);
74 static int ci_ep_enable(struct usb_ep *ep,
75 		const struct usb_endpoint_descriptor *desc);
76 static int ci_ep_disable(struct usb_ep *ep);
77 static int ci_ep_queue(struct usb_ep *ep,
78 		struct usb_request *req, gfp_t gfp_flags);
79 static struct usb_request *
80 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
81 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
82 
83 static struct usb_gadget_ops ci_udc_ops = {
84 	.pullup = ci_pullup,
85 };
86 
87 static struct usb_ep_ops ci_ep_ops = {
88 	.enable         = ci_ep_enable,
89 	.disable        = ci_ep_disable,
90 	.queue          = ci_ep_queue,
91 	.alloc_request  = ci_ep_alloc_request,
92 	.free_request   = ci_ep_free_request,
93 };
94 
95 /* Init values for USB endpoints. */
96 static const struct usb_ep ci_ep_init[2] = {
97 	[0] = {	/* EP 0 */
98 		.maxpacket	= 64,
99 		.name		= "ep0",
100 		.ops		= &ci_ep_ops,
101 	},
102 	[1] = {	/* EP 1..n */
103 		.maxpacket	= 512,
104 		.name		= "ep-",
105 		.ops		= &ci_ep_ops,
106 	},
107 };
108 
109 static struct ci_drv controller = {
110 	.gadget	= {
111 		.name	= "ci_udc",
112 		.ops	= &ci_udc_ops,
113 		.is_dualspeed = 1,
114 	},
115 };
116 
117 /**
118  * ci_get_qh() - return queue head for endpoint
119  * @ep_num:	Endpoint number
120  * @dir_in:	Direction of the endpoint (IN = 1, OUT = 0)
121  *
122  * This function returns the QH associated with particular endpoint
123  * and it's direction.
124  */
125 static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in)
126 {
127 	return &controller.epts[(ep_num * 2) + dir_in];
128 }
129 
130 /**
131  * ci_get_qtd() - return queue item for endpoint
132  * @ep_num:	Endpoint number
133  * @dir_in:	Direction of the endpoint (IN = 1, OUT = 0)
134  *
135  * This function returns the QH associated with particular endpoint
136  * and it's direction.
137  */
138 static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in)
139 {
140 	return controller.items[(ep_num * 2) + dir_in];
141 }
142 
143 /**
144  * ci_flush_qh - flush cache over queue head
145  * @ep_num:	Endpoint number
146  *
147  * This function flushes cache over QH for particular endpoint.
148  */
149 static void ci_flush_qh(int ep_num)
150 {
151 	struct ept_queue_head *head = ci_get_qh(ep_num, 0);
152 	const uint32_t start = (uint32_t)head;
153 	const uint32_t end = start + 2 * sizeof(*head);
154 
155 	flush_dcache_range(start, end);
156 }
157 
158 /**
159  * ci_invalidate_qh - invalidate cache over queue head
160  * @ep_num:	Endpoint number
161  *
162  * This function invalidates cache over QH for particular endpoint.
163  */
164 static void ci_invalidate_qh(int ep_num)
165 {
166 	struct ept_queue_head *head = ci_get_qh(ep_num, 0);
167 	uint32_t start = (uint32_t)head;
168 	uint32_t end = start + 2 * sizeof(*head);
169 
170 	invalidate_dcache_range(start, end);
171 }
172 
173 /**
174  * ci_flush_qtd - flush cache over queue item
175  * @ep_num:	Endpoint number
176  *
177  * This function flushes cache over qTD pair for particular endpoint.
178  */
179 static void ci_flush_qtd(int ep_num)
180 {
181 	struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
182 	const uint32_t start = (uint32_t)item;
183 	const uint32_t end_raw = start + 2 * sizeof(*item);
184 	const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
185 
186 	flush_dcache_range(start, end);
187 }
188 
189 /**
190  * ci_invalidate_qtd - invalidate cache over queue item
191  * @ep_num:	Endpoint number
192  *
193  * This function invalidates cache over qTD pair for particular endpoint.
194  */
195 static void ci_invalidate_qtd(int ep_num)
196 {
197 	struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
198 	const uint32_t start = (uint32_t)item;
199 	const uint32_t end_raw = start + 2 * sizeof(*item);
200 	const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
201 
202 	invalidate_dcache_range(start, end);
203 }
204 
205 static struct usb_request *
206 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
207 {
208 	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
209 	return &ci_ep->req;
210 }
211 
212 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
213 {
214 	return;
215 }
216 
217 static void ep_enable(int num, int in, int maxpacket)
218 {
219 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
220 	unsigned n;
221 
222 	n = readl(&udc->epctrl[num]);
223 	if (in)
224 		n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
225 	else
226 		n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
227 
228 	if (num != 0) {
229 		struct ept_queue_head *head = ci_get_qh(num, in);
230 
231 		head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
232 		ci_flush_qh(num);
233 	}
234 	writel(n, &udc->epctrl[num]);
235 }
236 
237 static int ci_ep_enable(struct usb_ep *ep,
238 		const struct usb_endpoint_descriptor *desc)
239 {
240 	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
241 	int num, in;
242 	num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
243 	in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
244 	ci_ep->desc = desc;
245 
246 	if (num) {
247 		int max = get_unaligned_le16(&desc->wMaxPacketSize);
248 
249 		if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL))
250 			max = 64;
251 		if (ep->maxpacket != max) {
252 			DBG("%s: from %d to %d\n", __func__,
253 			    ep->maxpacket, max);
254 			ep->maxpacket = max;
255 		}
256 	}
257 	ep_enable(num, in, ep->maxpacket);
258 	DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket);
259 	return 0;
260 }
261 
262 static int ci_ep_disable(struct usb_ep *ep)
263 {
264 	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
265 
266 	ci_ep->desc = NULL;
267 	return 0;
268 }
269 
270 static int ci_bounce(struct ci_ep *ep, int in)
271 {
272 	uint32_t addr = (uint32_t)ep->req.buf;
273 	uint32_t ba;
274 
275 	/* Input buffer address is not aligned. */
276 	if (addr & (ARCH_DMA_MINALIGN - 1))
277 		goto align;
278 
279 	/* Input buffer length is not aligned. */
280 	if (ep->req.length & (ARCH_DMA_MINALIGN - 1))
281 		goto align;
282 
283 	/* The buffer is well aligned, only flush cache. */
284 	ep->b_len = ep->req.length;
285 	ep->b_buf = ep->req.buf;
286 	goto flush;
287 
288 align:
289 	/* Use internal buffer for small payloads. */
290 	if (ep->req.length <= 64) {
291 		ep->b_len = 64;
292 		ep->b_buf = ep->b_fast;
293 	} else {
294 		ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN);
295 		ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len);
296 		if (!ep->b_buf)
297 			return -ENOMEM;
298 	}
299 	if (in)
300 		memcpy(ep->b_buf, ep->req.buf, ep->req.length);
301 
302 flush:
303 	ba = (uint32_t)ep->b_buf;
304 	flush_dcache_range(ba, ba + ep->b_len);
305 
306 	return 0;
307 }
308 
309 static void ci_debounce(struct ci_ep *ep, int in)
310 {
311 	uint32_t addr = (uint32_t)ep->req.buf;
312 	uint32_t ba = (uint32_t)ep->b_buf;
313 
314 	if (in) {
315 		if (addr == ba)
316 			return;		/* not a bounce */
317 		goto free;
318 	}
319 	invalidate_dcache_range(ba, ba + ep->b_len);
320 
321 	if (addr == ba)
322 		return;		/* not a bounce */
323 
324 	memcpy(ep->req.buf, ep->b_buf, ep->req.length);
325 free:
326 	/* Large payloads use allocated buffer, free it. */
327 	if (ep->b_buf != ep->b_fast)
328 		free(ep->b_buf);
329 }
330 
331 static int ci_ep_queue(struct usb_ep *ep,
332 		struct usb_request *req, gfp_t gfp_flags)
333 {
334 	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
335 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
336 	struct ept_queue_item *item;
337 	struct ept_queue_head *head;
338 	int bit, num, len, in, ret;
339 	num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
340 	in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
341 	item = ci_get_qtd(num, in);
342 	head = ci_get_qh(num, in);
343 	len = req->length;
344 
345 	ret = ci_bounce(ci_ep, in);
346 	if (ret)
347 		return ret;
348 
349 	item->next = TERMINATE;
350 	item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
351 	item->page0 = (uint32_t)ci_ep->b_buf;
352 	item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000;
353 	ci_flush_qtd(num);
354 
355 	head->next = (unsigned) item;
356 	head->info = 0;
357 
358 	DBG("ept%d %s queue len %x, buffer %p\n",
359 	    num, in ? "in" : "out", len, ci_ep->b_buf);
360 	ci_flush_qh(num);
361 
362 	if (in)
363 		bit = EPT_TX(num);
364 	else
365 		bit = EPT_RX(num);
366 
367 	writel(bit, &udc->epprime);
368 
369 	return 0;
370 }
371 
372 static void handle_ep_complete(struct ci_ep *ep)
373 {
374 	struct ept_queue_item *item;
375 	int num, in, len;
376 	num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
377 	in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
378 	if (num == 0)
379 		ep->desc = &ep0_out_desc;
380 	item = ci_get_qtd(num, in);
381 	ci_invalidate_qtd(num);
382 
383 	if (item->info & 0xff)
384 		printf("EP%d/%s FAIL info=%x pg0=%x\n",
385 		       num, in ? "in" : "out", item->info, item->page0);
386 
387 	len = (item->info >> 16) & 0x7fff;
388 	ep->req.length -= len;
389 	ci_debounce(ep, in);
390 
391 	DBG("ept%d %s complete %x\n",
392 			num, in ? "in" : "out", len);
393 	ep->req.complete(&ep->ep, &ep->req);
394 	if (num == 0) {
395 		ep->req.length = 0;
396 		usb_ep_queue(&ep->ep, &ep->req, 0);
397 		ep->desc = &ep0_in_desc;
398 	}
399 }
400 
401 #define SETUP(type, request) (((type) << 8) | (request))
402 
403 static void handle_setup(void)
404 {
405 	struct usb_request *req = &controller.ep[0].req;
406 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
407 	struct ept_queue_head *head;
408 	struct usb_ctrlrequest r;
409 	int status = 0;
410 	int num, in, _num, _in, i;
411 	char *buf;
412 	head = ci_get_qh(0, 0);	/* EP0 OUT */
413 
414 	ci_invalidate_qh(0);
415 	memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
416 	writel(EPT_RX(0), &udc->epstat);
417 	DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
418 	    r.bRequestType, r.bRequest, r.wIndex, r.wValue);
419 
420 	switch (SETUP(r.bRequestType, r.bRequest)) {
421 	case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
422 		_num = r.wIndex & 15;
423 		_in = !!(r.wIndex & 0x80);
424 
425 		if ((r.wValue == 0) && (r.wLength == 0)) {
426 			req->length = 0;
427 			for (i = 0; i < NUM_ENDPOINTS; i++) {
428 				struct ci_ep *ep = &controller.ep[i];
429 
430 				if (!ep->desc)
431 					continue;
432 				num = ep->desc->bEndpointAddress
433 						& USB_ENDPOINT_NUMBER_MASK;
434 				in = (ep->desc->bEndpointAddress
435 						& USB_DIR_IN) != 0;
436 				if ((num == _num) && (in == _in)) {
437 					ep_enable(num, in, ep->ep.maxpacket);
438 					usb_ep_queue(controller.gadget.ep0,
439 							req, 0);
440 					break;
441 				}
442 			}
443 		}
444 		return;
445 
446 	case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
447 		/*
448 		 * write address delayed (will take effect
449 		 * after the next IN txn)
450 		 */
451 		writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
452 		req->length = 0;
453 		usb_ep_queue(controller.gadget.ep0, req, 0);
454 		return;
455 
456 	case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
457 		req->length = 2;
458 		buf = (char *)req->buf;
459 		buf[0] = 1 << USB_DEVICE_SELF_POWERED;
460 		buf[1] = 0;
461 		usb_ep_queue(controller.gadget.ep0, req, 0);
462 		return;
463 	}
464 	/* pass request up to the gadget driver */
465 	if (controller.driver)
466 		status = controller.driver->setup(&controller.gadget, &r);
467 	else
468 		status = -ENODEV;
469 
470 	if (!status)
471 		return;
472 	DBG("STALL reqname %s type %x value %x, index %x\n",
473 	    reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
474 	writel((1<<16) | (1 << 0), &udc->epctrl[0]);
475 }
476 
477 static void stop_activity(void)
478 {
479 	int i, num, in;
480 	struct ept_queue_head *head;
481 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
482 	writel(readl(&udc->epcomp), &udc->epcomp);
483 	writel(readl(&udc->epstat), &udc->epstat);
484 	writel(0xffffffff, &udc->epflush);
485 
486 	/* error out any pending reqs */
487 	for (i = 0; i < NUM_ENDPOINTS; i++) {
488 		if (i != 0)
489 			writel(0, &udc->epctrl[i]);
490 		if (controller.ep[i].desc) {
491 			num = controller.ep[i].desc->bEndpointAddress
492 				& USB_ENDPOINT_NUMBER_MASK;
493 			in = (controller.ep[i].desc->bEndpointAddress
494 				& USB_DIR_IN) != 0;
495 			head = ci_get_qh(num, in);
496 			head->info = INFO_ACTIVE;
497 			ci_flush_qh(num);
498 		}
499 	}
500 }
501 
502 void udc_irq(void)
503 {
504 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
505 	unsigned n = readl(&udc->usbsts);
506 	writel(n, &udc->usbsts);
507 	int bit, i, num, in;
508 
509 	n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
510 	if (n == 0)
511 		return;
512 
513 	if (n & STS_URI) {
514 		DBG("-- reset --\n");
515 		stop_activity();
516 	}
517 	if (n & STS_SLI)
518 		DBG("-- suspend --\n");
519 
520 	if (n & STS_PCI) {
521 		int max = 64;
522 		int speed = USB_SPEED_FULL;
523 
524 		bit = (readl(&udc->portsc) >> 26) & 3;
525 		DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
526 		if (bit == 2) {
527 			speed = USB_SPEED_HIGH;
528 			max = 512;
529 		}
530 		controller.gadget.speed = speed;
531 		for (i = 1; i < NUM_ENDPOINTS; i++) {
532 			if (controller.ep[i].ep.maxpacket > max)
533 				controller.ep[i].ep.maxpacket = max;
534 		}
535 	}
536 
537 	if (n & STS_UEI)
538 		printf("<UEI %x>\n", readl(&udc->epcomp));
539 
540 	if ((n & STS_UI) || (n & STS_UEI)) {
541 		n = readl(&udc->epstat);
542 		if (n & EPT_RX(0))
543 			handle_setup();
544 
545 		n = readl(&udc->epcomp);
546 		if (n != 0)
547 			writel(n, &udc->epcomp);
548 
549 		for (i = 0; i < NUM_ENDPOINTS && n; i++) {
550 			if (controller.ep[i].desc) {
551 				num = controller.ep[i].desc->bEndpointAddress
552 					& USB_ENDPOINT_NUMBER_MASK;
553 				in = (controller.ep[i].desc->bEndpointAddress
554 						& USB_DIR_IN) != 0;
555 				bit = (in) ? EPT_TX(num) : EPT_RX(num);
556 				if (n & bit)
557 					handle_ep_complete(&controller.ep[i]);
558 			}
559 		}
560 	}
561 }
562 
563 int usb_gadget_handle_interrupts(void)
564 {
565 	u32 value;
566 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
567 
568 	value = readl(&udc->usbsts);
569 	if (value)
570 		udc_irq();
571 
572 	return value;
573 }
574 
575 static int ci_pullup(struct usb_gadget *gadget, int is_on)
576 {
577 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
578 	if (is_on) {
579 		/* RESET */
580 		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
581 		udelay(200);
582 
583 		writel((unsigned)controller.epts, &udc->epinitaddr);
584 
585 		/* select DEVICE mode */
586 		writel(USBMODE_DEVICE, &udc->usbmode);
587 
588 		writel(0xffffffff, &udc->epflush);
589 
590 		/* Turn on the USB connection by enabling the pullup resistor */
591 		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
592 	} else {
593 		stop_activity();
594 		writel(USBCMD_FS2, &udc->usbcmd);
595 		udelay(800);
596 		if (controller.driver)
597 			controller.driver->disconnect(gadget);
598 	}
599 
600 	return 0;
601 }
602 
603 void udc_disconnect(void)
604 {
605 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
606 	/* disable pullup */
607 	stop_activity();
608 	writel(USBCMD_FS2, &udc->usbcmd);
609 	udelay(800);
610 	if (controller.driver)
611 		controller.driver->disconnect(&controller.gadget);
612 }
613 
614 static int ci_udc_probe(void)
615 {
616 	struct ept_queue_head *head;
617 	uint8_t *imem;
618 	int i;
619 
620 	const int num = 2 * NUM_ENDPOINTS;
621 
622 	const int eplist_min_align = 4096;
623 	const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
624 	const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
625 	const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
626 
627 	const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32);
628 	const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item);
629 	const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN);
630 	const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz;
631 
632 	/* The QH list must be aligned to 4096 bytes. */
633 	controller.epts = memalign(eplist_align, eplist_sz);
634 	if (!controller.epts)
635 		return -ENOMEM;
636 	memset(controller.epts, 0, eplist_sz);
637 
638 	/*
639 	 * Each qTD item must be 32-byte aligned, each qTD touple must be
640 	 * cacheline aligned. There are two qTD items for each endpoint and
641 	 * only one of them is used for the endpoint at time, so we can group
642 	 * them together.
643 	 */
644 	controller.items_mem = memalign(ilist_align, ilist_sz);
645 	if (!controller.items_mem) {
646 		free(controller.epts);
647 		return -ENOMEM;
648 	}
649 	memset(controller.items_mem, 0, ilist_sz);
650 
651 	for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
652 		/*
653 		 * Configure QH for each endpoint. The structure of the QH list
654 		 * is such that each two subsequent fields, N and N+1 where N is
655 		 * even, in the QH list represent QH for one endpoint. The Nth
656 		 * entry represents OUT configuration and the N+1th entry does
657 		 * represent IN configuration of the endpoint.
658 		 */
659 		head = controller.epts + i;
660 		if (i < 2)
661 			head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
662 				| CONFIG_ZLT | CONFIG_IOS;
663 		else
664 			head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
665 				| CONFIG_ZLT;
666 		head->next = TERMINATE;
667 		head->info = 0;
668 
669 		imem = controller.items_mem + ((i >> 1) * ilist_ent_sz);
670 		if (i & 1)
671 			imem += sizeof(struct ept_queue_item);
672 
673 		controller.items[i] = (struct ept_queue_item *)imem;
674 
675 		if (i & 1) {
676 			ci_flush_qh(i - 1);
677 			ci_flush_qtd(i - 1);
678 		}
679 	}
680 
681 	INIT_LIST_HEAD(&controller.gadget.ep_list);
682 
683 	/* Init EP 0 */
684 	memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
685 	controller.ep[0].desc = &ep0_in_desc;
686 	controller.gadget.ep0 = &controller.ep[0].ep;
687 	INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
688 
689 	/* Init EP 1..n */
690 	for (i = 1; i < NUM_ENDPOINTS; i++) {
691 		memcpy(&controller.ep[i].ep, &ci_ep_init[1],
692 		       sizeof(*ci_ep_init));
693 		list_add_tail(&controller.ep[i].ep.ep_list,
694 			      &controller.gadget.ep_list);
695 	}
696 
697 	return 0;
698 }
699 
700 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
701 {
702 	struct ci_udc *udc;
703 	int ret;
704 
705 	if (!driver)
706 		return -EINVAL;
707 	if (!driver->bind || !driver->setup || !driver->disconnect)
708 		return -EINVAL;
709 	if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
710 		return -EINVAL;
711 
712 	ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl);
713 	if (ret)
714 		return ret;
715 
716 	ret = ci_udc_probe();
717 	if (!ret) {
718 		udc = (struct ci_udc *)controller.ctrl->hcor;
719 
720 		/* select ULPI phy */
721 		writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
722 	}
723 
724 	ret = driver->bind(&controller.gadget);
725 	if (ret) {
726 		DBG("driver->bind() returned %d\n", ret);
727 		return ret;
728 	}
729 	controller.driver = driver;
730 
731 	return 0;
732 }
733 
734 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
735 {
736 	return 0;
737 }
738