1 /* 2 * Copyright 2015 Broadcom Corporation. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/sysmap.h> 11 #include <asm/kona-common/clk.h> 12 13 #include "dwc2_udc_otg_priv.h" 14 #include "bcm_udc_otg.h" 15 16 void otg_phy_init(struct dwc2_udc *dev) 17 { 18 /* turn on the USB OTG clocks */ 19 clk_usb_otg_enable((void *)HSOTG_BASE_ADDR); 20 21 /* set Phy to driving mode */ 22 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 23 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 24 25 udelay(100); 26 27 /* clear Soft Disconnect */ 28 wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 29 HSOTG_DCTL_SFTDISCON_MASK); 30 31 /* invoke Reset (active low) */ 32 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 33 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 34 35 /* Reset needs to be asserted for 2ms */ 36 udelay(2000); 37 38 /* release Reset */ 39 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 40 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK, 41 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 42 } 43 44 void otg_phy_off(struct dwc2_udc *dev) 45 { 46 /* Soft Disconnect */ 47 wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 48 HSOTG_DCTL_SFTDISCON_MASK, 49 HSOTG_DCTL_SFTDISCON_MASK); 50 51 /* set Phy to non-driving (reset) mode */ 52 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 53 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK, 54 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 55 } 56