1 /* 2 * Register definition for Atmel USBA high speed USB device controller 3 * [Original from Linux kernel: drivers/usb/gadget/atmel_usba_udc.h] 4 * 5 * Copyright (C) 2005-2013 Atmel Corporation 6 * Bo Shen <voice.shen@atmel.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __LINUX_USB_GADGET_USBA_UDC_H__ 12 #define __LINUX_USB_GADGET_USBA_UDC_H__ 13 14 /* USB register offsets */ 15 #define USBA_CTRL 0x0000 16 #define USBA_FNUM 0x0004 17 #define USBA_INT_ENB 0x0010 18 #define USBA_INT_STA 0x0014 19 #define USBA_INT_CLR 0x0018 20 #define USBA_EPT_RST 0x001c 21 #define USBA_TST 0x00e0 22 23 /* USB endpoint register offsets */ 24 #define USBA_EPT_CFG 0x0000 25 #define USBA_EPT_CTL_ENB 0x0004 26 #define USBA_EPT_CTL_DIS 0x0008 27 #define USBA_EPT_CTL 0x000c 28 #define USBA_EPT_SET_STA 0x0014 29 #define USBA_EPT_CLR_STA 0x0018 30 #define USBA_EPT_STA 0x001c 31 32 /* USB DMA register offsets */ 33 #define USBA_DMA_NXT_DSC 0x0000 34 #define USBA_DMA_ADDRESS 0x0004 35 #define USBA_DMA_CONTROL 0x0008 36 #define USBA_DMA_STATUS 0x000c 37 38 /* Bitfields in CTRL */ 39 #define USBA_DEV_ADDR_OFFSET 0 40 #define USBA_DEV_ADDR_SIZE 7 41 #define USBA_FADDR_EN (1 << 7) 42 #define USBA_EN_USBA (1 << 8) 43 #define USBA_DETACH (1 << 9) 44 #define USBA_REMOTE_WAKE_UP (1 << 10) 45 #define USBA_PULLD_DIS (1 << 11) 46 47 #define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS) 48 #define USBA_DISABLE_MASK USBA_DETACH 49 50 /* Bitfields in FNUM */ 51 #define USBA_MICRO_FRAME_NUM_OFFSET 0 52 #define USBA_MICRO_FRAME_NUM_SIZE 3 53 #define USBA_FRAME_NUMBER_OFFSET 3 54 #define USBA_FRAME_NUMBER_SIZE 11 55 #define USBA_FRAME_NUM_ERROR (1 << 31) 56 57 /* Bitfields in INT_ENB/INT_STA/INT_CLR */ 58 #define USBA_HIGH_SPEED (1 << 0) 59 #define USBA_DET_SUSPEND (1 << 1) 60 #define USBA_MICRO_SOF (1 << 2) 61 #define USBA_SOF (1 << 3) 62 #define USBA_END_OF_RESET (1 << 4) 63 #define USBA_WAKE_UP (1 << 5) 64 #define USBA_END_OF_RESUME (1 << 6) 65 #define USBA_UPSTREAM_RESUME (1 << 7) 66 #define USBA_EPT_INT_OFFSET 8 67 #define USBA_EPT_INT_SIZE 16 68 #define USBA_DMA_INT_OFFSET 24 69 #define USBA_DMA_INT_SIZE 8 70 71 /* Bitfields in EPT_RST */ 72 #define USBA_RST_OFFSET 0 73 #define USBA_RST_SIZE 16 74 75 /* Bitfields in USBA_TST */ 76 #define USBA_SPEED_CFG_OFFSET 0 77 #define USBA_SPEED_CFG_SIZE 2 78 #define USBA_TST_J_MODE (1 << 2) 79 #define USBA_TST_K_MODE (1 << 3) 80 #define USBA_TST_PKT_MODE (1 << 4) 81 #define USBA_OPMODE2 (1 << 5) 82 83 /* Bitfields in EPT_CFG */ 84 #define USBA_EPT_SIZE_OFFSET 0 85 #define USBA_EPT_SIZE_SIZE 3 86 #define USBA_EPT_DIR_IN (1 << 3) 87 #define USBA_EPT_TYPE_OFFSET 4 88 #define USBA_EPT_TYPE_SIZE 2 89 #define USBA_BK_NUMBER_OFFSET 6 90 #define USBA_BK_NUMBER_SIZE 2 91 #define USBA_NB_TRANS_OFFSET 8 92 #define USBA_NB_TRANS_SIZE 2 93 #define USBA_EPT_MAPPED (1 << 31) 94 95 /* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */ 96 #define USBA_EPT_ENABLE (1 << 0) 97 #define USBA_AUTO_VALID (1 << 1) 98 #define USBA_INTDIS_DMA (1 << 3) 99 #define USBA_NYET_DIS (1 << 4) 100 #define USBA_DATAX_RX (1 << 6) 101 #define USBA_MDATA_RX (1 << 7) 102 /* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */ 103 #define USBA_BUSY_BANK_IE (1 << 18) 104 105 /* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */ 106 #define USBA_FORCE_STALL (1 << 5) 107 #define USBA_TOGGLE_CLR (1 << 6) 108 #define USBA_TOGGLE_SEQ_OFFSET 6 109 #define USBA_TOGGLE_SEQ_SIZE 2 110 #define USBA_ERR_OVFLW (1 << 8) 111 #define USBA_RX_BK_RDY (1 << 9) 112 #define USBA_KILL_BANK (1 << 9) 113 #define USBA_TX_COMPLETE (1 << 10) 114 #define USBA_TX_PK_RDY (1 << 11) 115 #define USBA_ISO_ERR_TRANS (1 << 11) 116 #define USBA_RX_SETUP (1 << 12) 117 #define USBA_ISO_ERR_FLOW (1 << 12) 118 #define USBA_STALL_SENT (1 << 13) 119 #define USBA_ISO_ERR_CRC (1 << 13) 120 #define USBA_ISO_ERR_NBTRANS (1 << 13) 121 #define USBA_NAK_IN (1 << 14) 122 #define USBA_ISO_ERR_FLUSH (1 << 14) 123 #define USBA_NAK_OUT (1 << 15) 124 #define USBA_CURRENT_BANK_OFFSET 16 125 #define USBA_CURRENT_BANK_SIZE 2 126 #define USBA_BUSY_BANKS_OFFSET 18 127 #define USBA_BUSY_BANKS_SIZE 2 128 #define USBA_BYTE_COUNT_OFFSET 20 129 #define USBA_BYTE_COUNT_SIZE 11 130 #define USBA_SHORT_PACKET (1 << 31) 131 132 /* Bitfields in DMA_CONTROL */ 133 #define USBA_DMA_CH_EN (1 << 0) 134 #define USBA_DMA_LINK (1 << 1) 135 #define USBA_DMA_END_TR_EN (1 << 2) 136 #define USBA_DMA_END_BUF_EN (1 << 3) 137 #define USBA_DMA_END_TR_IE (1 << 4) 138 #define USBA_DMA_END_BUF_IE (1 << 5) 139 #define USBA_DMA_DESC_LOAD_IE (1 << 6) 140 #define USBA_DMA_BURST_LOCK (1 << 7) 141 #define USBA_DMA_BUF_LEN_OFFSET 16 142 #define USBA_DMA_BUF_LEN_SIZE 16 143 144 /* Bitfields in DMA_STATUS */ 145 #define USBA_DMA_CH_ACTIVE (1 << 1) 146 #define USBA_DMA_END_TR_ST (1 << 4) 147 #define USBA_DMA_END_BUF_ST (1 << 5) 148 #define USBA_DMA_DESC_LOAD_ST (1 << 6) 149 150 /* Constants for SPEED_CFG */ 151 #define USBA_SPEED_CFG_NORMAL 0 152 #define USBA_SPEED_CFG_FORCE_HIGH 2 153 #define USBA_SPEED_CFG_FORCE_FULL 3 154 155 /* Constants for EPT_SIZE */ 156 #define USBA_EPT_SIZE_8 0 157 #define USBA_EPT_SIZE_16 1 158 #define USBA_EPT_SIZE_32 2 159 #define USBA_EPT_SIZE_64 3 160 #define USBA_EPT_SIZE_128 4 161 #define USBA_EPT_SIZE_256 5 162 #define USBA_EPT_SIZE_512 6 163 #define USBA_EPT_SIZE_1024 7 164 165 /* Constants for EPT_TYPE */ 166 #define USBA_EPT_TYPE_CONTROL 0 167 #define USBA_EPT_TYPE_ISO 1 168 #define USBA_EPT_TYPE_BULK 2 169 #define USBA_EPT_TYPE_INT 3 170 171 /* Constants for BK_NUMBER */ 172 #define USBA_BK_NUMBER_ZERO 0 173 #define USBA_BK_NUMBER_ONE 1 174 #define USBA_BK_NUMBER_DOUBLE 2 175 #define USBA_BK_NUMBER_TRIPLE 3 176 177 /* Bit manipulation macros */ 178 #define USBA_BF(name, value) \ 179 (((value) & ((1 << USBA_##name##_SIZE) - 1)) \ 180 << USBA_##name##_OFFSET) 181 #define USBA_BFEXT(name, value) \ 182 (((value) >> USBA_##name##_OFFSET) \ 183 & ((1 << USBA_##name##_SIZE) - 1)) 184 #define USBA_BFINS(name, value, old) \ 185 (((old) & ~(((1 << USBA_##name##_SIZE) - 1) \ 186 << USBA_##name##_OFFSET)) \ 187 | USBA_BF(name, value)) 188 189 /* Register access macros */ 190 #define usba_readl(udc, reg) \ 191 __raw_readl((udc)->regs + USBA_##reg) 192 #define usba_writel(udc, reg, value) \ 193 __raw_writel((value), (udc)->regs + USBA_##reg) 194 #define usba_ep_readl(ep, reg) \ 195 __raw_readl((ep)->ep_regs + USBA_EPT_##reg) 196 #define usba_ep_writel(ep, reg, value) \ 197 __raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg) 198 #define usba_dma_readl(ep, reg) \ 199 __raw_readl((ep)->dma_regs + USBA_DMA_##reg) 200 #define usba_dma_writel(ep, reg, value) \ 201 __raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg) 202 203 /* Calculate base address for a given endpoint or DMA controller */ 204 #define USBA_EPT_BASE(x) (0x100 + (x) * 0x20) 205 #define USBA_DMA_BASE(x) (0x300 + (x) * 0x10) 206 #define USBA_FIFO_BASE(x) ((x) << 16) 207 208 /* Synth parameters */ 209 #define USBA_NR_ENDPOINTS 7 210 211 #define EP0_FIFO_SIZE 64 212 #define EP0_EPT_SIZE USBA_EPT_SIZE_64 213 #define EP0_NR_BANKS 1 214 215 #define DBG_ERR 0x0001 /* report all error returns */ 216 #define DBG_HW 0x0002 /* debug hardware initialization */ 217 #define DBG_GADGET 0x0004 /* calls to/from gadget driver */ 218 #define DBG_INT 0x0008 /* interrupts */ 219 #define DBG_BUS 0x0010 /* report changes in bus state */ 220 #define DBG_QUEUE 0x0020 /* debug request queue processing */ 221 #define DBG_FIFO 0x0040 /* debug FIFO contents */ 222 #define DBG_DMA 0x0080 /* debug DMA handling */ 223 #define DBG_REQ 0x0100 /* print out queued request length */ 224 #define DBG_ALL 0xffff 225 #define DBG_NONE 0x0000 226 227 #define DEBUG_LEVEL (DBG_ERR) 228 229 #define DBG(level, fmt, ...) \ 230 do { \ 231 if ((level) & DEBUG_LEVEL) \ 232 debug("udc: " fmt, ## __VA_ARGS__); \ 233 } while (0) 234 235 enum usba_ctrl_state { 236 WAIT_FOR_SETUP, 237 DATA_STAGE_IN, 238 DATA_STAGE_OUT, 239 STATUS_STAGE_IN, 240 STATUS_STAGE_OUT, 241 STATUS_STAGE_ADDR, 242 STATUS_STAGE_TEST, 243 }; 244 245 struct usba_dma_desc { 246 dma_addr_t next; 247 dma_addr_t addr; 248 u32 ctrl; 249 }; 250 251 struct usba_ep { 252 int state; 253 void *ep_regs; 254 void *dma_regs; 255 void *fifo; 256 struct usb_ep ep; 257 struct usba_udc *udc; 258 259 struct list_head queue; 260 261 u16 fifo_size; 262 u8 nr_banks; 263 u8 index; 264 unsigned int can_dma:1; 265 unsigned int can_isoc:1; 266 unsigned int is_isoc:1; 267 unsigned int is_in:1; 268 269 const struct usb_endpoint_descriptor *desc; 270 }; 271 272 struct usba_request { 273 struct usb_request req; 274 struct list_head queue; 275 276 u32 ctrl; 277 278 unsigned int submitted:1; 279 unsigned int last_transaction:1; 280 unsigned int using_dma:1; 281 unsigned int mapped:1; 282 }; 283 284 struct usba_udc { 285 void *regs; 286 void *fifo; 287 288 struct usb_gadget gadget; 289 struct usb_gadget_driver *driver; 290 struct platform_device *pdev; 291 int irq; 292 int vbus_pin; 293 int vbus_pin_inverted; 294 int num_ep; 295 struct usba_ep *usba_ep; 296 297 u16 devstatus; 298 299 u16 test_mode; 300 int vbus_prev; 301 }; 302 303 static inline struct usba_ep *to_usba_ep(struct usb_ep *ep) 304 { 305 return container_of(ep, struct usba_ep, ep); 306 } 307 308 static inline struct usba_request *to_usba_req(struct usb_request *req) 309 { 310 return container_of(req, struct usba_request, req); 311 } 312 313 static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget) 314 { 315 return container_of(gadget, struct usba_udc, gadget); 316 } 317 318 #define ep_is_control(ep) ((ep)->index == 0) 319 #define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE) 320 321 #endif /* __LINUX_USB_GADGET_USBA_UDC_H */ 322