1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (C) 2009 NVIDIA, Corporation 4 * Copyright (C) 2007-2008 SMSC (Steve Glendinning) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/unaligned.h> 10 #include <common.h> 11 #include <usb.h> 12 #include <linux/mii.h> 13 #include "usb_ether.h" 14 #include <malloc.h> 15 16 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 17 18 /* LED defines */ 19 #define LED_GPIO_CFG (0x24) 20 #define LED_GPIO_CFG_SPD_LED (0x01000000) 21 #define LED_GPIO_CFG_LNK_LED (0x00100000) 22 #define LED_GPIO_CFG_FDX_LED (0x00010000) 23 24 /* Tx command words */ 25 #define TX_CMD_A_FIRST_SEG_ 0x00002000 26 #define TX_CMD_A_LAST_SEG_ 0x00001000 27 28 /* Rx status word */ 29 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 30 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 31 32 /* SCSRs */ 33 #define ID_REV 0x00 34 35 #define INT_STS 0x08 36 37 #define TX_CFG 0x10 38 #define TX_CFG_ON_ 0x00000004 39 40 #define HW_CFG 0x14 41 #define HW_CFG_BIR_ 0x00001000 42 #define HW_CFG_RXDOFF_ 0x00000600 43 #define HW_CFG_MEF_ 0x00000020 44 #define HW_CFG_BCE_ 0x00000002 45 #define HW_CFG_LRST_ 0x00000008 46 47 #define PM_CTRL 0x20 48 #define PM_CTL_PHY_RST_ 0x00000010 49 50 #define AFC_CFG 0x2C 51 52 /* 53 * Hi watermark = 15.5Kb (~10 mtu pkts) 54 * low watermark = 3k (~2 mtu pkts) 55 * backpressure duration = ~ 350us 56 * Apply FC on any frame. 57 */ 58 #define AFC_CFG_DEFAULT 0x00F830A1 59 60 #define E2P_CMD 0x30 61 #define E2P_CMD_BUSY_ 0x80000000 62 #define E2P_CMD_READ_ 0x00000000 63 #define E2P_CMD_TIMEOUT_ 0x00000400 64 #define E2P_CMD_LOADED_ 0x00000200 65 #define E2P_CMD_ADDR_ 0x000001FF 66 67 #define E2P_DATA 0x34 68 69 #define BURST_CAP 0x38 70 71 #define INT_EP_CTL 0x68 72 #define INT_EP_CTL_PHY_INT_ 0x00008000 73 74 #define BULK_IN_DLY 0x6C 75 76 /* MAC CSRs */ 77 #define MAC_CR 0x100 78 #define MAC_CR_MCPAS_ 0x00080000 79 #define MAC_CR_PRMS_ 0x00040000 80 #define MAC_CR_HPFILT_ 0x00002000 81 #define MAC_CR_TXEN_ 0x00000008 82 #define MAC_CR_RXEN_ 0x00000004 83 84 #define ADDRH 0x104 85 86 #define ADDRL 0x108 87 88 #define MII_ADDR 0x114 89 #define MII_WRITE_ 0x02 90 #define MII_BUSY_ 0x01 91 #define MII_READ_ 0x00 /* ~of MII Write bit */ 92 93 #define MII_DATA 0x118 94 95 #define FLOW 0x11C 96 97 #define VLAN1 0x120 98 99 #define COE_CR 0x130 100 #define Tx_COE_EN_ 0x00010000 101 #define Rx_COE_EN_ 0x00000001 102 103 /* Vendor-specific PHY Definitions */ 104 #define PHY_INT_SRC 29 105 106 #define PHY_INT_MASK 30 107 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 108 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 109 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 110 PHY_INT_MASK_LINK_DOWN_) 111 112 /* USB Vendor Requests */ 113 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 114 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 115 116 /* Some extra defines */ 117 #define HS_USB_PKT_SIZE 512 118 #define FS_USB_PKT_SIZE 64 119 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 120 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 121 #define DEFAULT_BULK_IN_DELAY 0x00002000 122 #define MAX_SINGLE_PACKET_SIZE 2048 123 #define EEPROM_MAC_OFFSET 0x01 124 #define SMSC95XX_INTERNAL_PHY_ID 1 125 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 126 127 /* local defines */ 128 #define SMSC95XX_BASE_NAME "sms" 129 #define USB_CTRL_SET_TIMEOUT 5000 130 #define USB_CTRL_GET_TIMEOUT 5000 131 #define USB_BULK_SEND_TIMEOUT 5000 132 #define USB_BULK_RECV_TIMEOUT 5000 133 134 #define AX_RX_URB_SIZE 2048 135 #define PHY_CONNECT_TIMEOUT 5000 136 137 #define TURBO_MODE 138 139 /* local vars */ 140 static int curr_eth_dev; /* index for name of next device detected */ 141 142 /* driver private */ 143 struct smsc95xx_private { 144 size_t rx_urb_size; /* maximum USB URB size */ 145 u32 mac_cr; /* MAC control register value */ 146 int have_hwaddr; /* 1 if we have a hardware MAC address */ 147 }; 148 149 /* 150 * Smsc95xx infrastructure commands 151 */ 152 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) 153 { 154 int len; 155 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 156 157 cpu_to_le32s(&data); 158 tmpbuf[0] = data; 159 160 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0), 161 USB_VENDOR_REQUEST_WRITE_REGISTER, 162 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 163 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT); 164 if (len != sizeof(data)) { 165 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 166 index, data, len); 167 return -1; 168 } 169 return 0; 170 } 171 172 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data) 173 { 174 int len; 175 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 176 177 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0), 178 USB_VENDOR_REQUEST_READ_REGISTER, 179 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 180 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT); 181 *data = tmpbuf[0]; 182 if (len != sizeof(data)) { 183 debug("smsc95xx_read_reg failed: index=%d, len=%d", 184 index, len); 185 return -1; 186 } 187 188 le32_to_cpus(data); 189 return 0; 190 } 191 192 /* Loop until the read is completed with timeout */ 193 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev) 194 { 195 unsigned long start_time = get_timer(0); 196 u32 val; 197 198 do { 199 smsc95xx_read_reg(dev, MII_ADDR, &val); 200 if (!(val & MII_BUSY_)) 201 return 0; 202 } while (get_timer(start_time) < 1 * 1000 * 1000); 203 204 return -1; 205 } 206 207 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx) 208 { 209 u32 val, addr; 210 211 /* confirm MII not busy */ 212 if (smsc95xx_phy_wait_not_busy(dev)) { 213 debug("MII is busy in smsc95xx_mdio_read\n"); 214 return -1; 215 } 216 217 /* set the address, index & direction (read from PHY) */ 218 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 219 smsc95xx_write_reg(dev, MII_ADDR, addr); 220 221 if (smsc95xx_phy_wait_not_busy(dev)) { 222 debug("Timed out reading MII reg %02X\n", idx); 223 return -1; 224 } 225 226 smsc95xx_read_reg(dev, MII_DATA, &val); 227 228 return (u16)(val & 0xFFFF); 229 } 230 231 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx, 232 int regval) 233 { 234 u32 val, addr; 235 236 /* confirm MII not busy */ 237 if (smsc95xx_phy_wait_not_busy(dev)) { 238 debug("MII is busy in smsc95xx_mdio_write\n"); 239 return; 240 } 241 242 val = regval; 243 smsc95xx_write_reg(dev, MII_DATA, val); 244 245 /* set the address, index & direction (write to PHY) */ 246 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 247 smsc95xx_write_reg(dev, MII_ADDR, addr); 248 249 if (smsc95xx_phy_wait_not_busy(dev)) 250 debug("Timed out writing MII reg %02X\n", idx); 251 } 252 253 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev) 254 { 255 unsigned long start_time = get_timer(0); 256 u32 val; 257 258 do { 259 smsc95xx_read_reg(dev, E2P_CMD, &val); 260 if (!(val & E2P_CMD_BUSY_)) 261 return 0; 262 udelay(40); 263 } while (get_timer(start_time) < 1 * 1000 * 1000); 264 265 debug("EEPROM is busy\n"); 266 return -1; 267 } 268 269 static int smsc95xx_wait_eeprom(struct ueth_data *dev) 270 { 271 unsigned long start_time = get_timer(0); 272 u32 val; 273 274 do { 275 smsc95xx_read_reg(dev, E2P_CMD, &val); 276 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 277 break; 278 udelay(40); 279 } while (get_timer(start_time) < 1 * 1000 * 1000); 280 281 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 282 debug("EEPROM read operation timeout\n"); 283 return -1; 284 } 285 return 0; 286 } 287 288 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length, 289 u8 *data) 290 { 291 u32 val; 292 int i, ret; 293 294 ret = smsc95xx_eeprom_confirm_not_busy(dev); 295 if (ret) 296 return ret; 297 298 for (i = 0; i < length; i++) { 299 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 300 smsc95xx_write_reg(dev, E2P_CMD, val); 301 302 ret = smsc95xx_wait_eeprom(dev); 303 if (ret < 0) 304 return ret; 305 306 smsc95xx_read_reg(dev, E2P_DATA, &val); 307 data[i] = val & 0xFF; 308 offset++; 309 } 310 return 0; 311 } 312 313 /* 314 * mii_nway_restart - restart NWay (autonegotiation) for this interface 315 * 316 * Returns 0 on success, negative on error. 317 */ 318 static int mii_nway_restart(struct ueth_data *dev) 319 { 320 int bmcr; 321 int r = -1; 322 323 /* if autoneg is off, it's an error */ 324 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR); 325 326 if (bmcr & BMCR_ANENABLE) { 327 bmcr |= BMCR_ANRESTART; 328 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 329 r = 0; 330 } 331 return r; 332 } 333 334 static int smsc95xx_phy_initialize(struct ueth_data *dev) 335 { 336 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 337 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 338 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 339 ADVERTISE_PAUSE_ASYM); 340 341 /* read to clear */ 342 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC); 343 344 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK, 345 PHY_INT_MASK_DEFAULT_); 346 mii_nway_restart(dev); 347 348 debug("phy initialised succesfully\n"); 349 return 0; 350 } 351 352 static int smsc95xx_init_mac_address(struct eth_device *eth, 353 struct ueth_data *dev) 354 { 355 /* try reading mac address from EEPROM */ 356 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 357 eth->enetaddr) == 0) { 358 if (is_valid_ethaddr(eth->enetaddr)) { 359 /* eeprom values are valid so use them */ 360 debug("MAC address read from EEPROM\n"); 361 return 0; 362 } 363 } 364 365 /* 366 * No eeprom, or eeprom values are invalid. Generating a random MAC 367 * address is not safe. Just return an error. 368 */ 369 return -1; 370 } 371 372 static int smsc95xx_write_hwaddr(struct eth_device *eth) 373 { 374 struct ueth_data *dev = (struct ueth_data *)eth->priv; 375 struct smsc95xx_private *priv = dev->dev_priv; 376 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]); 377 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]); 378 int ret; 379 380 /* set hardware address */ 381 debug("** %s()\n", __func__); 382 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); 383 if (ret < 0) 384 return ret; 385 386 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); 387 if (ret < 0) 388 return ret; 389 390 debug("MAC %pM\n", eth->enetaddr); 391 priv->have_hwaddr = 1; 392 return 0; 393 } 394 395 /* Enable or disable Tx & Rx checksum offload engines */ 396 static int smsc95xx_set_csums(struct ueth_data *dev, 397 int use_tx_csum, int use_rx_csum) 398 { 399 u32 read_buf; 400 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); 401 if (ret < 0) 402 return ret; 403 404 if (use_tx_csum) 405 read_buf |= Tx_COE_EN_; 406 else 407 read_buf &= ~Tx_COE_EN_; 408 409 if (use_rx_csum) 410 read_buf |= Rx_COE_EN_; 411 else 412 read_buf &= ~Rx_COE_EN_; 413 414 ret = smsc95xx_write_reg(dev, COE_CR, read_buf); 415 if (ret < 0) 416 return ret; 417 418 debug("COE_CR = 0x%08x\n", read_buf); 419 return 0; 420 } 421 422 static void smsc95xx_set_multicast(struct ueth_data *dev) 423 { 424 struct smsc95xx_private *priv = dev->dev_priv; 425 426 /* No multicast in u-boot */ 427 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 428 } 429 430 /* starts the TX path */ 431 static void smsc95xx_start_tx_path(struct ueth_data *dev) 432 { 433 struct smsc95xx_private *priv = dev->dev_priv; 434 u32 reg_val; 435 436 /* Enable Tx at MAC */ 437 priv->mac_cr |= MAC_CR_TXEN_; 438 439 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 440 441 /* Enable Tx at SCSRs */ 442 reg_val = TX_CFG_ON_; 443 smsc95xx_write_reg(dev, TX_CFG, reg_val); 444 } 445 446 /* Starts the Receive path */ 447 static void smsc95xx_start_rx_path(struct ueth_data *dev) 448 { 449 struct smsc95xx_private *priv = dev->dev_priv; 450 451 priv->mac_cr |= MAC_CR_RXEN_; 452 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 453 } 454 455 /* 456 * Smsc95xx callbacks 457 */ 458 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 459 { 460 int ret; 461 u32 write_buf; 462 u32 read_buf; 463 u32 burst_cap; 464 int timeout; 465 struct ueth_data *dev = (struct ueth_data *)eth->priv; 466 struct smsc95xx_private *priv = 467 (struct smsc95xx_private *)dev->dev_priv; 468 #define TIMEOUT_RESOLUTION 50 /* ms */ 469 int link_detected; 470 471 debug("** %s()\n", __func__); 472 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 473 474 write_buf = HW_CFG_LRST_; 475 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf); 476 if (ret < 0) 477 return ret; 478 479 timeout = 0; 480 do { 481 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 482 if (ret < 0) 483 return ret; 484 udelay(10 * 1000); 485 timeout++; 486 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 487 488 if (timeout >= 100) { 489 debug("timeout waiting for completion of Lite Reset\n"); 490 return -1; 491 } 492 493 write_buf = PM_CTL_PHY_RST_; 494 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf); 495 if (ret < 0) 496 return ret; 497 498 timeout = 0; 499 do { 500 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); 501 if (ret < 0) 502 return ret; 503 udelay(10 * 1000); 504 timeout++; 505 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 506 if (timeout >= 100) { 507 debug("timeout waiting for PHY Reset\n"); 508 return -1; 509 } 510 if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) 511 priv->have_hwaddr = 1; 512 if (!priv->have_hwaddr) { 513 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 514 return -1; 515 } 516 if (smsc95xx_write_hwaddr(eth) < 0) 517 return -1; 518 519 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 520 if (ret < 0) 521 return ret; 522 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 523 524 read_buf |= HW_CFG_BIR_; 525 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 526 if (ret < 0) 527 return ret; 528 529 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 530 if (ret < 0) 531 return ret; 532 debug("Read Value from HW_CFG after writing " 533 "HW_CFG_BIR_: 0x%08x\n", read_buf); 534 535 #ifdef TURBO_MODE 536 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 537 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 538 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 539 } else { 540 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 541 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 542 } 543 #else 544 burst_cap = 0; 545 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 546 #endif 547 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); 548 549 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); 550 if (ret < 0) 551 return ret; 552 553 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); 554 if (ret < 0) 555 return ret; 556 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 557 558 read_buf = DEFAULT_BULK_IN_DELAY; 559 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf); 560 if (ret < 0) 561 return ret; 562 563 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); 564 if (ret < 0) 565 return ret; 566 debug("Read Value from BULK_IN_DLY after writing: " 567 "0x%08x\n", read_buf); 568 569 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 570 if (ret < 0) 571 return ret; 572 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 573 574 #ifdef TURBO_MODE 575 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 576 #endif 577 read_buf &= ~HW_CFG_RXDOFF_; 578 579 #define NET_IP_ALIGN 0 580 read_buf |= NET_IP_ALIGN << 9; 581 582 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 583 if (ret < 0) 584 return ret; 585 586 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 587 if (ret < 0) 588 return ret; 589 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 590 591 write_buf = 0xFFFFFFFF; 592 ret = smsc95xx_write_reg(dev, INT_STS, write_buf); 593 if (ret < 0) 594 return ret; 595 596 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); 597 if (ret < 0) 598 return ret; 599 debug("ID_REV = 0x%08x\n", read_buf); 600 601 /* Configure GPIO pins as LED outputs */ 602 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | 603 LED_GPIO_CFG_FDX_LED; 604 ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); 605 if (ret < 0) 606 return ret; 607 debug("LED_GPIO_CFG set\n"); 608 609 /* Init Tx */ 610 write_buf = 0; 611 ret = smsc95xx_write_reg(dev, FLOW, write_buf); 612 if (ret < 0) 613 return ret; 614 615 read_buf = AFC_CFG_DEFAULT; 616 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf); 617 if (ret < 0) 618 return ret; 619 620 ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr); 621 if (ret < 0) 622 return ret; 623 624 /* Init Rx. Set Vlan */ 625 write_buf = (u32)ETH_P_8021Q; 626 ret = smsc95xx_write_reg(dev, VLAN1, write_buf); 627 if (ret < 0) 628 return ret; 629 630 /* Disable checksum offload engines */ 631 ret = smsc95xx_set_csums(dev, 0, 0); 632 if (ret < 0) { 633 debug("Failed to set csum offload: %d\n", ret); 634 return ret; 635 } 636 smsc95xx_set_multicast(dev); 637 638 if (smsc95xx_phy_initialize(dev) < 0) 639 return -1; 640 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); 641 if (ret < 0) 642 return ret; 643 644 /* enable PHY interrupts */ 645 read_buf |= INT_EP_CTL_PHY_INT_; 646 647 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); 648 if (ret < 0) 649 return ret; 650 651 smsc95xx_start_tx_path(dev); 652 smsc95xx_start_rx_path(dev); 653 654 timeout = 0; 655 do { 656 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR) 657 & BMSR_LSTATUS; 658 if (!link_detected) { 659 if (timeout == 0) 660 printf("Waiting for Ethernet connection... "); 661 udelay(TIMEOUT_RESOLUTION * 1000); 662 timeout += TIMEOUT_RESOLUTION; 663 } 664 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 665 if (link_detected) { 666 if (timeout != 0) 667 printf("done.\n"); 668 } else { 669 printf("unable to connect.\n"); 670 return -1; 671 } 672 return 0; 673 } 674 675 static int smsc95xx_send(struct eth_device *eth, void* packet, int length) 676 { 677 struct ueth_data *dev = (struct ueth_data *)eth->priv; 678 int err; 679 int actual_len; 680 u32 tx_cmd_a; 681 u32 tx_cmd_b; 682 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 683 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); 684 685 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 686 if (length > PKTSIZE) 687 return -1; 688 689 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 690 tx_cmd_b = (u32)length; 691 cpu_to_le32s(&tx_cmd_a); 692 cpu_to_le32s(&tx_cmd_b); 693 694 /* prepend cmd_a and cmd_b */ 695 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 696 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 697 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 698 length); 699 err = usb_bulk_msg(dev->pusb_dev, 700 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 701 (void *)msg, 702 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 703 &actual_len, 704 USB_BULK_SEND_TIMEOUT); 705 debug("Tx: len = %u, actual = %u, err = %d\n", 706 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 707 actual_len, err); 708 return err; 709 } 710 711 static int smsc95xx_recv(struct eth_device *eth) 712 { 713 struct ueth_data *dev = (struct ueth_data *)eth->priv; 714 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); 715 unsigned char *buf_ptr; 716 int err; 717 int actual_len; 718 u32 packet_len; 719 int cur_buf_align; 720 721 debug("** %s()\n", __func__); 722 err = usb_bulk_msg(dev->pusb_dev, 723 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 724 (void *)recv_buf, 725 AX_RX_URB_SIZE, 726 &actual_len, 727 USB_BULK_RECV_TIMEOUT); 728 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 729 actual_len, err); 730 if (err != 0) { 731 debug("Rx: failed to receive\n"); 732 return -1; 733 } 734 if (actual_len > AX_RX_URB_SIZE) { 735 debug("Rx: received too many bytes %d\n", actual_len); 736 return -1; 737 } 738 739 buf_ptr = recv_buf; 740 while (actual_len > 0) { 741 /* 742 * 1st 4 bytes contain the length of the actual data plus error 743 * info. Extract data length. 744 */ 745 if (actual_len < sizeof(packet_len)) { 746 debug("Rx: incomplete packet length\n"); 747 return -1; 748 } 749 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 750 le32_to_cpus(&packet_len); 751 if (packet_len & RX_STS_ES_) { 752 debug("Rx: Error header=%#x", packet_len); 753 return -1; 754 } 755 packet_len = ((packet_len & RX_STS_FL_) >> 16); 756 757 if (packet_len > actual_len - sizeof(packet_len)) { 758 debug("Rx: too large packet: %d\n", packet_len); 759 return -1; 760 } 761 762 /* Notify net stack */ 763 net_process_received_packet(buf_ptr + sizeof(packet_len), 764 packet_len - 4); 765 766 /* Adjust for next iteration */ 767 actual_len -= sizeof(packet_len) + packet_len; 768 buf_ptr += sizeof(packet_len) + packet_len; 769 cur_buf_align = (int)buf_ptr - (int)recv_buf; 770 771 if (cur_buf_align & 0x03) { 772 int align = 4 - (cur_buf_align & 0x03); 773 774 actual_len -= align; 775 buf_ptr += align; 776 } 777 } 778 return err; 779 } 780 781 static void smsc95xx_halt(struct eth_device *eth) 782 { 783 debug("** %s()\n", __func__); 784 } 785 786 /* 787 * SMSC probing functions 788 */ 789 void smsc95xx_eth_before_probe(void) 790 { 791 curr_eth_dev = 0; 792 } 793 794 struct smsc95xx_dongle { 795 unsigned short vendor; 796 unsigned short product; 797 }; 798 799 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 800 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 801 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 802 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ 803 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */ 804 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */ 805 { 0x0000, 0x0000 } /* END - Do not remove */ 806 }; 807 808 /* Probe to see if a new device is actually an SMSC device */ 809 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 810 struct ueth_data *ss) 811 { 812 struct usb_interface *iface; 813 struct usb_interface_descriptor *iface_desc; 814 int i; 815 816 /* let's examine the device now */ 817 iface = &dev->config.if_desc[ifnum]; 818 iface_desc = &dev->config.if_desc[ifnum].desc; 819 820 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 821 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 822 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 823 /* Found a supported dongle */ 824 break; 825 } 826 if (smsc95xx_dongles[i].vendor == 0) 827 return 0; 828 829 /* At this point, we know we've got a live one */ 830 debug("\n\nUSB Ethernet device detected\n"); 831 memset(ss, '\0', sizeof(struct ueth_data)); 832 833 /* Initialize the ueth_data structure with some useful info */ 834 ss->ifnum = ifnum; 835 ss->pusb_dev = dev; 836 ss->subclass = iface_desc->bInterfaceSubClass; 837 ss->protocol = iface_desc->bInterfaceProtocol; 838 839 /* 840 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 841 * We will ignore any others. 842 */ 843 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 844 /* is it an BULK endpoint? */ 845 if ((iface->ep_desc[i].bmAttributes & 846 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 847 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 848 ss->ep_in = 849 iface->ep_desc[i].bEndpointAddress & 850 USB_ENDPOINT_NUMBER_MASK; 851 else 852 ss->ep_out = 853 iface->ep_desc[i].bEndpointAddress & 854 USB_ENDPOINT_NUMBER_MASK; 855 } 856 857 /* is it an interrupt endpoint? */ 858 if ((iface->ep_desc[i].bmAttributes & 859 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 860 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 861 USB_ENDPOINT_NUMBER_MASK; 862 ss->irqinterval = iface->ep_desc[i].bInterval; 863 } 864 } 865 debug("Endpoints In %d Out %d Int %d\n", 866 ss->ep_in, ss->ep_out, ss->ep_int); 867 868 /* Do some basic sanity checks, and bail if we find a problem */ 869 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 870 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 871 debug("Problems with device\n"); 872 return 0; 873 } 874 dev->privptr = (void *)ss; 875 876 /* alloc driver private */ 877 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); 878 if (!ss->dev_priv) 879 return 0; 880 881 return 1; 882 } 883 884 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 885 struct eth_device *eth) 886 { 887 debug("** %s()\n", __func__); 888 if (!eth) { 889 debug("%s: missing parameter.\n", __func__); 890 return 0; 891 } 892 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 893 eth->init = smsc95xx_init; 894 eth->send = smsc95xx_send; 895 eth->recv = smsc95xx_recv; 896 eth->halt = smsc95xx_halt; 897 eth->write_hwaddr = smsc95xx_write_hwaddr; 898 eth->priv = ss; 899 return 1; 900 } 901