1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (C) 2009 NVIDIA, Corporation 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <usb.h> 25 #include <linux/mii.h> 26 #include "usb_ether.h" 27 28 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 29 30 /* Tx command words */ 31 #define TX_CMD_A_FIRST_SEG_ 0x00002000 32 #define TX_CMD_A_LAST_SEG_ 0x00001000 33 34 /* Rx status word */ 35 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 36 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 37 38 /* SCSRs */ 39 #define ID_REV 0x00 40 41 #define INT_STS 0x08 42 43 #define TX_CFG 0x10 44 #define TX_CFG_ON_ 0x00000004 45 46 #define HW_CFG 0x14 47 #define HW_CFG_BIR_ 0x00001000 48 #define HW_CFG_RXDOFF_ 0x00000600 49 #define HW_CFG_MEF_ 0x00000020 50 #define HW_CFG_BCE_ 0x00000002 51 #define HW_CFG_LRST_ 0x00000008 52 53 #define PM_CTRL 0x20 54 #define PM_CTL_PHY_RST_ 0x00000010 55 56 #define AFC_CFG 0x2C 57 58 /* 59 * Hi watermark = 15.5Kb (~10 mtu pkts) 60 * low watermark = 3k (~2 mtu pkts) 61 * backpressure duration = ~ 350us 62 * Apply FC on any frame. 63 */ 64 #define AFC_CFG_DEFAULT 0x00F830A1 65 66 #define E2P_CMD 0x30 67 #define E2P_CMD_BUSY_ 0x80000000 68 #define E2P_CMD_READ_ 0x00000000 69 #define E2P_CMD_TIMEOUT_ 0x00000400 70 #define E2P_CMD_LOADED_ 0x00000200 71 #define E2P_CMD_ADDR_ 0x000001FF 72 73 #define E2P_DATA 0x34 74 75 #define BURST_CAP 0x38 76 77 #define INT_EP_CTL 0x68 78 #define INT_EP_CTL_PHY_INT_ 0x00008000 79 80 #define BULK_IN_DLY 0x6C 81 82 /* MAC CSRs */ 83 #define MAC_CR 0x100 84 #define MAC_CR_MCPAS_ 0x00080000 85 #define MAC_CR_PRMS_ 0x00040000 86 #define MAC_CR_HPFILT_ 0x00002000 87 #define MAC_CR_TXEN_ 0x00000008 88 #define MAC_CR_RXEN_ 0x00000004 89 90 #define ADDRH 0x104 91 92 #define ADDRL 0x108 93 94 #define MII_ADDR 0x114 95 #define MII_WRITE_ 0x02 96 #define MII_BUSY_ 0x01 97 #define MII_READ_ 0x00 /* ~of MII Write bit */ 98 99 #define MII_DATA 0x118 100 101 #define FLOW 0x11C 102 103 #define VLAN1 0x120 104 105 #define COE_CR 0x130 106 #define Tx_COE_EN_ 0x00010000 107 #define Rx_COE_EN_ 0x00000001 108 109 /* Vendor-specific PHY Definitions */ 110 #define PHY_INT_SRC 29 111 112 #define PHY_INT_MASK 30 113 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 114 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 115 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 116 PHY_INT_MASK_LINK_DOWN_) 117 118 /* USB Vendor Requests */ 119 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 120 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 121 122 /* Some extra defines */ 123 #define HS_USB_PKT_SIZE 512 124 #define FS_USB_PKT_SIZE 64 125 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 126 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 127 #define DEFAULT_BULK_IN_DELAY 0x00002000 128 #define MAX_SINGLE_PACKET_SIZE 2048 129 #define EEPROM_MAC_OFFSET 0x01 130 #define SMSC95XX_INTERNAL_PHY_ID 1 131 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 132 133 /* local defines */ 134 #define SMSC95XX_BASE_NAME "sms" 135 #define USB_CTRL_SET_TIMEOUT 5000 136 #define USB_CTRL_GET_TIMEOUT 5000 137 #define USB_BULK_SEND_TIMEOUT 5000 138 #define USB_BULK_RECV_TIMEOUT 5000 139 140 #define AX_RX_URB_SIZE 2048 141 #define PHY_CONNECT_TIMEOUT 5000 142 143 #define TURBO_MODE 144 145 /* local vars */ 146 static int curr_eth_dev; /* index for name of next device detected */ 147 148 149 /* 150 * Smsc95xx infrastructure commands 151 */ 152 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) 153 { 154 int len; 155 156 cpu_to_le32s(&data); 157 158 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0), 159 USB_VENDOR_REQUEST_WRITE_REGISTER, 160 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 161 00, index, &data, sizeof(data), USB_CTRL_SET_TIMEOUT); 162 if (len != sizeof(data)) { 163 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 164 index, data, len); 165 return -1; 166 } 167 return 0; 168 } 169 170 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data) 171 { 172 int len; 173 174 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0), 175 USB_VENDOR_REQUEST_READ_REGISTER, 176 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 177 00, index, data, sizeof(data), USB_CTRL_GET_TIMEOUT); 178 if (len != sizeof(data)) { 179 debug("smsc95xx_read_reg failed: index=%d, len=%d", 180 index, len); 181 return -1; 182 } 183 184 le32_to_cpus(data); 185 return 0; 186 } 187 188 /* Loop until the read is completed with timeout */ 189 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev) 190 { 191 unsigned long start_time = get_timer(0); 192 u32 val; 193 194 do { 195 smsc95xx_read_reg(dev, MII_ADDR, &val); 196 if (!(val & MII_BUSY_)) 197 return 0; 198 } while (get_timer(start_time) < 1 * 1000 * 1000); 199 200 return -1; 201 } 202 203 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx) 204 { 205 u32 val, addr; 206 207 /* confirm MII not busy */ 208 if (smsc95xx_phy_wait_not_busy(dev)) { 209 debug("MII is busy in smsc95xx_mdio_read\n"); 210 return -1; 211 } 212 213 /* set the address, index & direction (read from PHY) */ 214 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 215 smsc95xx_write_reg(dev, MII_ADDR, addr); 216 217 if (smsc95xx_phy_wait_not_busy(dev)) { 218 debug("Timed out reading MII reg %02X\n", idx); 219 return -1; 220 } 221 222 smsc95xx_read_reg(dev, MII_DATA, &val); 223 224 return (u16)(val & 0xFFFF); 225 } 226 227 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx, 228 int regval) 229 { 230 u32 val, addr; 231 232 /* confirm MII not busy */ 233 if (smsc95xx_phy_wait_not_busy(dev)) { 234 debug("MII is busy in smsc95xx_mdio_write\n"); 235 return; 236 } 237 238 val = regval; 239 smsc95xx_write_reg(dev, MII_DATA, val); 240 241 /* set the address, index & direction (write to PHY) */ 242 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 243 smsc95xx_write_reg(dev, MII_ADDR, addr); 244 245 if (smsc95xx_phy_wait_not_busy(dev)) 246 debug("Timed out writing MII reg %02X\n", idx); 247 } 248 249 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev) 250 { 251 unsigned long start_time = get_timer(0); 252 u32 val; 253 254 do { 255 smsc95xx_read_reg(dev, E2P_CMD, &val); 256 if (!(val & E2P_CMD_LOADED_)) { 257 debug("No EEPROM present\n"); 258 return -1; 259 } 260 if (!(val & E2P_CMD_BUSY_)) 261 return 0; 262 udelay(40); 263 } while (get_timer(start_time) < 1 * 1000 * 1000); 264 265 debug("EEPROM is busy\n"); 266 return -1; 267 } 268 269 static int smsc95xx_wait_eeprom(struct ueth_data *dev) 270 { 271 unsigned long start_time = get_timer(0); 272 u32 val; 273 274 do { 275 smsc95xx_read_reg(dev, E2P_CMD, &val); 276 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 277 break; 278 udelay(40); 279 } while (get_timer(start_time) < 1 * 1000 * 1000); 280 281 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 282 debug("EEPROM read operation timeout\n"); 283 return -1; 284 } 285 return 0; 286 } 287 288 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length, 289 u8 *data) 290 { 291 u32 val; 292 int i, ret; 293 294 ret = smsc95xx_eeprom_confirm_not_busy(dev); 295 if (ret) 296 return ret; 297 298 for (i = 0; i < length; i++) { 299 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 300 smsc95xx_write_reg(dev, E2P_CMD, val); 301 302 ret = smsc95xx_wait_eeprom(dev); 303 if (ret < 0) 304 return ret; 305 306 smsc95xx_read_reg(dev, E2P_DATA, &val); 307 data[i] = val & 0xFF; 308 offset++; 309 } 310 return 0; 311 } 312 313 /* 314 * mii_nway_restart - restart NWay (autonegotiation) for this interface 315 * 316 * Returns 0 on success, negative on error. 317 */ 318 static int mii_nway_restart(struct ueth_data *dev) 319 { 320 int bmcr; 321 int r = -1; 322 323 /* if autoneg is off, it's an error */ 324 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR); 325 326 if (bmcr & BMCR_ANENABLE) { 327 bmcr |= BMCR_ANRESTART; 328 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 329 r = 0; 330 } 331 return r; 332 } 333 334 static int smsc95xx_phy_initialize(struct ueth_data *dev) 335 { 336 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 337 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 338 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 339 ADVERTISE_PAUSE_ASYM); 340 341 /* read to clear */ 342 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC); 343 344 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK, 345 PHY_INT_MASK_DEFAULT_); 346 mii_nway_restart(dev); 347 348 debug("phy initialised succesfully\n"); 349 return 0; 350 } 351 352 static int smsc95xx_init_mac_address(struct eth_device *eth, 353 struct ueth_data *dev) 354 { 355 /* try reading mac address from EEPROM */ 356 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 357 eth->enetaddr) == 0) { 358 if (is_valid_ether_addr(eth->enetaddr)) { 359 /* eeprom values are valid so use them */ 360 debug("MAC address read from EEPROM\n"); 361 return 0; 362 } 363 } 364 365 /* 366 * No eeprom, or eeprom values are invalid. Generating a random MAC 367 * address is not safe. Just return an error. 368 */ 369 return -1; 370 } 371 372 static int smsc95xx_write_hwaddr(struct eth_device *eth) 373 { 374 struct ueth_data *dev = (struct ueth_data *)eth->priv; 375 u32 addr_lo, addr_hi; 376 int ret; 377 378 /* set hardware address */ 379 debug("** %s()\n", __func__); 380 addr_lo = cpu_to_le32(*eth->enetaddr); 381 addr_hi = cpu_to_le16(*((u16 *)(eth->enetaddr + 4))); 382 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); 383 if (ret < 0) { 384 debug("Failed to write ADDRL: %d\n", ret); 385 return ret; 386 } 387 388 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); 389 if (ret < 0) 390 return ret; 391 debug("MAC %02x:%02x:%02x:%02x:%02x:%02x\n", 392 eth->enetaddr[0], eth->enetaddr[1], 393 eth->enetaddr[2], eth->enetaddr[3], 394 eth->enetaddr[4], eth->enetaddr[5]); 395 dev->have_hwaddr = 1; 396 return 0; 397 } 398 399 /* Enable or disable Tx & Rx checksum offload engines */ 400 static int smsc95xx_set_csums(struct ueth_data *dev, 401 int use_tx_csum, int use_rx_csum) 402 { 403 u32 read_buf; 404 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); 405 if (ret < 0) 406 return ret; 407 408 if (use_tx_csum) 409 read_buf |= Tx_COE_EN_; 410 else 411 read_buf &= ~Tx_COE_EN_; 412 413 if (use_rx_csum) 414 read_buf |= Rx_COE_EN_; 415 else 416 read_buf &= ~Rx_COE_EN_; 417 418 ret = smsc95xx_write_reg(dev, COE_CR, read_buf); 419 if (ret < 0) 420 return ret; 421 422 debug("COE_CR = 0x%08x\n", read_buf); 423 return 0; 424 } 425 426 static void smsc95xx_set_multicast(struct ueth_data *dev) 427 { 428 /* No multicast in u-boot */ 429 dev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 430 } 431 432 /* starts the TX path */ 433 static void smsc95xx_start_tx_path(struct ueth_data *dev) 434 { 435 u32 reg_val; 436 437 /* Enable Tx at MAC */ 438 dev->mac_cr |= MAC_CR_TXEN_; 439 440 smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr); 441 442 /* Enable Tx at SCSRs */ 443 reg_val = TX_CFG_ON_; 444 smsc95xx_write_reg(dev, TX_CFG, reg_val); 445 } 446 447 /* Starts the Receive path */ 448 static void smsc95xx_start_rx_path(struct ueth_data *dev) 449 { 450 dev->mac_cr |= MAC_CR_RXEN_; 451 smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr); 452 } 453 454 /* 455 * Smsc95xx callbacks 456 */ 457 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 458 { 459 int ret; 460 u32 write_buf; 461 u32 read_buf; 462 u32 burst_cap; 463 int timeout; 464 struct ueth_data *dev = (struct ueth_data *)eth->priv; 465 #define TIMEOUT_RESOLUTION 50 /* ms */ 466 int link_detected; 467 468 debug("** %s()\n", __func__); 469 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 470 471 write_buf = HW_CFG_LRST_; 472 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf); 473 if (ret < 0) 474 return ret; 475 476 timeout = 0; 477 do { 478 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 479 if (ret < 0) 480 return ret; 481 udelay(10 * 1000); 482 timeout++; 483 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 484 485 if (timeout >= 100) { 486 debug("timeout waiting for completion of Lite Reset\n"); 487 return -1; 488 } 489 490 write_buf = PM_CTL_PHY_RST_; 491 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf); 492 if (ret < 0) 493 return ret; 494 495 timeout = 0; 496 do { 497 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); 498 if (ret < 0) 499 return ret; 500 udelay(10 * 1000); 501 timeout++; 502 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 503 if (timeout >= 100) { 504 debug("timeout waiting for PHY Reset\n"); 505 return -1; 506 } 507 if (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) 508 dev->have_hwaddr = 1; 509 if (!dev->have_hwaddr) { 510 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 511 return -1; 512 } 513 if (smsc95xx_write_hwaddr(eth) < 0) 514 return -1; 515 516 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 517 if (ret < 0) 518 return ret; 519 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 520 521 read_buf |= HW_CFG_BIR_; 522 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 523 if (ret < 0) 524 return ret; 525 526 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 527 if (ret < 0) 528 return ret; 529 debug("Read Value from HW_CFG after writing " 530 "HW_CFG_BIR_: 0x%08x\n", read_buf); 531 532 #ifdef TURBO_MODE 533 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 534 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 535 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 536 } else { 537 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 538 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 539 } 540 #else 541 burst_cap = 0; 542 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 543 #endif 544 debug("rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); 545 546 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); 547 if (ret < 0) 548 return ret; 549 550 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); 551 if (ret < 0) 552 return ret; 553 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 554 555 read_buf = DEFAULT_BULK_IN_DELAY; 556 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf); 557 if (ret < 0) 558 return ret; 559 560 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); 561 if (ret < 0) 562 return ret; 563 debug("Read Value from BULK_IN_DLY after writing: " 564 "0x%08x\n", read_buf); 565 566 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 567 if (ret < 0) 568 return ret; 569 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 570 571 #ifdef TURBO_MODE 572 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 573 #endif 574 read_buf &= ~HW_CFG_RXDOFF_; 575 576 #define NET_IP_ALIGN 0 577 read_buf |= NET_IP_ALIGN << 9; 578 579 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 580 if (ret < 0) 581 return ret; 582 583 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 584 if (ret < 0) 585 return ret; 586 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 587 588 write_buf = 0xFFFFFFFF; 589 ret = smsc95xx_write_reg(dev, INT_STS, write_buf); 590 if (ret < 0) 591 return ret; 592 593 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); 594 if (ret < 0) 595 return ret; 596 debug("ID_REV = 0x%08x\n", read_buf); 597 598 /* Init Tx */ 599 write_buf = 0; 600 ret = smsc95xx_write_reg(dev, FLOW, write_buf); 601 if (ret < 0) 602 return ret; 603 604 read_buf = AFC_CFG_DEFAULT; 605 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf); 606 if (ret < 0) 607 return ret; 608 609 ret = smsc95xx_read_reg(dev, MAC_CR, &dev->mac_cr); 610 if (ret < 0) 611 return ret; 612 613 /* Init Rx. Set Vlan */ 614 write_buf = (u32)ETH_P_8021Q; 615 ret = smsc95xx_write_reg(dev, VLAN1, write_buf); 616 if (ret < 0) 617 return ret; 618 619 /* Disable checksum offload engines */ 620 ret = smsc95xx_set_csums(dev, 0, 0); 621 if (ret < 0) { 622 debug("Failed to set csum offload: %d\n", ret); 623 return ret; 624 } 625 smsc95xx_set_multicast(dev); 626 627 if (smsc95xx_phy_initialize(dev) < 0) 628 return -1; 629 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); 630 if (ret < 0) 631 return ret; 632 633 /* enable PHY interrupts */ 634 read_buf |= INT_EP_CTL_PHY_INT_; 635 636 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); 637 if (ret < 0) 638 return ret; 639 640 smsc95xx_start_tx_path(dev); 641 smsc95xx_start_rx_path(dev); 642 643 timeout = 0; 644 do { 645 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR) 646 & BMSR_LSTATUS; 647 if (!link_detected) { 648 if (timeout == 0) 649 printf("Waiting for Ethernet connection... "); 650 udelay(TIMEOUT_RESOLUTION * 1000); 651 timeout += TIMEOUT_RESOLUTION; 652 } 653 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 654 if (link_detected) { 655 if (timeout != 0) 656 printf("done.\n"); 657 } else { 658 printf("unable to connect.\n"); 659 return -1; 660 } 661 return 0; 662 } 663 664 static int smsc95xx_send(struct eth_device *eth, volatile void* packet, 665 int length) 666 { 667 struct ueth_data *dev = (struct ueth_data *)eth->priv; 668 int err; 669 int actual_len; 670 u32 tx_cmd_a; 671 u32 tx_cmd_b; 672 unsigned char msg[PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)]; 673 674 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 675 if (length > PKTSIZE) 676 return -1; 677 678 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 679 tx_cmd_b = (u32)length; 680 cpu_to_le32s(&tx_cmd_a); 681 cpu_to_le32s(&tx_cmd_b); 682 683 /* prepend cmd_a and cmd_b */ 684 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 685 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 686 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 687 length); 688 err = usb_bulk_msg(dev->pusb_dev, 689 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 690 (void *)msg, 691 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 692 &actual_len, 693 USB_BULK_SEND_TIMEOUT); 694 debug("Tx: len = %u, actual = %u, err = %d\n", 695 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 696 actual_len, err); 697 return err; 698 } 699 700 static int smsc95xx_recv(struct eth_device *eth) 701 { 702 struct ueth_data *dev = (struct ueth_data *)eth->priv; 703 static unsigned char recv_buf[AX_RX_URB_SIZE]; 704 unsigned char *buf_ptr; 705 int err; 706 int actual_len; 707 u32 packet_len; 708 int cur_buf_align; 709 710 debug("** %s()\n", __func__); 711 err = usb_bulk_msg(dev->pusb_dev, 712 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 713 (void *)recv_buf, 714 AX_RX_URB_SIZE, 715 &actual_len, 716 USB_BULK_RECV_TIMEOUT); 717 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 718 actual_len, err); 719 if (err != 0) { 720 debug("Rx: failed to receive\n"); 721 return -1; 722 } 723 if (actual_len > AX_RX_URB_SIZE) { 724 debug("Rx: received too many bytes %d\n", actual_len); 725 return -1; 726 } 727 728 buf_ptr = recv_buf; 729 while (actual_len > 0) { 730 /* 731 * 1st 4 bytes contain the length of the actual data plus error 732 * info. Extract data length. 733 */ 734 if (actual_len < sizeof(packet_len)) { 735 debug("Rx: incomplete packet length\n"); 736 return -1; 737 } 738 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 739 le32_to_cpus(&packet_len); 740 if (packet_len & RX_STS_ES_) { 741 debug("Rx: Error header=%#x", packet_len); 742 return -1; 743 } 744 packet_len = ((packet_len & RX_STS_FL_) >> 16); 745 746 if (packet_len > actual_len - sizeof(packet_len)) { 747 debug("Rx: too large packet: %d\n", packet_len); 748 return -1; 749 } 750 751 /* Notify net stack */ 752 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4); 753 754 /* Adjust for next iteration */ 755 actual_len -= sizeof(packet_len) + packet_len; 756 buf_ptr += sizeof(packet_len) + packet_len; 757 cur_buf_align = (int)buf_ptr - (int)recv_buf; 758 759 if (cur_buf_align & 0x03) { 760 int align = 4 - (cur_buf_align & 0x03); 761 762 actual_len -= align; 763 buf_ptr += align; 764 } 765 } 766 return err; 767 } 768 769 static void smsc95xx_halt(struct eth_device *eth) 770 { 771 debug("** %s()\n", __func__); 772 } 773 774 /* 775 * SMSC probing functions 776 */ 777 void smsc95xx_eth_before_probe(void) 778 { 779 curr_eth_dev = 0; 780 } 781 782 struct smsc95xx_dongle { 783 unsigned short vendor; 784 unsigned short product; 785 }; 786 787 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 788 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 789 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 790 { 0x0000, 0x0000 } /* END - Do not remove */ 791 }; 792 793 /* Probe to see if a new device is actually an SMSC device */ 794 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 795 struct ueth_data *ss) 796 { 797 struct usb_interface *iface; 798 struct usb_interface_descriptor *iface_desc; 799 int i; 800 801 /* let's examine the device now */ 802 iface = &dev->config.if_desc[ifnum]; 803 iface_desc = &dev->config.if_desc[ifnum].desc; 804 805 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 806 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 807 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 808 /* Found a supported dongle */ 809 break; 810 } 811 if (smsc95xx_dongles[i].vendor == 0) 812 return 0; 813 814 /* At this point, we know we've got a live one */ 815 debug("\n\nUSB Ethernet device detected\n"); 816 memset(ss, '\0', sizeof(struct ueth_data)); 817 818 /* Initialize the ueth_data structure with some useful info */ 819 ss->ifnum = ifnum; 820 ss->pusb_dev = dev; 821 ss->subclass = iface_desc->bInterfaceSubClass; 822 ss->protocol = iface_desc->bInterfaceProtocol; 823 824 /* 825 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 826 * We will ignore any others. 827 */ 828 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 829 /* is it an BULK endpoint? */ 830 if ((iface->ep_desc[i].bmAttributes & 831 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 832 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 833 ss->ep_in = 834 iface->ep_desc[i].bEndpointAddress & 835 USB_ENDPOINT_NUMBER_MASK; 836 else 837 ss->ep_out = 838 iface->ep_desc[i].bEndpointAddress & 839 USB_ENDPOINT_NUMBER_MASK; 840 } 841 842 /* is it an interrupt endpoint? */ 843 if ((iface->ep_desc[i].bmAttributes & 844 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 845 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 846 USB_ENDPOINT_NUMBER_MASK; 847 ss->irqinterval = iface->ep_desc[i].bInterval; 848 } 849 } 850 debug("Endpoints In %d Out %d Int %d\n", 851 ss->ep_in, ss->ep_out, ss->ep_int); 852 853 /* Do some basic sanity checks, and bail if we find a problem */ 854 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 855 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 856 debug("Problems with device\n"); 857 return 0; 858 } 859 dev->privptr = (void *)ss; 860 return 1; 861 } 862 863 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 864 struct eth_device *eth) 865 { 866 debug("** %s()\n", __func__); 867 if (!eth) { 868 debug("%s: missing parameter.\n", __func__); 869 return 0; 870 } 871 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 872 eth->init = smsc95xx_init; 873 eth->send = smsc95xx_send; 874 eth->recv = smsc95xx_recv; 875 eth->halt = smsc95xx_halt; 876 eth->write_hwaddr = smsc95xx_write_hwaddr; 877 eth->priv = ss; 878 return 1; 879 } 880