1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (C) 2009 NVIDIA, Corporation 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <asm/unaligned.h> 9 #include <common.h> 10 #include <usb.h> 11 #include <linux/mii.h> 12 #include "usb_ether.h" 13 #include <malloc.h> 14 15 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 16 17 /* Tx command words */ 18 #define TX_CMD_A_FIRST_SEG_ 0x00002000 19 #define TX_CMD_A_LAST_SEG_ 0x00001000 20 21 /* Rx status word */ 22 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 23 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 24 25 /* SCSRs */ 26 #define ID_REV 0x00 27 28 #define INT_STS 0x08 29 30 #define TX_CFG 0x10 31 #define TX_CFG_ON_ 0x00000004 32 33 #define HW_CFG 0x14 34 #define HW_CFG_BIR_ 0x00001000 35 #define HW_CFG_RXDOFF_ 0x00000600 36 #define HW_CFG_MEF_ 0x00000020 37 #define HW_CFG_BCE_ 0x00000002 38 #define HW_CFG_LRST_ 0x00000008 39 40 #define PM_CTRL 0x20 41 #define PM_CTL_PHY_RST_ 0x00000010 42 43 #define AFC_CFG 0x2C 44 45 /* 46 * Hi watermark = 15.5Kb (~10 mtu pkts) 47 * low watermark = 3k (~2 mtu pkts) 48 * backpressure duration = ~ 350us 49 * Apply FC on any frame. 50 */ 51 #define AFC_CFG_DEFAULT 0x00F830A1 52 53 #define E2P_CMD 0x30 54 #define E2P_CMD_BUSY_ 0x80000000 55 #define E2P_CMD_READ_ 0x00000000 56 #define E2P_CMD_TIMEOUT_ 0x00000400 57 #define E2P_CMD_LOADED_ 0x00000200 58 #define E2P_CMD_ADDR_ 0x000001FF 59 60 #define E2P_DATA 0x34 61 62 #define BURST_CAP 0x38 63 64 #define INT_EP_CTL 0x68 65 #define INT_EP_CTL_PHY_INT_ 0x00008000 66 67 #define BULK_IN_DLY 0x6C 68 69 /* MAC CSRs */ 70 #define MAC_CR 0x100 71 #define MAC_CR_MCPAS_ 0x00080000 72 #define MAC_CR_PRMS_ 0x00040000 73 #define MAC_CR_HPFILT_ 0x00002000 74 #define MAC_CR_TXEN_ 0x00000008 75 #define MAC_CR_RXEN_ 0x00000004 76 77 #define ADDRH 0x104 78 79 #define ADDRL 0x108 80 81 #define MII_ADDR 0x114 82 #define MII_WRITE_ 0x02 83 #define MII_BUSY_ 0x01 84 #define MII_READ_ 0x00 /* ~of MII Write bit */ 85 86 #define MII_DATA 0x118 87 88 #define FLOW 0x11C 89 90 #define VLAN1 0x120 91 92 #define COE_CR 0x130 93 #define Tx_COE_EN_ 0x00010000 94 #define Rx_COE_EN_ 0x00000001 95 96 /* Vendor-specific PHY Definitions */ 97 #define PHY_INT_SRC 29 98 99 #define PHY_INT_MASK 30 100 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 101 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 102 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 103 PHY_INT_MASK_LINK_DOWN_) 104 105 /* USB Vendor Requests */ 106 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 107 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 108 109 /* Some extra defines */ 110 #define HS_USB_PKT_SIZE 512 111 #define FS_USB_PKT_SIZE 64 112 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 113 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 114 #define DEFAULT_BULK_IN_DELAY 0x00002000 115 #define MAX_SINGLE_PACKET_SIZE 2048 116 #define EEPROM_MAC_OFFSET 0x01 117 #define SMSC95XX_INTERNAL_PHY_ID 1 118 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 119 120 /* local defines */ 121 #define SMSC95XX_BASE_NAME "sms" 122 #define USB_CTRL_SET_TIMEOUT 5000 123 #define USB_CTRL_GET_TIMEOUT 5000 124 #define USB_BULK_SEND_TIMEOUT 5000 125 #define USB_BULK_RECV_TIMEOUT 5000 126 127 #define AX_RX_URB_SIZE 2048 128 #define PHY_CONNECT_TIMEOUT 5000 129 130 #define TURBO_MODE 131 132 /* local vars */ 133 static int curr_eth_dev; /* index for name of next device detected */ 134 135 /* driver private */ 136 struct smsc95xx_private { 137 size_t rx_urb_size; /* maximum USB URB size */ 138 u32 mac_cr; /* MAC control register value */ 139 int have_hwaddr; /* 1 if we have a hardware MAC address */ 140 }; 141 142 /* 143 * Smsc95xx infrastructure commands 144 */ 145 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) 146 { 147 int len; 148 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 149 150 cpu_to_le32s(&data); 151 tmpbuf[0] = data; 152 153 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0), 154 USB_VENDOR_REQUEST_WRITE_REGISTER, 155 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 156 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT); 157 if (len != sizeof(data)) { 158 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 159 index, data, len); 160 return -1; 161 } 162 return 0; 163 } 164 165 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data) 166 { 167 int len; 168 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 169 170 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0), 171 USB_VENDOR_REQUEST_READ_REGISTER, 172 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 173 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT); 174 *data = tmpbuf[0]; 175 if (len != sizeof(data)) { 176 debug("smsc95xx_read_reg failed: index=%d, len=%d", 177 index, len); 178 return -1; 179 } 180 181 le32_to_cpus(data); 182 return 0; 183 } 184 185 /* Loop until the read is completed with timeout */ 186 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev) 187 { 188 unsigned long start_time = get_timer(0); 189 u32 val; 190 191 do { 192 smsc95xx_read_reg(dev, MII_ADDR, &val); 193 if (!(val & MII_BUSY_)) 194 return 0; 195 } while (get_timer(start_time) < 1 * 1000 * 1000); 196 197 return -1; 198 } 199 200 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx) 201 { 202 u32 val, addr; 203 204 /* confirm MII not busy */ 205 if (smsc95xx_phy_wait_not_busy(dev)) { 206 debug("MII is busy in smsc95xx_mdio_read\n"); 207 return -1; 208 } 209 210 /* set the address, index & direction (read from PHY) */ 211 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 212 smsc95xx_write_reg(dev, MII_ADDR, addr); 213 214 if (smsc95xx_phy_wait_not_busy(dev)) { 215 debug("Timed out reading MII reg %02X\n", idx); 216 return -1; 217 } 218 219 smsc95xx_read_reg(dev, MII_DATA, &val); 220 221 return (u16)(val & 0xFFFF); 222 } 223 224 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx, 225 int regval) 226 { 227 u32 val, addr; 228 229 /* confirm MII not busy */ 230 if (smsc95xx_phy_wait_not_busy(dev)) { 231 debug("MII is busy in smsc95xx_mdio_write\n"); 232 return; 233 } 234 235 val = regval; 236 smsc95xx_write_reg(dev, MII_DATA, val); 237 238 /* set the address, index & direction (write to PHY) */ 239 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 240 smsc95xx_write_reg(dev, MII_ADDR, addr); 241 242 if (smsc95xx_phy_wait_not_busy(dev)) 243 debug("Timed out writing MII reg %02X\n", idx); 244 } 245 246 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev) 247 { 248 unsigned long start_time = get_timer(0); 249 u32 val; 250 251 do { 252 smsc95xx_read_reg(dev, E2P_CMD, &val); 253 if (!(val & E2P_CMD_BUSY_)) 254 return 0; 255 udelay(40); 256 } while (get_timer(start_time) < 1 * 1000 * 1000); 257 258 debug("EEPROM is busy\n"); 259 return -1; 260 } 261 262 static int smsc95xx_wait_eeprom(struct ueth_data *dev) 263 { 264 unsigned long start_time = get_timer(0); 265 u32 val; 266 267 do { 268 smsc95xx_read_reg(dev, E2P_CMD, &val); 269 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 270 break; 271 udelay(40); 272 } while (get_timer(start_time) < 1 * 1000 * 1000); 273 274 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 275 debug("EEPROM read operation timeout\n"); 276 return -1; 277 } 278 return 0; 279 } 280 281 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length, 282 u8 *data) 283 { 284 u32 val; 285 int i, ret; 286 287 ret = smsc95xx_eeprom_confirm_not_busy(dev); 288 if (ret) 289 return ret; 290 291 for (i = 0; i < length; i++) { 292 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 293 smsc95xx_write_reg(dev, E2P_CMD, val); 294 295 ret = smsc95xx_wait_eeprom(dev); 296 if (ret < 0) 297 return ret; 298 299 smsc95xx_read_reg(dev, E2P_DATA, &val); 300 data[i] = val & 0xFF; 301 offset++; 302 } 303 return 0; 304 } 305 306 /* 307 * mii_nway_restart - restart NWay (autonegotiation) for this interface 308 * 309 * Returns 0 on success, negative on error. 310 */ 311 static int mii_nway_restart(struct ueth_data *dev) 312 { 313 int bmcr; 314 int r = -1; 315 316 /* if autoneg is off, it's an error */ 317 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR); 318 319 if (bmcr & BMCR_ANENABLE) { 320 bmcr |= BMCR_ANRESTART; 321 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 322 r = 0; 323 } 324 return r; 325 } 326 327 static int smsc95xx_phy_initialize(struct ueth_data *dev) 328 { 329 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 330 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 331 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 332 ADVERTISE_PAUSE_ASYM); 333 334 /* read to clear */ 335 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC); 336 337 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK, 338 PHY_INT_MASK_DEFAULT_); 339 mii_nway_restart(dev); 340 341 debug("phy initialised succesfully\n"); 342 return 0; 343 } 344 345 static int smsc95xx_init_mac_address(struct eth_device *eth, 346 struct ueth_data *dev) 347 { 348 /* try reading mac address from EEPROM */ 349 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 350 eth->enetaddr) == 0) { 351 if (is_valid_ether_addr(eth->enetaddr)) { 352 /* eeprom values are valid so use them */ 353 debug("MAC address read from EEPROM\n"); 354 return 0; 355 } 356 } 357 358 /* 359 * No eeprom, or eeprom values are invalid. Generating a random MAC 360 * address is not safe. Just return an error. 361 */ 362 return -1; 363 } 364 365 static int smsc95xx_write_hwaddr(struct eth_device *eth) 366 { 367 struct ueth_data *dev = (struct ueth_data *)eth->priv; 368 struct smsc95xx_private *priv = dev->dev_priv; 369 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]); 370 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]); 371 int ret; 372 373 /* set hardware address */ 374 debug("** %s()\n", __func__); 375 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); 376 if (ret < 0) 377 return ret; 378 379 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); 380 if (ret < 0) 381 return ret; 382 383 debug("MAC %pM\n", eth->enetaddr); 384 priv->have_hwaddr = 1; 385 return 0; 386 } 387 388 /* Enable or disable Tx & Rx checksum offload engines */ 389 static int smsc95xx_set_csums(struct ueth_data *dev, 390 int use_tx_csum, int use_rx_csum) 391 { 392 u32 read_buf; 393 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); 394 if (ret < 0) 395 return ret; 396 397 if (use_tx_csum) 398 read_buf |= Tx_COE_EN_; 399 else 400 read_buf &= ~Tx_COE_EN_; 401 402 if (use_rx_csum) 403 read_buf |= Rx_COE_EN_; 404 else 405 read_buf &= ~Rx_COE_EN_; 406 407 ret = smsc95xx_write_reg(dev, COE_CR, read_buf); 408 if (ret < 0) 409 return ret; 410 411 debug("COE_CR = 0x%08x\n", read_buf); 412 return 0; 413 } 414 415 static void smsc95xx_set_multicast(struct ueth_data *dev) 416 { 417 struct smsc95xx_private *priv = dev->dev_priv; 418 419 /* No multicast in u-boot */ 420 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 421 } 422 423 /* starts the TX path */ 424 static void smsc95xx_start_tx_path(struct ueth_data *dev) 425 { 426 struct smsc95xx_private *priv = dev->dev_priv; 427 u32 reg_val; 428 429 /* Enable Tx at MAC */ 430 priv->mac_cr |= MAC_CR_TXEN_; 431 432 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 433 434 /* Enable Tx at SCSRs */ 435 reg_val = TX_CFG_ON_; 436 smsc95xx_write_reg(dev, TX_CFG, reg_val); 437 } 438 439 /* Starts the Receive path */ 440 static void smsc95xx_start_rx_path(struct ueth_data *dev) 441 { 442 struct smsc95xx_private *priv = dev->dev_priv; 443 444 priv->mac_cr |= MAC_CR_RXEN_; 445 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 446 } 447 448 /* 449 * Smsc95xx callbacks 450 */ 451 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 452 { 453 int ret; 454 u32 write_buf; 455 u32 read_buf; 456 u32 burst_cap; 457 int timeout; 458 struct ueth_data *dev = (struct ueth_data *)eth->priv; 459 struct smsc95xx_private *priv = 460 (struct smsc95xx_private *)dev->dev_priv; 461 #define TIMEOUT_RESOLUTION 50 /* ms */ 462 int link_detected; 463 464 debug("** %s()\n", __func__); 465 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 466 467 write_buf = HW_CFG_LRST_; 468 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf); 469 if (ret < 0) 470 return ret; 471 472 timeout = 0; 473 do { 474 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 475 if (ret < 0) 476 return ret; 477 udelay(10 * 1000); 478 timeout++; 479 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 480 481 if (timeout >= 100) { 482 debug("timeout waiting for completion of Lite Reset\n"); 483 return -1; 484 } 485 486 write_buf = PM_CTL_PHY_RST_; 487 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf); 488 if (ret < 0) 489 return ret; 490 491 timeout = 0; 492 do { 493 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); 494 if (ret < 0) 495 return ret; 496 udelay(10 * 1000); 497 timeout++; 498 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 499 if (timeout >= 100) { 500 debug("timeout waiting for PHY Reset\n"); 501 return -1; 502 } 503 if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) 504 priv->have_hwaddr = 1; 505 if (!priv->have_hwaddr) { 506 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 507 return -1; 508 } 509 if (smsc95xx_write_hwaddr(eth) < 0) 510 return -1; 511 512 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 513 if (ret < 0) 514 return ret; 515 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 516 517 read_buf |= HW_CFG_BIR_; 518 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 519 if (ret < 0) 520 return ret; 521 522 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 523 if (ret < 0) 524 return ret; 525 debug("Read Value from HW_CFG after writing " 526 "HW_CFG_BIR_: 0x%08x\n", read_buf); 527 528 #ifdef TURBO_MODE 529 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 530 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 531 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 532 } else { 533 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 534 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 535 } 536 #else 537 burst_cap = 0; 538 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 539 #endif 540 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); 541 542 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); 543 if (ret < 0) 544 return ret; 545 546 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); 547 if (ret < 0) 548 return ret; 549 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 550 551 read_buf = DEFAULT_BULK_IN_DELAY; 552 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf); 553 if (ret < 0) 554 return ret; 555 556 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); 557 if (ret < 0) 558 return ret; 559 debug("Read Value from BULK_IN_DLY after writing: " 560 "0x%08x\n", read_buf); 561 562 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 563 if (ret < 0) 564 return ret; 565 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 566 567 #ifdef TURBO_MODE 568 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 569 #endif 570 read_buf &= ~HW_CFG_RXDOFF_; 571 572 #define NET_IP_ALIGN 0 573 read_buf |= NET_IP_ALIGN << 9; 574 575 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 576 if (ret < 0) 577 return ret; 578 579 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 580 if (ret < 0) 581 return ret; 582 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 583 584 write_buf = 0xFFFFFFFF; 585 ret = smsc95xx_write_reg(dev, INT_STS, write_buf); 586 if (ret < 0) 587 return ret; 588 589 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); 590 if (ret < 0) 591 return ret; 592 debug("ID_REV = 0x%08x\n", read_buf); 593 594 /* Init Tx */ 595 write_buf = 0; 596 ret = smsc95xx_write_reg(dev, FLOW, write_buf); 597 if (ret < 0) 598 return ret; 599 600 read_buf = AFC_CFG_DEFAULT; 601 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf); 602 if (ret < 0) 603 return ret; 604 605 ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr); 606 if (ret < 0) 607 return ret; 608 609 /* Init Rx. Set Vlan */ 610 write_buf = (u32)ETH_P_8021Q; 611 ret = smsc95xx_write_reg(dev, VLAN1, write_buf); 612 if (ret < 0) 613 return ret; 614 615 /* Disable checksum offload engines */ 616 ret = smsc95xx_set_csums(dev, 0, 0); 617 if (ret < 0) { 618 debug("Failed to set csum offload: %d\n", ret); 619 return ret; 620 } 621 smsc95xx_set_multicast(dev); 622 623 if (smsc95xx_phy_initialize(dev) < 0) 624 return -1; 625 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); 626 if (ret < 0) 627 return ret; 628 629 /* enable PHY interrupts */ 630 read_buf |= INT_EP_CTL_PHY_INT_; 631 632 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); 633 if (ret < 0) 634 return ret; 635 636 smsc95xx_start_tx_path(dev); 637 smsc95xx_start_rx_path(dev); 638 639 timeout = 0; 640 do { 641 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR) 642 & BMSR_LSTATUS; 643 if (!link_detected) { 644 if (timeout == 0) 645 printf("Waiting for Ethernet connection... "); 646 udelay(TIMEOUT_RESOLUTION * 1000); 647 timeout += TIMEOUT_RESOLUTION; 648 } 649 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 650 if (link_detected) { 651 if (timeout != 0) 652 printf("done.\n"); 653 } else { 654 printf("unable to connect.\n"); 655 return -1; 656 } 657 return 0; 658 } 659 660 static int smsc95xx_send(struct eth_device *eth, void* packet, int length) 661 { 662 struct ueth_data *dev = (struct ueth_data *)eth->priv; 663 int err; 664 int actual_len; 665 u32 tx_cmd_a; 666 u32 tx_cmd_b; 667 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 668 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); 669 670 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 671 if (length > PKTSIZE) 672 return -1; 673 674 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 675 tx_cmd_b = (u32)length; 676 cpu_to_le32s(&tx_cmd_a); 677 cpu_to_le32s(&tx_cmd_b); 678 679 /* prepend cmd_a and cmd_b */ 680 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 681 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 682 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 683 length); 684 err = usb_bulk_msg(dev->pusb_dev, 685 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 686 (void *)msg, 687 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 688 &actual_len, 689 USB_BULK_SEND_TIMEOUT); 690 debug("Tx: len = %u, actual = %u, err = %d\n", 691 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 692 actual_len, err); 693 return err; 694 } 695 696 static int smsc95xx_recv(struct eth_device *eth) 697 { 698 struct ueth_data *dev = (struct ueth_data *)eth->priv; 699 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); 700 unsigned char *buf_ptr; 701 int err; 702 int actual_len; 703 u32 packet_len; 704 int cur_buf_align; 705 706 debug("** %s()\n", __func__); 707 err = usb_bulk_msg(dev->pusb_dev, 708 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 709 (void *)recv_buf, 710 AX_RX_URB_SIZE, 711 &actual_len, 712 USB_BULK_RECV_TIMEOUT); 713 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 714 actual_len, err); 715 if (err != 0) { 716 debug("Rx: failed to receive\n"); 717 return -1; 718 } 719 if (actual_len > AX_RX_URB_SIZE) { 720 debug("Rx: received too many bytes %d\n", actual_len); 721 return -1; 722 } 723 724 buf_ptr = recv_buf; 725 while (actual_len > 0) { 726 /* 727 * 1st 4 bytes contain the length of the actual data plus error 728 * info. Extract data length. 729 */ 730 if (actual_len < sizeof(packet_len)) { 731 debug("Rx: incomplete packet length\n"); 732 return -1; 733 } 734 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 735 le32_to_cpus(&packet_len); 736 if (packet_len & RX_STS_ES_) { 737 debug("Rx: Error header=%#x", packet_len); 738 return -1; 739 } 740 packet_len = ((packet_len & RX_STS_FL_) >> 16); 741 742 if (packet_len > actual_len - sizeof(packet_len)) { 743 debug("Rx: too large packet: %d\n", packet_len); 744 return -1; 745 } 746 747 /* Notify net stack */ 748 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4); 749 750 /* Adjust for next iteration */ 751 actual_len -= sizeof(packet_len) + packet_len; 752 buf_ptr += sizeof(packet_len) + packet_len; 753 cur_buf_align = (int)buf_ptr - (int)recv_buf; 754 755 if (cur_buf_align & 0x03) { 756 int align = 4 - (cur_buf_align & 0x03); 757 758 actual_len -= align; 759 buf_ptr += align; 760 } 761 } 762 return err; 763 } 764 765 static void smsc95xx_halt(struct eth_device *eth) 766 { 767 debug("** %s()\n", __func__); 768 } 769 770 /* 771 * SMSC probing functions 772 */ 773 void smsc95xx_eth_before_probe(void) 774 { 775 curr_eth_dev = 0; 776 } 777 778 struct smsc95xx_dongle { 779 unsigned short vendor; 780 unsigned short product; 781 }; 782 783 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 784 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 785 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 786 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ 787 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */ 788 { 0x0000, 0x0000 } /* END - Do not remove */ 789 }; 790 791 /* Probe to see if a new device is actually an SMSC device */ 792 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 793 struct ueth_data *ss) 794 { 795 struct usb_interface *iface; 796 struct usb_interface_descriptor *iface_desc; 797 int i; 798 799 /* let's examine the device now */ 800 iface = &dev->config.if_desc[ifnum]; 801 iface_desc = &dev->config.if_desc[ifnum].desc; 802 803 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 804 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 805 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 806 /* Found a supported dongle */ 807 break; 808 } 809 if (smsc95xx_dongles[i].vendor == 0) 810 return 0; 811 812 /* At this point, we know we've got a live one */ 813 debug("\n\nUSB Ethernet device detected\n"); 814 memset(ss, '\0', sizeof(struct ueth_data)); 815 816 /* Initialize the ueth_data structure with some useful info */ 817 ss->ifnum = ifnum; 818 ss->pusb_dev = dev; 819 ss->subclass = iface_desc->bInterfaceSubClass; 820 ss->protocol = iface_desc->bInterfaceProtocol; 821 822 /* 823 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 824 * We will ignore any others. 825 */ 826 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 827 /* is it an BULK endpoint? */ 828 if ((iface->ep_desc[i].bmAttributes & 829 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 830 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 831 ss->ep_in = 832 iface->ep_desc[i].bEndpointAddress & 833 USB_ENDPOINT_NUMBER_MASK; 834 else 835 ss->ep_out = 836 iface->ep_desc[i].bEndpointAddress & 837 USB_ENDPOINT_NUMBER_MASK; 838 } 839 840 /* is it an interrupt endpoint? */ 841 if ((iface->ep_desc[i].bmAttributes & 842 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 843 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 844 USB_ENDPOINT_NUMBER_MASK; 845 ss->irqinterval = iface->ep_desc[i].bInterval; 846 } 847 } 848 debug("Endpoints In %d Out %d Int %d\n", 849 ss->ep_in, ss->ep_out, ss->ep_int); 850 851 /* Do some basic sanity checks, and bail if we find a problem */ 852 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 853 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 854 debug("Problems with device\n"); 855 return 0; 856 } 857 dev->privptr = (void *)ss; 858 859 /* alloc driver private */ 860 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); 861 if (!ss->dev_priv) 862 return 0; 863 864 return 1; 865 } 866 867 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 868 struct eth_device *eth) 869 { 870 debug("** %s()\n", __func__); 871 if (!eth) { 872 debug("%s: missing parameter.\n", __func__); 873 return 0; 874 } 875 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 876 eth->init = smsc95xx_init; 877 eth->send = smsc95xx_send; 878 eth->recv = smsc95xx_recv; 879 eth->halt = smsc95xx_halt; 880 eth->write_hwaddr = smsc95xx_write_hwaddr; 881 eth->priv = ss; 882 return 1; 883 } 884