1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (C) 2009 NVIDIA, Corporation 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <asm/unaligned.h> 24 #include <common.h> 25 #include <usb.h> 26 #include <linux/mii.h> 27 #include "usb_ether.h" 28 #include <malloc.h> 29 30 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 31 32 /* Tx command words */ 33 #define TX_CMD_A_FIRST_SEG_ 0x00002000 34 #define TX_CMD_A_LAST_SEG_ 0x00001000 35 36 /* Rx status word */ 37 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 38 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 39 40 /* SCSRs */ 41 #define ID_REV 0x00 42 43 #define INT_STS 0x08 44 45 #define TX_CFG 0x10 46 #define TX_CFG_ON_ 0x00000004 47 48 #define HW_CFG 0x14 49 #define HW_CFG_BIR_ 0x00001000 50 #define HW_CFG_RXDOFF_ 0x00000600 51 #define HW_CFG_MEF_ 0x00000020 52 #define HW_CFG_BCE_ 0x00000002 53 #define HW_CFG_LRST_ 0x00000008 54 55 #define PM_CTRL 0x20 56 #define PM_CTL_PHY_RST_ 0x00000010 57 58 #define AFC_CFG 0x2C 59 60 /* 61 * Hi watermark = 15.5Kb (~10 mtu pkts) 62 * low watermark = 3k (~2 mtu pkts) 63 * backpressure duration = ~ 350us 64 * Apply FC on any frame. 65 */ 66 #define AFC_CFG_DEFAULT 0x00F830A1 67 68 #define E2P_CMD 0x30 69 #define E2P_CMD_BUSY_ 0x80000000 70 #define E2P_CMD_READ_ 0x00000000 71 #define E2P_CMD_TIMEOUT_ 0x00000400 72 #define E2P_CMD_LOADED_ 0x00000200 73 #define E2P_CMD_ADDR_ 0x000001FF 74 75 #define E2P_DATA 0x34 76 77 #define BURST_CAP 0x38 78 79 #define INT_EP_CTL 0x68 80 #define INT_EP_CTL_PHY_INT_ 0x00008000 81 82 #define BULK_IN_DLY 0x6C 83 84 /* MAC CSRs */ 85 #define MAC_CR 0x100 86 #define MAC_CR_MCPAS_ 0x00080000 87 #define MAC_CR_PRMS_ 0x00040000 88 #define MAC_CR_HPFILT_ 0x00002000 89 #define MAC_CR_TXEN_ 0x00000008 90 #define MAC_CR_RXEN_ 0x00000004 91 92 #define ADDRH 0x104 93 94 #define ADDRL 0x108 95 96 #define MII_ADDR 0x114 97 #define MII_WRITE_ 0x02 98 #define MII_BUSY_ 0x01 99 #define MII_READ_ 0x00 /* ~of MII Write bit */ 100 101 #define MII_DATA 0x118 102 103 #define FLOW 0x11C 104 105 #define VLAN1 0x120 106 107 #define COE_CR 0x130 108 #define Tx_COE_EN_ 0x00010000 109 #define Rx_COE_EN_ 0x00000001 110 111 /* Vendor-specific PHY Definitions */ 112 #define PHY_INT_SRC 29 113 114 #define PHY_INT_MASK 30 115 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 116 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 117 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 118 PHY_INT_MASK_LINK_DOWN_) 119 120 /* USB Vendor Requests */ 121 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 122 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 123 124 /* Some extra defines */ 125 #define HS_USB_PKT_SIZE 512 126 #define FS_USB_PKT_SIZE 64 127 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 128 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 129 #define DEFAULT_BULK_IN_DELAY 0x00002000 130 #define MAX_SINGLE_PACKET_SIZE 2048 131 #define EEPROM_MAC_OFFSET 0x01 132 #define SMSC95XX_INTERNAL_PHY_ID 1 133 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 134 135 /* local defines */ 136 #define SMSC95XX_BASE_NAME "sms" 137 #define USB_CTRL_SET_TIMEOUT 5000 138 #define USB_CTRL_GET_TIMEOUT 5000 139 #define USB_BULK_SEND_TIMEOUT 5000 140 #define USB_BULK_RECV_TIMEOUT 5000 141 142 #define AX_RX_URB_SIZE 2048 143 #define PHY_CONNECT_TIMEOUT 5000 144 145 #define TURBO_MODE 146 147 /* local vars */ 148 static int curr_eth_dev; /* index for name of next device detected */ 149 150 /* driver private */ 151 struct smsc95xx_private { 152 size_t rx_urb_size; /* maximum USB URB size */ 153 u32 mac_cr; /* MAC control register value */ 154 int have_hwaddr; /* 1 if we have a hardware MAC address */ 155 }; 156 157 /* 158 * Smsc95xx infrastructure commands 159 */ 160 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) 161 { 162 int len; 163 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 164 165 cpu_to_le32s(&data); 166 tmpbuf[0] = data; 167 168 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0), 169 USB_VENDOR_REQUEST_WRITE_REGISTER, 170 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 171 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT); 172 if (len != sizeof(data)) { 173 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 174 index, data, len); 175 return -1; 176 } 177 return 0; 178 } 179 180 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data) 181 { 182 int len; 183 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 184 185 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0), 186 USB_VENDOR_REQUEST_READ_REGISTER, 187 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 188 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT); 189 *data = tmpbuf[0]; 190 if (len != sizeof(data)) { 191 debug("smsc95xx_read_reg failed: index=%d, len=%d", 192 index, len); 193 return -1; 194 } 195 196 le32_to_cpus(data); 197 return 0; 198 } 199 200 /* Loop until the read is completed with timeout */ 201 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev) 202 { 203 unsigned long start_time = get_timer(0); 204 u32 val; 205 206 do { 207 smsc95xx_read_reg(dev, MII_ADDR, &val); 208 if (!(val & MII_BUSY_)) 209 return 0; 210 } while (get_timer(start_time) < 1 * 1000 * 1000); 211 212 return -1; 213 } 214 215 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx) 216 { 217 u32 val, addr; 218 219 /* confirm MII not busy */ 220 if (smsc95xx_phy_wait_not_busy(dev)) { 221 debug("MII is busy in smsc95xx_mdio_read\n"); 222 return -1; 223 } 224 225 /* set the address, index & direction (read from PHY) */ 226 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 227 smsc95xx_write_reg(dev, MII_ADDR, addr); 228 229 if (smsc95xx_phy_wait_not_busy(dev)) { 230 debug("Timed out reading MII reg %02X\n", idx); 231 return -1; 232 } 233 234 smsc95xx_read_reg(dev, MII_DATA, &val); 235 236 return (u16)(val & 0xFFFF); 237 } 238 239 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx, 240 int regval) 241 { 242 u32 val, addr; 243 244 /* confirm MII not busy */ 245 if (smsc95xx_phy_wait_not_busy(dev)) { 246 debug("MII is busy in smsc95xx_mdio_write\n"); 247 return; 248 } 249 250 val = regval; 251 smsc95xx_write_reg(dev, MII_DATA, val); 252 253 /* set the address, index & direction (write to PHY) */ 254 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 255 smsc95xx_write_reg(dev, MII_ADDR, addr); 256 257 if (smsc95xx_phy_wait_not_busy(dev)) 258 debug("Timed out writing MII reg %02X\n", idx); 259 } 260 261 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev) 262 { 263 unsigned long start_time = get_timer(0); 264 u32 val; 265 266 do { 267 smsc95xx_read_reg(dev, E2P_CMD, &val); 268 if (!(val & E2P_CMD_LOADED_)) { 269 debug("No EEPROM present\n"); 270 return -1; 271 } 272 if (!(val & E2P_CMD_BUSY_)) 273 return 0; 274 udelay(40); 275 } while (get_timer(start_time) < 1 * 1000 * 1000); 276 277 debug("EEPROM is busy\n"); 278 return -1; 279 } 280 281 static int smsc95xx_wait_eeprom(struct ueth_data *dev) 282 { 283 unsigned long start_time = get_timer(0); 284 u32 val; 285 286 do { 287 smsc95xx_read_reg(dev, E2P_CMD, &val); 288 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 289 break; 290 udelay(40); 291 } while (get_timer(start_time) < 1 * 1000 * 1000); 292 293 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 294 debug("EEPROM read operation timeout\n"); 295 return -1; 296 } 297 return 0; 298 } 299 300 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length, 301 u8 *data) 302 { 303 u32 val; 304 int i, ret; 305 306 ret = smsc95xx_eeprom_confirm_not_busy(dev); 307 if (ret) 308 return ret; 309 310 for (i = 0; i < length; i++) { 311 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 312 smsc95xx_write_reg(dev, E2P_CMD, val); 313 314 ret = smsc95xx_wait_eeprom(dev); 315 if (ret < 0) 316 return ret; 317 318 smsc95xx_read_reg(dev, E2P_DATA, &val); 319 data[i] = val & 0xFF; 320 offset++; 321 } 322 return 0; 323 } 324 325 /* 326 * mii_nway_restart - restart NWay (autonegotiation) for this interface 327 * 328 * Returns 0 on success, negative on error. 329 */ 330 static int mii_nway_restart(struct ueth_data *dev) 331 { 332 int bmcr; 333 int r = -1; 334 335 /* if autoneg is off, it's an error */ 336 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR); 337 338 if (bmcr & BMCR_ANENABLE) { 339 bmcr |= BMCR_ANRESTART; 340 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 341 r = 0; 342 } 343 return r; 344 } 345 346 static int smsc95xx_phy_initialize(struct ueth_data *dev) 347 { 348 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 349 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 350 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 351 ADVERTISE_PAUSE_ASYM); 352 353 /* read to clear */ 354 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC); 355 356 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK, 357 PHY_INT_MASK_DEFAULT_); 358 mii_nway_restart(dev); 359 360 debug("phy initialised succesfully\n"); 361 return 0; 362 } 363 364 static int smsc95xx_init_mac_address(struct eth_device *eth, 365 struct ueth_data *dev) 366 { 367 /* try reading mac address from EEPROM */ 368 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 369 eth->enetaddr) == 0) { 370 if (is_valid_ether_addr(eth->enetaddr)) { 371 /* eeprom values are valid so use them */ 372 debug("MAC address read from EEPROM\n"); 373 return 0; 374 } 375 } 376 377 /* 378 * No eeprom, or eeprom values are invalid. Generating a random MAC 379 * address is not safe. Just return an error. 380 */ 381 return -1; 382 } 383 384 static int smsc95xx_write_hwaddr(struct eth_device *eth) 385 { 386 struct ueth_data *dev = (struct ueth_data *)eth->priv; 387 struct smsc95xx_private *priv = dev->dev_priv; 388 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]); 389 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]); 390 int ret; 391 392 /* set hardware address */ 393 debug("** %s()\n", __func__); 394 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); 395 if (ret < 0) 396 return ret; 397 398 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); 399 if (ret < 0) 400 return ret; 401 402 debug("MAC %pM\n", eth->enetaddr); 403 priv->have_hwaddr = 1; 404 return 0; 405 } 406 407 /* Enable or disable Tx & Rx checksum offload engines */ 408 static int smsc95xx_set_csums(struct ueth_data *dev, 409 int use_tx_csum, int use_rx_csum) 410 { 411 u32 read_buf; 412 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); 413 if (ret < 0) 414 return ret; 415 416 if (use_tx_csum) 417 read_buf |= Tx_COE_EN_; 418 else 419 read_buf &= ~Tx_COE_EN_; 420 421 if (use_rx_csum) 422 read_buf |= Rx_COE_EN_; 423 else 424 read_buf &= ~Rx_COE_EN_; 425 426 ret = smsc95xx_write_reg(dev, COE_CR, read_buf); 427 if (ret < 0) 428 return ret; 429 430 debug("COE_CR = 0x%08x\n", read_buf); 431 return 0; 432 } 433 434 static void smsc95xx_set_multicast(struct ueth_data *dev) 435 { 436 struct smsc95xx_private *priv = dev->dev_priv; 437 438 /* No multicast in u-boot */ 439 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 440 } 441 442 /* starts the TX path */ 443 static void smsc95xx_start_tx_path(struct ueth_data *dev) 444 { 445 struct smsc95xx_private *priv = dev->dev_priv; 446 u32 reg_val; 447 448 /* Enable Tx at MAC */ 449 priv->mac_cr |= MAC_CR_TXEN_; 450 451 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 452 453 /* Enable Tx at SCSRs */ 454 reg_val = TX_CFG_ON_; 455 smsc95xx_write_reg(dev, TX_CFG, reg_val); 456 } 457 458 /* Starts the Receive path */ 459 static void smsc95xx_start_rx_path(struct ueth_data *dev) 460 { 461 struct smsc95xx_private *priv = dev->dev_priv; 462 463 priv->mac_cr |= MAC_CR_RXEN_; 464 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 465 } 466 467 /* 468 * Smsc95xx callbacks 469 */ 470 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 471 { 472 int ret; 473 u32 write_buf; 474 u32 read_buf; 475 u32 burst_cap; 476 int timeout; 477 struct ueth_data *dev = (struct ueth_data *)eth->priv; 478 struct smsc95xx_private *priv = 479 (struct smsc95xx_private *)dev->dev_priv; 480 #define TIMEOUT_RESOLUTION 50 /* ms */ 481 int link_detected; 482 483 debug("** %s()\n", __func__); 484 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 485 486 write_buf = HW_CFG_LRST_; 487 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf); 488 if (ret < 0) 489 return ret; 490 491 timeout = 0; 492 do { 493 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 494 if (ret < 0) 495 return ret; 496 udelay(10 * 1000); 497 timeout++; 498 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 499 500 if (timeout >= 100) { 501 debug("timeout waiting for completion of Lite Reset\n"); 502 return -1; 503 } 504 505 write_buf = PM_CTL_PHY_RST_; 506 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf); 507 if (ret < 0) 508 return ret; 509 510 timeout = 0; 511 do { 512 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); 513 if (ret < 0) 514 return ret; 515 udelay(10 * 1000); 516 timeout++; 517 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 518 if (timeout >= 100) { 519 debug("timeout waiting for PHY Reset\n"); 520 return -1; 521 } 522 if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) 523 priv->have_hwaddr = 1; 524 if (!priv->have_hwaddr) { 525 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 526 return -1; 527 } 528 if (smsc95xx_write_hwaddr(eth) < 0) 529 return -1; 530 531 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 532 if (ret < 0) 533 return ret; 534 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 535 536 read_buf |= HW_CFG_BIR_; 537 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 538 if (ret < 0) 539 return ret; 540 541 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 542 if (ret < 0) 543 return ret; 544 debug("Read Value from HW_CFG after writing " 545 "HW_CFG_BIR_: 0x%08x\n", read_buf); 546 547 #ifdef TURBO_MODE 548 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 549 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 550 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 551 } else { 552 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 553 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 554 } 555 #else 556 burst_cap = 0; 557 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 558 #endif 559 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); 560 561 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); 562 if (ret < 0) 563 return ret; 564 565 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); 566 if (ret < 0) 567 return ret; 568 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 569 570 read_buf = DEFAULT_BULK_IN_DELAY; 571 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf); 572 if (ret < 0) 573 return ret; 574 575 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); 576 if (ret < 0) 577 return ret; 578 debug("Read Value from BULK_IN_DLY after writing: " 579 "0x%08x\n", read_buf); 580 581 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 582 if (ret < 0) 583 return ret; 584 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 585 586 #ifdef TURBO_MODE 587 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 588 #endif 589 read_buf &= ~HW_CFG_RXDOFF_; 590 591 #define NET_IP_ALIGN 0 592 read_buf |= NET_IP_ALIGN << 9; 593 594 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 595 if (ret < 0) 596 return ret; 597 598 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 599 if (ret < 0) 600 return ret; 601 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 602 603 write_buf = 0xFFFFFFFF; 604 ret = smsc95xx_write_reg(dev, INT_STS, write_buf); 605 if (ret < 0) 606 return ret; 607 608 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); 609 if (ret < 0) 610 return ret; 611 debug("ID_REV = 0x%08x\n", read_buf); 612 613 /* Init Tx */ 614 write_buf = 0; 615 ret = smsc95xx_write_reg(dev, FLOW, write_buf); 616 if (ret < 0) 617 return ret; 618 619 read_buf = AFC_CFG_DEFAULT; 620 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf); 621 if (ret < 0) 622 return ret; 623 624 ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr); 625 if (ret < 0) 626 return ret; 627 628 /* Init Rx. Set Vlan */ 629 write_buf = (u32)ETH_P_8021Q; 630 ret = smsc95xx_write_reg(dev, VLAN1, write_buf); 631 if (ret < 0) 632 return ret; 633 634 /* Disable checksum offload engines */ 635 ret = smsc95xx_set_csums(dev, 0, 0); 636 if (ret < 0) { 637 debug("Failed to set csum offload: %d\n", ret); 638 return ret; 639 } 640 smsc95xx_set_multicast(dev); 641 642 if (smsc95xx_phy_initialize(dev) < 0) 643 return -1; 644 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); 645 if (ret < 0) 646 return ret; 647 648 /* enable PHY interrupts */ 649 read_buf |= INT_EP_CTL_PHY_INT_; 650 651 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); 652 if (ret < 0) 653 return ret; 654 655 smsc95xx_start_tx_path(dev); 656 smsc95xx_start_rx_path(dev); 657 658 timeout = 0; 659 do { 660 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR) 661 & BMSR_LSTATUS; 662 if (!link_detected) { 663 if (timeout == 0) 664 printf("Waiting for Ethernet connection... "); 665 udelay(TIMEOUT_RESOLUTION * 1000); 666 timeout += TIMEOUT_RESOLUTION; 667 } 668 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 669 if (link_detected) { 670 if (timeout != 0) 671 printf("done.\n"); 672 } else { 673 printf("unable to connect.\n"); 674 return -1; 675 } 676 return 0; 677 } 678 679 static int smsc95xx_send(struct eth_device *eth, void* packet, int length) 680 { 681 struct ueth_data *dev = (struct ueth_data *)eth->priv; 682 int err; 683 int actual_len; 684 u32 tx_cmd_a; 685 u32 tx_cmd_b; 686 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 687 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); 688 689 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 690 if (length > PKTSIZE) 691 return -1; 692 693 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 694 tx_cmd_b = (u32)length; 695 cpu_to_le32s(&tx_cmd_a); 696 cpu_to_le32s(&tx_cmd_b); 697 698 /* prepend cmd_a and cmd_b */ 699 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 700 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 701 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 702 length); 703 err = usb_bulk_msg(dev->pusb_dev, 704 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 705 (void *)msg, 706 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 707 &actual_len, 708 USB_BULK_SEND_TIMEOUT); 709 debug("Tx: len = %u, actual = %u, err = %d\n", 710 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 711 actual_len, err); 712 return err; 713 } 714 715 static int smsc95xx_recv(struct eth_device *eth) 716 { 717 struct ueth_data *dev = (struct ueth_data *)eth->priv; 718 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); 719 unsigned char *buf_ptr; 720 int err; 721 int actual_len; 722 u32 packet_len; 723 int cur_buf_align; 724 725 debug("** %s()\n", __func__); 726 err = usb_bulk_msg(dev->pusb_dev, 727 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 728 (void *)recv_buf, 729 AX_RX_URB_SIZE, 730 &actual_len, 731 USB_BULK_RECV_TIMEOUT); 732 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 733 actual_len, err); 734 if (err != 0) { 735 debug("Rx: failed to receive\n"); 736 return -1; 737 } 738 if (actual_len > AX_RX_URB_SIZE) { 739 debug("Rx: received too many bytes %d\n", actual_len); 740 return -1; 741 } 742 743 buf_ptr = recv_buf; 744 while (actual_len > 0) { 745 /* 746 * 1st 4 bytes contain the length of the actual data plus error 747 * info. Extract data length. 748 */ 749 if (actual_len < sizeof(packet_len)) { 750 debug("Rx: incomplete packet length\n"); 751 return -1; 752 } 753 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 754 le32_to_cpus(&packet_len); 755 if (packet_len & RX_STS_ES_) { 756 debug("Rx: Error header=%#x", packet_len); 757 return -1; 758 } 759 packet_len = ((packet_len & RX_STS_FL_) >> 16); 760 761 if (packet_len > actual_len - sizeof(packet_len)) { 762 debug("Rx: too large packet: %d\n", packet_len); 763 return -1; 764 } 765 766 /* Notify net stack */ 767 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4); 768 769 /* Adjust for next iteration */ 770 actual_len -= sizeof(packet_len) + packet_len; 771 buf_ptr += sizeof(packet_len) + packet_len; 772 cur_buf_align = (int)buf_ptr - (int)recv_buf; 773 774 if (cur_buf_align & 0x03) { 775 int align = 4 - (cur_buf_align & 0x03); 776 777 actual_len -= align; 778 buf_ptr += align; 779 } 780 } 781 return err; 782 } 783 784 static void smsc95xx_halt(struct eth_device *eth) 785 { 786 debug("** %s()\n", __func__); 787 } 788 789 /* 790 * SMSC probing functions 791 */ 792 void smsc95xx_eth_before_probe(void) 793 { 794 curr_eth_dev = 0; 795 } 796 797 struct smsc95xx_dongle { 798 unsigned short vendor; 799 unsigned short product; 800 }; 801 802 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 803 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 804 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 805 { 0x0000, 0x0000 } /* END - Do not remove */ 806 }; 807 808 /* Probe to see if a new device is actually an SMSC device */ 809 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 810 struct ueth_data *ss) 811 { 812 struct usb_interface *iface; 813 struct usb_interface_descriptor *iface_desc; 814 int i; 815 816 /* let's examine the device now */ 817 iface = &dev->config.if_desc[ifnum]; 818 iface_desc = &dev->config.if_desc[ifnum].desc; 819 820 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 821 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 822 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 823 /* Found a supported dongle */ 824 break; 825 } 826 if (smsc95xx_dongles[i].vendor == 0) 827 return 0; 828 829 /* At this point, we know we've got a live one */ 830 debug("\n\nUSB Ethernet device detected\n"); 831 memset(ss, '\0', sizeof(struct ueth_data)); 832 833 /* Initialize the ueth_data structure with some useful info */ 834 ss->ifnum = ifnum; 835 ss->pusb_dev = dev; 836 ss->subclass = iface_desc->bInterfaceSubClass; 837 ss->protocol = iface_desc->bInterfaceProtocol; 838 839 /* 840 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 841 * We will ignore any others. 842 */ 843 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 844 /* is it an BULK endpoint? */ 845 if ((iface->ep_desc[i].bmAttributes & 846 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 847 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 848 ss->ep_in = 849 iface->ep_desc[i].bEndpointAddress & 850 USB_ENDPOINT_NUMBER_MASK; 851 else 852 ss->ep_out = 853 iface->ep_desc[i].bEndpointAddress & 854 USB_ENDPOINT_NUMBER_MASK; 855 } 856 857 /* is it an interrupt endpoint? */ 858 if ((iface->ep_desc[i].bmAttributes & 859 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 860 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 861 USB_ENDPOINT_NUMBER_MASK; 862 ss->irqinterval = iface->ep_desc[i].bInterval; 863 } 864 } 865 debug("Endpoints In %d Out %d Int %d\n", 866 ss->ep_in, ss->ep_out, ss->ep_int); 867 868 /* Do some basic sanity checks, and bail if we find a problem */ 869 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 870 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 871 debug("Problems with device\n"); 872 return 0; 873 } 874 dev->privptr = (void *)ss; 875 876 /* alloc driver private */ 877 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); 878 if (!ss->dev_priv) 879 return 0; 880 881 return 1; 882 } 883 884 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 885 struct eth_device *eth) 886 { 887 debug("** %s()\n", __func__); 888 if (!eth) { 889 debug("%s: missing parameter.\n", __func__); 890 return 0; 891 } 892 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 893 eth->init = smsc95xx_init; 894 eth->send = smsc95xx_send; 895 eth->recv = smsc95xx_recv; 896 eth->halt = smsc95xx_halt; 897 eth->write_hwaddr = smsc95xx_write_hwaddr; 898 eth->priv = ss; 899 return 1; 900 } 901