1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (C) 2009 NVIDIA, Corporation 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <asm/unaligned.h> 24 #include <common.h> 25 #include <usb.h> 26 #include <linux/mii.h> 27 #include "usb_ether.h" 28 29 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 30 31 /* Tx command words */ 32 #define TX_CMD_A_FIRST_SEG_ 0x00002000 33 #define TX_CMD_A_LAST_SEG_ 0x00001000 34 35 /* Rx status word */ 36 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 37 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 38 39 /* SCSRs */ 40 #define ID_REV 0x00 41 42 #define INT_STS 0x08 43 44 #define TX_CFG 0x10 45 #define TX_CFG_ON_ 0x00000004 46 47 #define HW_CFG 0x14 48 #define HW_CFG_BIR_ 0x00001000 49 #define HW_CFG_RXDOFF_ 0x00000600 50 #define HW_CFG_MEF_ 0x00000020 51 #define HW_CFG_BCE_ 0x00000002 52 #define HW_CFG_LRST_ 0x00000008 53 54 #define PM_CTRL 0x20 55 #define PM_CTL_PHY_RST_ 0x00000010 56 57 #define AFC_CFG 0x2C 58 59 /* 60 * Hi watermark = 15.5Kb (~10 mtu pkts) 61 * low watermark = 3k (~2 mtu pkts) 62 * backpressure duration = ~ 350us 63 * Apply FC on any frame. 64 */ 65 #define AFC_CFG_DEFAULT 0x00F830A1 66 67 #define E2P_CMD 0x30 68 #define E2P_CMD_BUSY_ 0x80000000 69 #define E2P_CMD_READ_ 0x00000000 70 #define E2P_CMD_TIMEOUT_ 0x00000400 71 #define E2P_CMD_LOADED_ 0x00000200 72 #define E2P_CMD_ADDR_ 0x000001FF 73 74 #define E2P_DATA 0x34 75 76 #define BURST_CAP 0x38 77 78 #define INT_EP_CTL 0x68 79 #define INT_EP_CTL_PHY_INT_ 0x00008000 80 81 #define BULK_IN_DLY 0x6C 82 83 /* MAC CSRs */ 84 #define MAC_CR 0x100 85 #define MAC_CR_MCPAS_ 0x00080000 86 #define MAC_CR_PRMS_ 0x00040000 87 #define MAC_CR_HPFILT_ 0x00002000 88 #define MAC_CR_TXEN_ 0x00000008 89 #define MAC_CR_RXEN_ 0x00000004 90 91 #define ADDRH 0x104 92 93 #define ADDRL 0x108 94 95 #define MII_ADDR 0x114 96 #define MII_WRITE_ 0x02 97 #define MII_BUSY_ 0x01 98 #define MII_READ_ 0x00 /* ~of MII Write bit */ 99 100 #define MII_DATA 0x118 101 102 #define FLOW 0x11C 103 104 #define VLAN1 0x120 105 106 #define COE_CR 0x130 107 #define Tx_COE_EN_ 0x00010000 108 #define Rx_COE_EN_ 0x00000001 109 110 /* Vendor-specific PHY Definitions */ 111 #define PHY_INT_SRC 29 112 113 #define PHY_INT_MASK 30 114 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 115 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 116 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 117 PHY_INT_MASK_LINK_DOWN_) 118 119 /* USB Vendor Requests */ 120 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 121 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 122 123 /* Some extra defines */ 124 #define HS_USB_PKT_SIZE 512 125 #define FS_USB_PKT_SIZE 64 126 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 127 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 128 #define DEFAULT_BULK_IN_DELAY 0x00002000 129 #define MAX_SINGLE_PACKET_SIZE 2048 130 #define EEPROM_MAC_OFFSET 0x01 131 #define SMSC95XX_INTERNAL_PHY_ID 1 132 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 133 134 /* local defines */ 135 #define SMSC95XX_BASE_NAME "sms" 136 #define USB_CTRL_SET_TIMEOUT 5000 137 #define USB_CTRL_GET_TIMEOUT 5000 138 #define USB_BULK_SEND_TIMEOUT 5000 139 #define USB_BULK_RECV_TIMEOUT 5000 140 141 #define AX_RX_URB_SIZE 2048 142 #define PHY_CONNECT_TIMEOUT 5000 143 144 #define TURBO_MODE 145 146 /* local vars */ 147 static int curr_eth_dev; /* index for name of next device detected */ 148 149 150 /* 151 * Smsc95xx infrastructure commands 152 */ 153 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) 154 { 155 int len; 156 157 cpu_to_le32s(&data); 158 159 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0), 160 USB_VENDOR_REQUEST_WRITE_REGISTER, 161 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 162 00, index, &data, sizeof(data), USB_CTRL_SET_TIMEOUT); 163 if (len != sizeof(data)) { 164 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 165 index, data, len); 166 return -1; 167 } 168 return 0; 169 } 170 171 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data) 172 { 173 int len; 174 175 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0), 176 USB_VENDOR_REQUEST_READ_REGISTER, 177 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 178 00, index, data, sizeof(data), USB_CTRL_GET_TIMEOUT); 179 if (len != sizeof(data)) { 180 debug("smsc95xx_read_reg failed: index=%d, len=%d", 181 index, len); 182 return -1; 183 } 184 185 le32_to_cpus(data); 186 return 0; 187 } 188 189 /* Loop until the read is completed with timeout */ 190 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev) 191 { 192 unsigned long start_time = get_timer(0); 193 u32 val; 194 195 do { 196 smsc95xx_read_reg(dev, MII_ADDR, &val); 197 if (!(val & MII_BUSY_)) 198 return 0; 199 } while (get_timer(start_time) < 1 * 1000 * 1000); 200 201 return -1; 202 } 203 204 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx) 205 { 206 u32 val, addr; 207 208 /* confirm MII not busy */ 209 if (smsc95xx_phy_wait_not_busy(dev)) { 210 debug("MII is busy in smsc95xx_mdio_read\n"); 211 return -1; 212 } 213 214 /* set the address, index & direction (read from PHY) */ 215 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 216 smsc95xx_write_reg(dev, MII_ADDR, addr); 217 218 if (smsc95xx_phy_wait_not_busy(dev)) { 219 debug("Timed out reading MII reg %02X\n", idx); 220 return -1; 221 } 222 223 smsc95xx_read_reg(dev, MII_DATA, &val); 224 225 return (u16)(val & 0xFFFF); 226 } 227 228 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx, 229 int regval) 230 { 231 u32 val, addr; 232 233 /* confirm MII not busy */ 234 if (smsc95xx_phy_wait_not_busy(dev)) { 235 debug("MII is busy in smsc95xx_mdio_write\n"); 236 return; 237 } 238 239 val = regval; 240 smsc95xx_write_reg(dev, MII_DATA, val); 241 242 /* set the address, index & direction (write to PHY) */ 243 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 244 smsc95xx_write_reg(dev, MII_ADDR, addr); 245 246 if (smsc95xx_phy_wait_not_busy(dev)) 247 debug("Timed out writing MII reg %02X\n", idx); 248 } 249 250 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev) 251 { 252 unsigned long start_time = get_timer(0); 253 u32 val; 254 255 do { 256 smsc95xx_read_reg(dev, E2P_CMD, &val); 257 if (!(val & E2P_CMD_LOADED_)) { 258 debug("No EEPROM present\n"); 259 return -1; 260 } 261 if (!(val & E2P_CMD_BUSY_)) 262 return 0; 263 udelay(40); 264 } while (get_timer(start_time) < 1 * 1000 * 1000); 265 266 debug("EEPROM is busy\n"); 267 return -1; 268 } 269 270 static int smsc95xx_wait_eeprom(struct ueth_data *dev) 271 { 272 unsigned long start_time = get_timer(0); 273 u32 val; 274 275 do { 276 smsc95xx_read_reg(dev, E2P_CMD, &val); 277 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 278 break; 279 udelay(40); 280 } while (get_timer(start_time) < 1 * 1000 * 1000); 281 282 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 283 debug("EEPROM read operation timeout\n"); 284 return -1; 285 } 286 return 0; 287 } 288 289 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length, 290 u8 *data) 291 { 292 u32 val; 293 int i, ret; 294 295 ret = smsc95xx_eeprom_confirm_not_busy(dev); 296 if (ret) 297 return ret; 298 299 for (i = 0; i < length; i++) { 300 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 301 smsc95xx_write_reg(dev, E2P_CMD, val); 302 303 ret = smsc95xx_wait_eeprom(dev); 304 if (ret < 0) 305 return ret; 306 307 smsc95xx_read_reg(dev, E2P_DATA, &val); 308 data[i] = val & 0xFF; 309 offset++; 310 } 311 return 0; 312 } 313 314 /* 315 * mii_nway_restart - restart NWay (autonegotiation) for this interface 316 * 317 * Returns 0 on success, negative on error. 318 */ 319 static int mii_nway_restart(struct ueth_data *dev) 320 { 321 int bmcr; 322 int r = -1; 323 324 /* if autoneg is off, it's an error */ 325 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR); 326 327 if (bmcr & BMCR_ANENABLE) { 328 bmcr |= BMCR_ANRESTART; 329 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 330 r = 0; 331 } 332 return r; 333 } 334 335 static int smsc95xx_phy_initialize(struct ueth_data *dev) 336 { 337 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 338 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 339 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 340 ADVERTISE_PAUSE_ASYM); 341 342 /* read to clear */ 343 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC); 344 345 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK, 346 PHY_INT_MASK_DEFAULT_); 347 mii_nway_restart(dev); 348 349 debug("phy initialised succesfully\n"); 350 return 0; 351 } 352 353 static int smsc95xx_init_mac_address(struct eth_device *eth, 354 struct ueth_data *dev) 355 { 356 /* try reading mac address from EEPROM */ 357 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 358 eth->enetaddr) == 0) { 359 if (is_valid_ether_addr(eth->enetaddr)) { 360 /* eeprom values are valid so use them */ 361 debug("MAC address read from EEPROM\n"); 362 return 0; 363 } 364 } 365 366 /* 367 * No eeprom, or eeprom values are invalid. Generating a random MAC 368 * address is not safe. Just return an error. 369 */ 370 return -1; 371 } 372 373 static int smsc95xx_write_hwaddr(struct eth_device *eth) 374 { 375 struct ueth_data *dev = (struct ueth_data *)eth->priv; 376 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]); 377 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]); 378 int ret; 379 380 /* set hardware address */ 381 debug("** %s()\n", __func__); 382 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); 383 if (ret < 0) 384 return ret; 385 386 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); 387 if (ret < 0) 388 return ret; 389 390 debug("MAC %pM\n", eth->enetaddr); 391 dev->have_hwaddr = 1; 392 return 0; 393 } 394 395 /* Enable or disable Tx & Rx checksum offload engines */ 396 static int smsc95xx_set_csums(struct ueth_data *dev, 397 int use_tx_csum, int use_rx_csum) 398 { 399 u32 read_buf; 400 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); 401 if (ret < 0) 402 return ret; 403 404 if (use_tx_csum) 405 read_buf |= Tx_COE_EN_; 406 else 407 read_buf &= ~Tx_COE_EN_; 408 409 if (use_rx_csum) 410 read_buf |= Rx_COE_EN_; 411 else 412 read_buf &= ~Rx_COE_EN_; 413 414 ret = smsc95xx_write_reg(dev, COE_CR, read_buf); 415 if (ret < 0) 416 return ret; 417 418 debug("COE_CR = 0x%08x\n", read_buf); 419 return 0; 420 } 421 422 static void smsc95xx_set_multicast(struct ueth_data *dev) 423 { 424 /* No multicast in u-boot */ 425 dev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 426 } 427 428 /* starts the TX path */ 429 static void smsc95xx_start_tx_path(struct ueth_data *dev) 430 { 431 u32 reg_val; 432 433 /* Enable Tx at MAC */ 434 dev->mac_cr |= MAC_CR_TXEN_; 435 436 smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr); 437 438 /* Enable Tx at SCSRs */ 439 reg_val = TX_CFG_ON_; 440 smsc95xx_write_reg(dev, TX_CFG, reg_val); 441 } 442 443 /* Starts the Receive path */ 444 static void smsc95xx_start_rx_path(struct ueth_data *dev) 445 { 446 dev->mac_cr |= MAC_CR_RXEN_; 447 smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr); 448 } 449 450 /* 451 * Smsc95xx callbacks 452 */ 453 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 454 { 455 int ret; 456 u32 write_buf; 457 u32 read_buf; 458 u32 burst_cap; 459 int timeout; 460 struct ueth_data *dev = (struct ueth_data *)eth->priv; 461 #define TIMEOUT_RESOLUTION 50 /* ms */ 462 int link_detected; 463 464 debug("** %s()\n", __func__); 465 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 466 467 write_buf = HW_CFG_LRST_; 468 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf); 469 if (ret < 0) 470 return ret; 471 472 timeout = 0; 473 do { 474 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 475 if (ret < 0) 476 return ret; 477 udelay(10 * 1000); 478 timeout++; 479 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 480 481 if (timeout >= 100) { 482 debug("timeout waiting for completion of Lite Reset\n"); 483 return -1; 484 } 485 486 write_buf = PM_CTL_PHY_RST_; 487 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf); 488 if (ret < 0) 489 return ret; 490 491 timeout = 0; 492 do { 493 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); 494 if (ret < 0) 495 return ret; 496 udelay(10 * 1000); 497 timeout++; 498 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 499 if (timeout >= 100) { 500 debug("timeout waiting for PHY Reset\n"); 501 return -1; 502 } 503 if (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) 504 dev->have_hwaddr = 1; 505 if (!dev->have_hwaddr) { 506 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 507 return -1; 508 } 509 if (smsc95xx_write_hwaddr(eth) < 0) 510 return -1; 511 512 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 513 if (ret < 0) 514 return ret; 515 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 516 517 read_buf |= HW_CFG_BIR_; 518 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 519 if (ret < 0) 520 return ret; 521 522 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 523 if (ret < 0) 524 return ret; 525 debug("Read Value from HW_CFG after writing " 526 "HW_CFG_BIR_: 0x%08x\n", read_buf); 527 528 #ifdef TURBO_MODE 529 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 530 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 531 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 532 } else { 533 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 534 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 535 } 536 #else 537 burst_cap = 0; 538 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 539 #endif 540 debug("rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); 541 542 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); 543 if (ret < 0) 544 return ret; 545 546 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); 547 if (ret < 0) 548 return ret; 549 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 550 551 read_buf = DEFAULT_BULK_IN_DELAY; 552 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf); 553 if (ret < 0) 554 return ret; 555 556 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); 557 if (ret < 0) 558 return ret; 559 debug("Read Value from BULK_IN_DLY after writing: " 560 "0x%08x\n", read_buf); 561 562 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 563 if (ret < 0) 564 return ret; 565 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 566 567 #ifdef TURBO_MODE 568 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 569 #endif 570 read_buf &= ~HW_CFG_RXDOFF_; 571 572 #define NET_IP_ALIGN 0 573 read_buf |= NET_IP_ALIGN << 9; 574 575 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 576 if (ret < 0) 577 return ret; 578 579 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 580 if (ret < 0) 581 return ret; 582 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 583 584 write_buf = 0xFFFFFFFF; 585 ret = smsc95xx_write_reg(dev, INT_STS, write_buf); 586 if (ret < 0) 587 return ret; 588 589 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); 590 if (ret < 0) 591 return ret; 592 debug("ID_REV = 0x%08x\n", read_buf); 593 594 /* Init Tx */ 595 write_buf = 0; 596 ret = smsc95xx_write_reg(dev, FLOW, write_buf); 597 if (ret < 0) 598 return ret; 599 600 read_buf = AFC_CFG_DEFAULT; 601 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf); 602 if (ret < 0) 603 return ret; 604 605 ret = smsc95xx_read_reg(dev, MAC_CR, &dev->mac_cr); 606 if (ret < 0) 607 return ret; 608 609 /* Init Rx. Set Vlan */ 610 write_buf = (u32)ETH_P_8021Q; 611 ret = smsc95xx_write_reg(dev, VLAN1, write_buf); 612 if (ret < 0) 613 return ret; 614 615 /* Disable checksum offload engines */ 616 ret = smsc95xx_set_csums(dev, 0, 0); 617 if (ret < 0) { 618 debug("Failed to set csum offload: %d\n", ret); 619 return ret; 620 } 621 smsc95xx_set_multicast(dev); 622 623 if (smsc95xx_phy_initialize(dev) < 0) 624 return -1; 625 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); 626 if (ret < 0) 627 return ret; 628 629 /* enable PHY interrupts */ 630 read_buf |= INT_EP_CTL_PHY_INT_; 631 632 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); 633 if (ret < 0) 634 return ret; 635 636 smsc95xx_start_tx_path(dev); 637 smsc95xx_start_rx_path(dev); 638 639 timeout = 0; 640 do { 641 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR) 642 & BMSR_LSTATUS; 643 if (!link_detected) { 644 if (timeout == 0) 645 printf("Waiting for Ethernet connection... "); 646 udelay(TIMEOUT_RESOLUTION * 1000); 647 timeout += TIMEOUT_RESOLUTION; 648 } 649 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 650 if (link_detected) { 651 if (timeout != 0) 652 printf("done.\n"); 653 } else { 654 printf("unable to connect.\n"); 655 return -1; 656 } 657 return 0; 658 } 659 660 static int smsc95xx_send(struct eth_device *eth, void* packet, int length) 661 { 662 struct ueth_data *dev = (struct ueth_data *)eth->priv; 663 int err; 664 int actual_len; 665 u32 tx_cmd_a; 666 u32 tx_cmd_b; 667 unsigned char msg[PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)]; 668 669 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 670 if (length > PKTSIZE) 671 return -1; 672 673 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 674 tx_cmd_b = (u32)length; 675 cpu_to_le32s(&tx_cmd_a); 676 cpu_to_le32s(&tx_cmd_b); 677 678 /* prepend cmd_a and cmd_b */ 679 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 680 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 681 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 682 length); 683 err = usb_bulk_msg(dev->pusb_dev, 684 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 685 (void *)msg, 686 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 687 &actual_len, 688 USB_BULK_SEND_TIMEOUT); 689 debug("Tx: len = %u, actual = %u, err = %d\n", 690 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 691 actual_len, err); 692 return err; 693 } 694 695 static int smsc95xx_recv(struct eth_device *eth) 696 { 697 struct ueth_data *dev = (struct ueth_data *)eth->priv; 698 static unsigned char recv_buf[AX_RX_URB_SIZE]; 699 unsigned char *buf_ptr; 700 int err; 701 int actual_len; 702 u32 packet_len; 703 int cur_buf_align; 704 705 debug("** %s()\n", __func__); 706 err = usb_bulk_msg(dev->pusb_dev, 707 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 708 (void *)recv_buf, 709 AX_RX_URB_SIZE, 710 &actual_len, 711 USB_BULK_RECV_TIMEOUT); 712 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 713 actual_len, err); 714 if (err != 0) { 715 debug("Rx: failed to receive\n"); 716 return -1; 717 } 718 if (actual_len > AX_RX_URB_SIZE) { 719 debug("Rx: received too many bytes %d\n", actual_len); 720 return -1; 721 } 722 723 buf_ptr = recv_buf; 724 while (actual_len > 0) { 725 /* 726 * 1st 4 bytes contain the length of the actual data plus error 727 * info. Extract data length. 728 */ 729 if (actual_len < sizeof(packet_len)) { 730 debug("Rx: incomplete packet length\n"); 731 return -1; 732 } 733 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 734 le32_to_cpus(&packet_len); 735 if (packet_len & RX_STS_ES_) { 736 debug("Rx: Error header=%#x", packet_len); 737 return -1; 738 } 739 packet_len = ((packet_len & RX_STS_FL_) >> 16); 740 741 if (packet_len > actual_len - sizeof(packet_len)) { 742 debug("Rx: too large packet: %d\n", packet_len); 743 return -1; 744 } 745 746 /* Notify net stack */ 747 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4); 748 749 /* Adjust for next iteration */ 750 actual_len -= sizeof(packet_len) + packet_len; 751 buf_ptr += sizeof(packet_len) + packet_len; 752 cur_buf_align = (int)buf_ptr - (int)recv_buf; 753 754 if (cur_buf_align & 0x03) { 755 int align = 4 - (cur_buf_align & 0x03); 756 757 actual_len -= align; 758 buf_ptr += align; 759 } 760 } 761 return err; 762 } 763 764 static void smsc95xx_halt(struct eth_device *eth) 765 { 766 debug("** %s()\n", __func__); 767 } 768 769 /* 770 * SMSC probing functions 771 */ 772 void smsc95xx_eth_before_probe(void) 773 { 774 curr_eth_dev = 0; 775 } 776 777 struct smsc95xx_dongle { 778 unsigned short vendor; 779 unsigned short product; 780 }; 781 782 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 783 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 784 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 785 { 0x0000, 0x0000 } /* END - Do not remove */ 786 }; 787 788 /* Probe to see if a new device is actually an SMSC device */ 789 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 790 struct ueth_data *ss) 791 { 792 struct usb_interface *iface; 793 struct usb_interface_descriptor *iface_desc; 794 int i; 795 796 /* let's examine the device now */ 797 iface = &dev->config.if_desc[ifnum]; 798 iface_desc = &dev->config.if_desc[ifnum].desc; 799 800 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 801 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 802 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 803 /* Found a supported dongle */ 804 break; 805 } 806 if (smsc95xx_dongles[i].vendor == 0) 807 return 0; 808 809 /* At this point, we know we've got a live one */ 810 debug("\n\nUSB Ethernet device detected\n"); 811 memset(ss, '\0', sizeof(struct ueth_data)); 812 813 /* Initialize the ueth_data structure with some useful info */ 814 ss->ifnum = ifnum; 815 ss->pusb_dev = dev; 816 ss->subclass = iface_desc->bInterfaceSubClass; 817 ss->protocol = iface_desc->bInterfaceProtocol; 818 819 /* 820 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 821 * We will ignore any others. 822 */ 823 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 824 /* is it an BULK endpoint? */ 825 if ((iface->ep_desc[i].bmAttributes & 826 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 827 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 828 ss->ep_in = 829 iface->ep_desc[i].bEndpointAddress & 830 USB_ENDPOINT_NUMBER_MASK; 831 else 832 ss->ep_out = 833 iface->ep_desc[i].bEndpointAddress & 834 USB_ENDPOINT_NUMBER_MASK; 835 } 836 837 /* is it an interrupt endpoint? */ 838 if ((iface->ep_desc[i].bmAttributes & 839 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 840 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 841 USB_ENDPOINT_NUMBER_MASK; 842 ss->irqinterval = iface->ep_desc[i].bInterval; 843 } 844 } 845 debug("Endpoints In %d Out %d Int %d\n", 846 ss->ep_in, ss->ep_out, ss->ep_int); 847 848 /* Do some basic sanity checks, and bail if we find a problem */ 849 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 850 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 851 debug("Problems with device\n"); 852 return 0; 853 } 854 dev->privptr = (void *)ss; 855 return 1; 856 } 857 858 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 859 struct eth_device *eth) 860 { 861 debug("** %s()\n", __func__); 862 if (!eth) { 863 debug("%s: missing parameter.\n", __func__); 864 return 0; 865 } 866 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 867 eth->init = smsc95xx_init; 868 eth->send = smsc95xx_send; 869 eth->recv = smsc95xx_recv; 870 eth->halt = smsc95xx_halt; 871 eth->write_hwaddr = smsc95xx_write_hwaddr; 872 eth->priv = ss; 873 return 1; 874 } 875