1 /* 2 * Copyright (c) 2015 Google, Inc 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * Copyright (C) 2009 NVIDIA, Corporation 5 * Copyright (C) 2007-2008 SMSC (Steve Glendinning) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <usb.h> 16 #include <asm/unaligned.h> 17 #include <linux/mii.h> 18 #include "usb_ether.h" 19 20 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 21 22 /* LED defines */ 23 #define LED_GPIO_CFG (0x24) 24 #define LED_GPIO_CFG_SPD_LED (0x01000000) 25 #define LED_GPIO_CFG_LNK_LED (0x00100000) 26 #define LED_GPIO_CFG_FDX_LED (0x00010000) 27 28 /* Tx command words */ 29 #define TX_CMD_A_FIRST_SEG_ 0x00002000 30 #define TX_CMD_A_LAST_SEG_ 0x00001000 31 32 /* Rx status word */ 33 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 34 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 35 36 /* SCSRs */ 37 #define ID_REV 0x00 38 39 #define INT_STS 0x08 40 41 #define TX_CFG 0x10 42 #define TX_CFG_ON_ 0x00000004 43 44 #define HW_CFG 0x14 45 #define HW_CFG_BIR_ 0x00001000 46 #define HW_CFG_RXDOFF_ 0x00000600 47 #define HW_CFG_MEF_ 0x00000020 48 #define HW_CFG_BCE_ 0x00000002 49 #define HW_CFG_LRST_ 0x00000008 50 51 #define PM_CTRL 0x20 52 #define PM_CTL_PHY_RST_ 0x00000010 53 54 #define AFC_CFG 0x2C 55 56 /* 57 * Hi watermark = 15.5Kb (~10 mtu pkts) 58 * low watermark = 3k (~2 mtu pkts) 59 * backpressure duration = ~ 350us 60 * Apply FC on any frame. 61 */ 62 #define AFC_CFG_DEFAULT 0x00F830A1 63 64 #define E2P_CMD 0x30 65 #define E2P_CMD_BUSY_ 0x80000000 66 #define E2P_CMD_READ_ 0x00000000 67 #define E2P_CMD_TIMEOUT_ 0x00000400 68 #define E2P_CMD_LOADED_ 0x00000200 69 #define E2P_CMD_ADDR_ 0x000001FF 70 71 #define E2P_DATA 0x34 72 73 #define BURST_CAP 0x38 74 75 #define INT_EP_CTL 0x68 76 #define INT_EP_CTL_PHY_INT_ 0x00008000 77 78 #define BULK_IN_DLY 0x6C 79 80 /* MAC CSRs */ 81 #define MAC_CR 0x100 82 #define MAC_CR_MCPAS_ 0x00080000 83 #define MAC_CR_PRMS_ 0x00040000 84 #define MAC_CR_HPFILT_ 0x00002000 85 #define MAC_CR_TXEN_ 0x00000008 86 #define MAC_CR_RXEN_ 0x00000004 87 88 #define ADDRH 0x104 89 90 #define ADDRL 0x108 91 92 #define MII_ADDR 0x114 93 #define MII_WRITE_ 0x02 94 #define MII_BUSY_ 0x01 95 #define MII_READ_ 0x00 /* ~of MII Write bit */ 96 97 #define MII_DATA 0x118 98 99 #define FLOW 0x11C 100 101 #define VLAN1 0x120 102 103 #define COE_CR 0x130 104 #define Tx_COE_EN_ 0x00010000 105 #define Rx_COE_EN_ 0x00000001 106 107 /* Vendor-specific PHY Definitions */ 108 #define PHY_INT_SRC 29 109 110 #define PHY_INT_MASK 30 111 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 112 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 113 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 114 PHY_INT_MASK_LINK_DOWN_) 115 116 /* USB Vendor Requests */ 117 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 118 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 119 120 /* Some extra defines */ 121 #define HS_USB_PKT_SIZE 512 122 #define FS_USB_PKT_SIZE 64 123 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 124 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 125 #define DEFAULT_BULK_IN_DELAY 0x00002000 126 #define MAX_SINGLE_PACKET_SIZE 2048 127 #define EEPROM_MAC_OFFSET 0x01 128 #define SMSC95XX_INTERNAL_PHY_ID 1 129 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 130 131 /* local defines */ 132 #define SMSC95XX_BASE_NAME "sms" 133 #define USB_CTRL_SET_TIMEOUT 5000 134 #define USB_CTRL_GET_TIMEOUT 5000 135 #define USB_BULK_SEND_TIMEOUT 5000 136 #define USB_BULK_RECV_TIMEOUT 5000 137 138 #define RX_URB_SIZE 2048 139 #define PHY_CONNECT_TIMEOUT 5000 140 141 #define TURBO_MODE 142 143 #ifndef CONFIG_DM_ETH 144 /* local vars */ 145 static int curr_eth_dev; /* index for name of next device detected */ 146 #endif 147 148 /* driver private */ 149 struct smsc95xx_private { 150 #ifdef CONFIG_DM_ETH 151 struct ueth_data ueth; 152 #endif 153 size_t rx_urb_size; /* maximum USB URB size */ 154 u32 mac_cr; /* MAC control register value */ 155 int have_hwaddr; /* 1 if we have a hardware MAC address */ 156 }; 157 158 /* 159 * Smsc95xx infrastructure commands 160 */ 161 static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data) 162 { 163 int len; 164 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 165 166 cpu_to_le32s(&data); 167 tmpbuf[0] = data; 168 169 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 170 USB_VENDOR_REQUEST_WRITE_REGISTER, 171 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 172 0, index, tmpbuf, sizeof(data), 173 USB_CTRL_SET_TIMEOUT); 174 if (len != sizeof(data)) { 175 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 176 index, data, len); 177 return -EIO; 178 } 179 return 0; 180 } 181 182 static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data) 183 { 184 int len; 185 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 186 187 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 188 USB_VENDOR_REQUEST_READ_REGISTER, 189 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 190 0, index, tmpbuf, sizeof(data), 191 USB_CTRL_GET_TIMEOUT); 192 *data = tmpbuf[0]; 193 if (len != sizeof(data)) { 194 debug("smsc95xx_read_reg failed: index=%d, len=%d", 195 index, len); 196 return -EIO; 197 } 198 199 le32_to_cpus(data); 200 return 0; 201 } 202 203 /* Loop until the read is completed with timeout */ 204 static int smsc95xx_phy_wait_not_busy(struct usb_device *udev) 205 { 206 unsigned long start_time = get_timer(0); 207 u32 val; 208 209 do { 210 smsc95xx_read_reg(udev, MII_ADDR, &val); 211 if (!(val & MII_BUSY_)) 212 return 0; 213 } while (get_timer(start_time) < 1000); 214 215 return -ETIMEDOUT; 216 } 217 218 static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx) 219 { 220 u32 val, addr; 221 222 /* confirm MII not busy */ 223 if (smsc95xx_phy_wait_not_busy(udev)) { 224 debug("MII is busy in smsc95xx_mdio_read\n"); 225 return -ETIMEDOUT; 226 } 227 228 /* set the address, index & direction (read from PHY) */ 229 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 230 smsc95xx_write_reg(udev, MII_ADDR, addr); 231 232 if (smsc95xx_phy_wait_not_busy(udev)) { 233 debug("Timed out reading MII reg %02X\n", idx); 234 return -ETIMEDOUT; 235 } 236 237 smsc95xx_read_reg(udev, MII_DATA, &val); 238 239 return (u16)(val & 0xFFFF); 240 } 241 242 static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx, 243 int regval) 244 { 245 u32 val, addr; 246 247 /* confirm MII not busy */ 248 if (smsc95xx_phy_wait_not_busy(udev)) { 249 debug("MII is busy in smsc95xx_mdio_write\n"); 250 return; 251 } 252 253 val = regval; 254 smsc95xx_write_reg(udev, MII_DATA, val); 255 256 /* set the address, index & direction (write to PHY) */ 257 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 258 smsc95xx_write_reg(udev, MII_ADDR, addr); 259 260 if (smsc95xx_phy_wait_not_busy(udev)) 261 debug("Timed out writing MII reg %02X\n", idx); 262 } 263 264 static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev) 265 { 266 unsigned long start_time = get_timer(0); 267 u32 val; 268 269 do { 270 smsc95xx_read_reg(udev, E2P_CMD, &val); 271 if (!(val & E2P_CMD_BUSY_)) 272 return 0; 273 udelay(40); 274 } while (get_timer(start_time) < 1 * 1000 * 1000); 275 276 debug("EEPROM is busy\n"); 277 return -ETIMEDOUT; 278 } 279 280 static int smsc95xx_wait_eeprom(struct usb_device *udev) 281 { 282 unsigned long start_time = get_timer(0); 283 u32 val; 284 285 do { 286 smsc95xx_read_reg(udev, E2P_CMD, &val); 287 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 288 break; 289 udelay(40); 290 } while (get_timer(start_time) < 1 * 1000 * 1000); 291 292 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 293 debug("EEPROM read operation timeout\n"); 294 return -ETIMEDOUT; 295 } 296 return 0; 297 } 298 299 static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length, 300 u8 *data) 301 { 302 u32 val; 303 int i, ret; 304 305 ret = smsc95xx_eeprom_confirm_not_busy(udev); 306 if (ret) 307 return ret; 308 309 for (i = 0; i < length; i++) { 310 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 311 smsc95xx_write_reg(udev, E2P_CMD, val); 312 313 ret = smsc95xx_wait_eeprom(udev); 314 if (ret < 0) 315 return ret; 316 317 smsc95xx_read_reg(udev, E2P_DATA, &val); 318 data[i] = val & 0xFF; 319 offset++; 320 } 321 return 0; 322 } 323 324 /* 325 * mii_nway_restart - restart NWay (autonegotiation) for this interface 326 * 327 * Returns 0 on success, negative on error. 328 */ 329 static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev) 330 { 331 int bmcr; 332 int r = -1; 333 334 /* if autoneg is off, it's an error */ 335 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR); 336 337 if (bmcr & BMCR_ANENABLE) { 338 bmcr |= BMCR_ANRESTART; 339 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr); 340 r = 0; 341 } 342 return r; 343 } 344 345 static int smsc95xx_phy_initialize(struct usb_device *udev, 346 struct ueth_data *dev) 347 { 348 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET); 349 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE, 350 ADVERTISE_ALL | ADVERTISE_CSMA | 351 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 352 353 /* read to clear */ 354 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC); 355 356 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK, 357 PHY_INT_MASK_DEFAULT_); 358 mii_nway_restart(udev, dev); 359 360 debug("phy initialised succesfully\n"); 361 return 0; 362 } 363 364 static int smsc95xx_init_mac_address(unsigned char *enetaddr, 365 struct usb_device *udev) 366 { 367 int ret; 368 369 /* try reading mac address from EEPROM */ 370 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr); 371 if (ret) 372 return ret; 373 374 if (is_valid_ethaddr(enetaddr)) { 375 /* eeprom values are valid so use them */ 376 debug("MAC address read from EEPROM\n"); 377 return 0; 378 } 379 380 /* 381 * No eeprom, or eeprom values are invalid. Generating a random MAC 382 * address is not safe. Just return an error. 383 */ 384 debug("Invalid MAC address read from EEPROM\n"); 385 386 return -ENXIO; 387 } 388 389 static int smsc95xx_write_hwaddr_common(struct usb_device *udev, 390 struct smsc95xx_private *priv, 391 unsigned char *enetaddr) 392 { 393 u32 addr_lo = __get_unaligned_le32(&enetaddr[0]); 394 u32 addr_hi = __get_unaligned_le16(&enetaddr[4]); 395 int ret; 396 397 /* set hardware address */ 398 debug("** %s()\n", __func__); 399 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo); 400 if (ret < 0) 401 return ret; 402 403 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi); 404 if (ret < 0) 405 return ret; 406 407 debug("MAC %pM\n", enetaddr); 408 priv->have_hwaddr = 1; 409 410 return 0; 411 } 412 413 /* Enable or disable Tx & Rx checksum offload engines */ 414 static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum, 415 int use_rx_csum) 416 { 417 u32 read_buf; 418 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf); 419 if (ret < 0) 420 return ret; 421 422 if (use_tx_csum) 423 read_buf |= Tx_COE_EN_; 424 else 425 read_buf &= ~Tx_COE_EN_; 426 427 if (use_rx_csum) 428 read_buf |= Rx_COE_EN_; 429 else 430 read_buf &= ~Rx_COE_EN_; 431 432 ret = smsc95xx_write_reg(udev, COE_CR, read_buf); 433 if (ret < 0) 434 return ret; 435 436 debug("COE_CR = 0x%08x\n", read_buf); 437 return 0; 438 } 439 440 static void smsc95xx_set_multicast(struct smsc95xx_private *priv) 441 { 442 /* No multicast in u-boot */ 443 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 444 } 445 446 /* starts the TX path */ 447 static void smsc95xx_start_tx_path(struct usb_device *udev, 448 struct smsc95xx_private *priv) 449 { 450 u32 reg_val; 451 452 /* Enable Tx at MAC */ 453 priv->mac_cr |= MAC_CR_TXEN_; 454 455 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr); 456 457 /* Enable Tx at SCSRs */ 458 reg_val = TX_CFG_ON_; 459 smsc95xx_write_reg(udev, TX_CFG, reg_val); 460 } 461 462 /* Starts the Receive path */ 463 static void smsc95xx_start_rx_path(struct usb_device *udev, 464 struct smsc95xx_private *priv) 465 { 466 priv->mac_cr |= MAC_CR_RXEN_; 467 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr); 468 } 469 470 static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev, 471 struct smsc95xx_private *priv, 472 unsigned char *enetaddr) 473 { 474 int ret; 475 u32 write_buf; 476 u32 read_buf; 477 u32 burst_cap; 478 int timeout; 479 #define TIMEOUT_RESOLUTION 50 /* ms */ 480 int link_detected; 481 482 debug("** %s()\n", __func__); 483 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 484 485 write_buf = HW_CFG_LRST_; 486 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf); 487 if (ret < 0) 488 return ret; 489 490 timeout = 0; 491 do { 492 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 493 if (ret < 0) 494 return ret; 495 udelay(10 * 1000); 496 timeout++; 497 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 498 499 if (timeout >= 100) { 500 debug("timeout waiting for completion of Lite Reset\n"); 501 return -ETIMEDOUT; 502 } 503 504 write_buf = PM_CTL_PHY_RST_; 505 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf); 506 if (ret < 0) 507 return ret; 508 509 timeout = 0; 510 do { 511 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf); 512 if (ret < 0) 513 return ret; 514 udelay(10 * 1000); 515 timeout++; 516 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 517 if (timeout >= 100) { 518 debug("timeout waiting for PHY Reset\n"); 519 return -ETIMEDOUT; 520 } 521 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) == 522 0) 523 priv->have_hwaddr = 1; 524 if (!priv->have_hwaddr) { 525 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 526 return -EADDRNOTAVAIL; 527 } 528 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr); 529 if (ret < 0) 530 return ret; 531 532 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 533 if (ret < 0) 534 return ret; 535 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 536 537 read_buf |= HW_CFG_BIR_; 538 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf); 539 if (ret < 0) 540 return ret; 541 542 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 543 if (ret < 0) 544 return ret; 545 debug("Read Value from HW_CFG after writing " 546 "HW_CFG_BIR_: 0x%08x\n", read_buf); 547 548 #ifdef TURBO_MODE 549 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 550 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 551 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 552 } else { 553 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 554 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 555 } 556 #else 557 burst_cap = 0; 558 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 559 #endif 560 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); 561 562 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap); 563 if (ret < 0) 564 return ret; 565 566 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf); 567 if (ret < 0) 568 return ret; 569 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 570 571 read_buf = DEFAULT_BULK_IN_DELAY; 572 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf); 573 if (ret < 0) 574 return ret; 575 576 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf); 577 if (ret < 0) 578 return ret; 579 debug("Read Value from BULK_IN_DLY after writing: " 580 "0x%08x\n", read_buf); 581 582 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 583 if (ret < 0) 584 return ret; 585 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 586 587 #ifdef TURBO_MODE 588 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 589 #endif 590 read_buf &= ~HW_CFG_RXDOFF_; 591 592 #define NET_IP_ALIGN 0 593 read_buf |= NET_IP_ALIGN << 9; 594 595 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf); 596 if (ret < 0) 597 return ret; 598 599 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 600 if (ret < 0) 601 return ret; 602 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 603 604 write_buf = 0xFFFFFFFF; 605 ret = smsc95xx_write_reg(udev, INT_STS, write_buf); 606 if (ret < 0) 607 return ret; 608 609 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf); 610 if (ret < 0) 611 return ret; 612 debug("ID_REV = 0x%08x\n", read_buf); 613 614 /* Configure GPIO pins as LED outputs */ 615 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | 616 LED_GPIO_CFG_FDX_LED; 617 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf); 618 if (ret < 0) 619 return ret; 620 debug("LED_GPIO_CFG set\n"); 621 622 /* Init Tx */ 623 write_buf = 0; 624 ret = smsc95xx_write_reg(udev, FLOW, write_buf); 625 if (ret < 0) 626 return ret; 627 628 read_buf = AFC_CFG_DEFAULT; 629 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf); 630 if (ret < 0) 631 return ret; 632 633 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr); 634 if (ret < 0) 635 return ret; 636 637 /* Init Rx. Set Vlan */ 638 write_buf = (u32)ETH_P_8021Q; 639 ret = smsc95xx_write_reg(udev, VLAN1, write_buf); 640 if (ret < 0) 641 return ret; 642 643 /* Disable checksum offload engines */ 644 ret = smsc95xx_set_csums(udev, 0, 0); 645 if (ret < 0) { 646 debug("Failed to set csum offload: %d\n", ret); 647 return ret; 648 } 649 smsc95xx_set_multicast(priv); 650 651 ret = smsc95xx_phy_initialize(udev, dev); 652 if (ret < 0) 653 return ret; 654 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf); 655 if (ret < 0) 656 return ret; 657 658 /* enable PHY interrupts */ 659 read_buf |= INT_EP_CTL_PHY_INT_; 660 661 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf); 662 if (ret < 0) 663 return ret; 664 665 smsc95xx_start_tx_path(udev, priv); 666 smsc95xx_start_rx_path(udev, priv); 667 668 timeout = 0; 669 do { 670 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR) 671 & BMSR_LSTATUS; 672 if (!link_detected) { 673 if (timeout == 0) 674 printf("Waiting for Ethernet connection... "); 675 udelay(TIMEOUT_RESOLUTION * 1000); 676 timeout += TIMEOUT_RESOLUTION; 677 } 678 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 679 if (link_detected) { 680 if (timeout != 0) 681 printf("done.\n"); 682 } else { 683 printf("unable to connect.\n"); 684 return -EIO; 685 } 686 return 0; 687 } 688 689 static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length) 690 { 691 int err; 692 int actual_len; 693 u32 tx_cmd_a; 694 u32 tx_cmd_b; 695 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 696 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); 697 698 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 699 if (length > PKTSIZE) 700 return -ENOSPC; 701 702 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 703 tx_cmd_b = (u32)length; 704 cpu_to_le32s(&tx_cmd_a); 705 cpu_to_le32s(&tx_cmd_b); 706 707 /* prepend cmd_a and cmd_b */ 708 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 709 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 710 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 711 length); 712 err = usb_bulk_msg(dev->pusb_dev, 713 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 714 (void *)msg, 715 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 716 &actual_len, 717 USB_BULK_SEND_TIMEOUT); 718 debug("Tx: len = %u, actual = %u, err = %d\n", 719 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 720 actual_len, err); 721 722 return err; 723 } 724 725 #ifndef CONFIG_DM_ETH 726 /* 727 * Smsc95xx callbacks 728 */ 729 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 730 { 731 struct ueth_data *dev = (struct ueth_data *)eth->priv; 732 struct usb_device *udev = dev->pusb_dev; 733 struct smsc95xx_private *priv = 734 (struct smsc95xx_private *)dev->dev_priv; 735 736 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr); 737 } 738 739 static int smsc95xx_send(struct eth_device *eth, void *packet, int length) 740 { 741 struct ueth_data *dev = (struct ueth_data *)eth->priv; 742 743 return smsc95xx_send_common(dev, packet, length); 744 } 745 746 static int smsc95xx_recv(struct eth_device *eth) 747 { 748 struct ueth_data *dev = (struct ueth_data *)eth->priv; 749 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE); 750 unsigned char *buf_ptr; 751 int err; 752 int actual_len; 753 u32 packet_len; 754 int cur_buf_align; 755 756 debug("** %s()\n", __func__); 757 err = usb_bulk_msg(dev->pusb_dev, 758 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 759 (void *)recv_buf, RX_URB_SIZE, &actual_len, 760 USB_BULK_RECV_TIMEOUT); 761 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE, 762 actual_len, err); 763 if (err != 0) { 764 debug("Rx: failed to receive\n"); 765 return -err; 766 } 767 if (actual_len > RX_URB_SIZE) { 768 debug("Rx: received too many bytes %d\n", actual_len); 769 return -ENOSPC; 770 } 771 772 buf_ptr = recv_buf; 773 while (actual_len > 0) { 774 /* 775 * 1st 4 bytes contain the length of the actual data plus error 776 * info. Extract data length. 777 */ 778 if (actual_len < sizeof(packet_len)) { 779 debug("Rx: incomplete packet length\n"); 780 return -EIO; 781 } 782 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 783 le32_to_cpus(&packet_len); 784 if (packet_len & RX_STS_ES_) { 785 debug("Rx: Error header=%#x", packet_len); 786 return -EIO; 787 } 788 packet_len = ((packet_len & RX_STS_FL_) >> 16); 789 790 if (packet_len > actual_len - sizeof(packet_len)) { 791 debug("Rx: too large packet: %d\n", packet_len); 792 return -EIO; 793 } 794 795 /* Notify net stack */ 796 net_process_received_packet(buf_ptr + sizeof(packet_len), 797 packet_len - 4); 798 799 /* Adjust for next iteration */ 800 actual_len -= sizeof(packet_len) + packet_len; 801 buf_ptr += sizeof(packet_len) + packet_len; 802 cur_buf_align = (int)buf_ptr - (int)recv_buf; 803 804 if (cur_buf_align & 0x03) { 805 int align = 4 - (cur_buf_align & 0x03); 806 807 actual_len -= align; 808 buf_ptr += align; 809 } 810 } 811 return err; 812 } 813 814 static void smsc95xx_halt(struct eth_device *eth) 815 { 816 debug("** %s()\n", __func__); 817 } 818 819 static int smsc95xx_write_hwaddr(struct eth_device *eth) 820 { 821 struct ueth_data *dev = eth->priv; 822 struct usb_device *udev = dev->pusb_dev; 823 struct smsc95xx_private *priv = dev->dev_priv; 824 825 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr); 826 } 827 828 /* 829 * SMSC probing functions 830 */ 831 void smsc95xx_eth_before_probe(void) 832 { 833 curr_eth_dev = 0; 834 } 835 836 struct smsc95xx_dongle { 837 unsigned short vendor; 838 unsigned short product; 839 }; 840 841 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 842 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 843 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 844 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ 845 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */ 846 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */ 847 { 0x0000, 0x0000 } /* END - Do not remove */ 848 }; 849 850 /* Probe to see if a new device is actually an SMSC device */ 851 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 852 struct ueth_data *ss) 853 { 854 struct usb_interface *iface; 855 struct usb_interface_descriptor *iface_desc; 856 int i; 857 858 /* let's examine the device now */ 859 iface = &dev->config.if_desc[ifnum]; 860 iface_desc = &dev->config.if_desc[ifnum].desc; 861 862 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 863 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 864 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 865 /* Found a supported dongle */ 866 break; 867 } 868 if (smsc95xx_dongles[i].vendor == 0) 869 return 0; 870 871 /* At this point, we know we've got a live one */ 872 debug("\n\nUSB Ethernet device detected\n"); 873 memset(ss, '\0', sizeof(struct ueth_data)); 874 875 /* Initialize the ueth_data structure with some useful info */ 876 ss->ifnum = ifnum; 877 ss->pusb_dev = dev; 878 ss->subclass = iface_desc->bInterfaceSubClass; 879 ss->protocol = iface_desc->bInterfaceProtocol; 880 881 /* 882 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 883 * We will ignore any others. 884 */ 885 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 886 /* is it an BULK endpoint? */ 887 if ((iface->ep_desc[i].bmAttributes & 888 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 889 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 890 ss->ep_in = 891 iface->ep_desc[i].bEndpointAddress & 892 USB_ENDPOINT_NUMBER_MASK; 893 else 894 ss->ep_out = 895 iface->ep_desc[i].bEndpointAddress & 896 USB_ENDPOINT_NUMBER_MASK; 897 } 898 899 /* is it an interrupt endpoint? */ 900 if ((iface->ep_desc[i].bmAttributes & 901 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 902 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 903 USB_ENDPOINT_NUMBER_MASK; 904 ss->irqinterval = iface->ep_desc[i].bInterval; 905 } 906 } 907 debug("Endpoints In %d Out %d Int %d\n", 908 ss->ep_in, ss->ep_out, ss->ep_int); 909 910 /* Do some basic sanity checks, and bail if we find a problem */ 911 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 912 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 913 debug("Problems with device\n"); 914 return 0; 915 } 916 dev->privptr = (void *)ss; 917 918 /* alloc driver private */ 919 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); 920 if (!ss->dev_priv) 921 return 0; 922 923 return 1; 924 } 925 926 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 927 struct eth_device *eth) 928 { 929 debug("** %s()\n", __func__); 930 if (!eth) { 931 debug("%s: missing parameter.\n", __func__); 932 return 0; 933 } 934 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 935 eth->init = smsc95xx_init; 936 eth->send = smsc95xx_send; 937 eth->recv = smsc95xx_recv; 938 eth->halt = smsc95xx_halt; 939 eth->write_hwaddr = smsc95xx_write_hwaddr; 940 eth->priv = ss; 941 return 1; 942 } 943 #endif /* !CONFIG_DM_ETH */ 944 945 #ifdef CONFIG_DM_ETH 946 static int smsc95xx_eth_start(struct udevice *dev) 947 { 948 struct usb_device *udev = dev_get_parentdata(dev); 949 struct smsc95xx_private *priv = dev_get_priv(dev); 950 struct eth_pdata *pdata = dev_get_platdata(dev); 951 952 /* Driver-model Ethernet ensures we have this */ 953 priv->have_hwaddr = 1; 954 955 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr); 956 } 957 958 void smsc95xx_eth_stop(struct udevice *dev) 959 { 960 debug("** %s()\n", __func__); 961 } 962 963 int smsc95xx_eth_send(struct udevice *dev, void *packet, int length) 964 { 965 struct smsc95xx_private *priv = dev_get_priv(dev); 966 967 return smsc95xx_send_common(&priv->ueth, packet, length); 968 } 969 970 int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp) 971 { 972 struct smsc95xx_private *priv = dev_get_priv(dev); 973 struct ueth_data *ueth = &priv->ueth; 974 uint8_t *ptr; 975 int ret, len; 976 u32 packet_len; 977 978 len = usb_ether_get_rx_bytes(ueth, &ptr); 979 debug("%s: first try, len=%d\n", __func__, len); 980 if (!len) { 981 if (!(flags & ETH_RECV_CHECK_DEVICE)) 982 return -EAGAIN; 983 ret = usb_ether_receive(ueth, RX_URB_SIZE); 984 if (ret == -EAGAIN) 985 return ret; 986 987 len = usb_ether_get_rx_bytes(ueth, &ptr); 988 debug("%s: second try, len=%d\n", __func__, len); 989 } 990 991 /* 992 * 1st 4 bytes contain the length of the actual data plus error info. 993 * Extract data length. 994 */ 995 if (len < sizeof(packet_len)) { 996 debug("Rx: incomplete packet length\n"); 997 goto err; 998 } 999 memcpy(&packet_len, ptr, sizeof(packet_len)); 1000 le32_to_cpus(&packet_len); 1001 if (packet_len & RX_STS_ES_) { 1002 debug("Rx: Error header=%#x", packet_len); 1003 goto err; 1004 } 1005 packet_len = ((packet_len & RX_STS_FL_) >> 16); 1006 1007 if (packet_len > len - sizeof(packet_len)) { 1008 debug("Rx: too large packet: %d\n", packet_len); 1009 goto err; 1010 } 1011 1012 *packetp = ptr + sizeof(packet_len); 1013 return packet_len; 1014 1015 err: 1016 usb_ether_advance_rxbuf(ueth, -1); 1017 return -EINVAL; 1018 } 1019 1020 static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len) 1021 { 1022 struct smsc95xx_private *priv = dev_get_priv(dev); 1023 1024 packet_len = ALIGN(packet_len, 4); 1025 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len); 1026 1027 return 0; 1028 } 1029 1030 int smsc95xx_write_hwaddr(struct udevice *dev) 1031 { 1032 struct usb_device *udev = dev_get_parentdata(dev); 1033 struct eth_pdata *pdata = dev_get_platdata(dev); 1034 struct smsc95xx_private *priv = dev_get_priv(dev); 1035 1036 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr); 1037 } 1038 1039 static int smsc95xx_eth_probe(struct udevice *dev) 1040 { 1041 struct smsc95xx_private *priv = dev_get_priv(dev); 1042 struct ueth_data *ueth = &priv->ueth; 1043 1044 return usb_ether_register(dev, ueth, RX_URB_SIZE); 1045 } 1046 1047 static const struct eth_ops smsc95xx_eth_ops = { 1048 .start = smsc95xx_eth_start, 1049 .send = smsc95xx_eth_send, 1050 .recv = smsc95xx_eth_recv, 1051 .free_pkt = smsc95xx_free_pkt, 1052 .stop = smsc95xx_eth_stop, 1053 .write_hwaddr = smsc95xx_write_hwaddr, 1054 }; 1055 1056 U_BOOT_DRIVER(smsc95xx_eth) = { 1057 .name = "smsc95xx_eth", 1058 .id = UCLASS_ETH, 1059 .probe = smsc95xx_eth_probe, 1060 .ops = &smsc95xx_eth_ops, 1061 .priv_auto_alloc_size = sizeof(struct smsc95xx_private), 1062 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1063 }; 1064 1065 static const struct usb_device_id smsc95xx_eth_id_table[] = { 1066 { USB_DEVICE(0x05ac, 0x1402) }, 1067 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */ 1068 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */ 1069 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */ 1070 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */ 1071 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */ 1072 { } /* Terminating entry */ 1073 }; 1074 1075 U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table); 1076 #endif 1077