1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (C) 2009 NVIDIA, Corporation 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <asm/unaligned.h> 24 #include <common.h> 25 #include <usb.h> 26 #include <linux/mii.h> 27 #include "usb_ether.h" 28 #include <malloc.h> 29 30 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 31 32 /* Tx command words */ 33 #define TX_CMD_A_FIRST_SEG_ 0x00002000 34 #define TX_CMD_A_LAST_SEG_ 0x00001000 35 36 /* Rx status word */ 37 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 38 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 39 40 /* SCSRs */ 41 #define ID_REV 0x00 42 43 #define INT_STS 0x08 44 45 #define TX_CFG 0x10 46 #define TX_CFG_ON_ 0x00000004 47 48 #define HW_CFG 0x14 49 #define HW_CFG_BIR_ 0x00001000 50 #define HW_CFG_RXDOFF_ 0x00000600 51 #define HW_CFG_MEF_ 0x00000020 52 #define HW_CFG_BCE_ 0x00000002 53 #define HW_CFG_LRST_ 0x00000008 54 55 #define PM_CTRL 0x20 56 #define PM_CTL_PHY_RST_ 0x00000010 57 58 #define AFC_CFG 0x2C 59 60 /* 61 * Hi watermark = 15.5Kb (~10 mtu pkts) 62 * low watermark = 3k (~2 mtu pkts) 63 * backpressure duration = ~ 350us 64 * Apply FC on any frame. 65 */ 66 #define AFC_CFG_DEFAULT 0x00F830A1 67 68 #define E2P_CMD 0x30 69 #define E2P_CMD_BUSY_ 0x80000000 70 #define E2P_CMD_READ_ 0x00000000 71 #define E2P_CMD_TIMEOUT_ 0x00000400 72 #define E2P_CMD_LOADED_ 0x00000200 73 #define E2P_CMD_ADDR_ 0x000001FF 74 75 #define E2P_DATA 0x34 76 77 #define BURST_CAP 0x38 78 79 #define INT_EP_CTL 0x68 80 #define INT_EP_CTL_PHY_INT_ 0x00008000 81 82 #define BULK_IN_DLY 0x6C 83 84 /* MAC CSRs */ 85 #define MAC_CR 0x100 86 #define MAC_CR_MCPAS_ 0x00080000 87 #define MAC_CR_PRMS_ 0x00040000 88 #define MAC_CR_HPFILT_ 0x00002000 89 #define MAC_CR_TXEN_ 0x00000008 90 #define MAC_CR_RXEN_ 0x00000004 91 92 #define ADDRH 0x104 93 94 #define ADDRL 0x108 95 96 #define MII_ADDR 0x114 97 #define MII_WRITE_ 0x02 98 #define MII_BUSY_ 0x01 99 #define MII_READ_ 0x00 /* ~of MII Write bit */ 100 101 #define MII_DATA 0x118 102 103 #define FLOW 0x11C 104 105 #define VLAN1 0x120 106 107 #define COE_CR 0x130 108 #define Tx_COE_EN_ 0x00010000 109 #define Rx_COE_EN_ 0x00000001 110 111 /* Vendor-specific PHY Definitions */ 112 #define PHY_INT_SRC 29 113 114 #define PHY_INT_MASK 30 115 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 116 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 117 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 118 PHY_INT_MASK_LINK_DOWN_) 119 120 /* USB Vendor Requests */ 121 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 122 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 123 124 /* Some extra defines */ 125 #define HS_USB_PKT_SIZE 512 126 #define FS_USB_PKT_SIZE 64 127 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 128 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 129 #define DEFAULT_BULK_IN_DELAY 0x00002000 130 #define MAX_SINGLE_PACKET_SIZE 2048 131 #define EEPROM_MAC_OFFSET 0x01 132 #define SMSC95XX_INTERNAL_PHY_ID 1 133 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 134 135 /* local defines */ 136 #define SMSC95XX_BASE_NAME "sms" 137 #define USB_CTRL_SET_TIMEOUT 5000 138 #define USB_CTRL_GET_TIMEOUT 5000 139 #define USB_BULK_SEND_TIMEOUT 5000 140 #define USB_BULK_RECV_TIMEOUT 5000 141 142 #define AX_RX_URB_SIZE 2048 143 #define PHY_CONNECT_TIMEOUT 5000 144 145 #define TURBO_MODE 146 147 /* local vars */ 148 static int curr_eth_dev; /* index for name of next device detected */ 149 150 /* driver private */ 151 struct smsc95xx_private { 152 size_t rx_urb_size; /* maximum USB URB size */ 153 u32 mac_cr; /* MAC control register value */ 154 int have_hwaddr; /* 1 if we have a hardware MAC address */ 155 }; 156 157 /* 158 * Smsc95xx infrastructure commands 159 */ 160 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) 161 { 162 int len; 163 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 164 165 cpu_to_le32s(&data); 166 tmpbuf[0] = data; 167 168 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0), 169 USB_VENDOR_REQUEST_WRITE_REGISTER, 170 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 171 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT); 172 if (len != sizeof(data)) { 173 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 174 index, data, len); 175 return -1; 176 } 177 return 0; 178 } 179 180 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data) 181 { 182 int len; 183 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 184 185 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0), 186 USB_VENDOR_REQUEST_READ_REGISTER, 187 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 188 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT); 189 *data = tmpbuf[0]; 190 if (len != sizeof(data)) { 191 debug("smsc95xx_read_reg failed: index=%d, len=%d", 192 index, len); 193 return -1; 194 } 195 196 le32_to_cpus(data); 197 return 0; 198 } 199 200 /* Loop until the read is completed with timeout */ 201 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev) 202 { 203 unsigned long start_time = get_timer(0); 204 u32 val; 205 206 do { 207 smsc95xx_read_reg(dev, MII_ADDR, &val); 208 if (!(val & MII_BUSY_)) 209 return 0; 210 } while (get_timer(start_time) < 1 * 1000 * 1000); 211 212 return -1; 213 } 214 215 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx) 216 { 217 u32 val, addr; 218 219 /* confirm MII not busy */ 220 if (smsc95xx_phy_wait_not_busy(dev)) { 221 debug("MII is busy in smsc95xx_mdio_read\n"); 222 return -1; 223 } 224 225 /* set the address, index & direction (read from PHY) */ 226 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 227 smsc95xx_write_reg(dev, MII_ADDR, addr); 228 229 if (smsc95xx_phy_wait_not_busy(dev)) { 230 debug("Timed out reading MII reg %02X\n", idx); 231 return -1; 232 } 233 234 smsc95xx_read_reg(dev, MII_DATA, &val); 235 236 return (u16)(val & 0xFFFF); 237 } 238 239 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx, 240 int regval) 241 { 242 u32 val, addr; 243 244 /* confirm MII not busy */ 245 if (smsc95xx_phy_wait_not_busy(dev)) { 246 debug("MII is busy in smsc95xx_mdio_write\n"); 247 return; 248 } 249 250 val = regval; 251 smsc95xx_write_reg(dev, MII_DATA, val); 252 253 /* set the address, index & direction (write to PHY) */ 254 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 255 smsc95xx_write_reg(dev, MII_ADDR, addr); 256 257 if (smsc95xx_phy_wait_not_busy(dev)) 258 debug("Timed out writing MII reg %02X\n", idx); 259 } 260 261 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev) 262 { 263 unsigned long start_time = get_timer(0); 264 u32 val; 265 266 do { 267 smsc95xx_read_reg(dev, E2P_CMD, &val); 268 if (!(val & E2P_CMD_BUSY_)) 269 return 0; 270 udelay(40); 271 } while (get_timer(start_time) < 1 * 1000 * 1000); 272 273 debug("EEPROM is busy\n"); 274 return -1; 275 } 276 277 static int smsc95xx_wait_eeprom(struct ueth_data *dev) 278 { 279 unsigned long start_time = get_timer(0); 280 u32 val; 281 282 do { 283 smsc95xx_read_reg(dev, E2P_CMD, &val); 284 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 285 break; 286 udelay(40); 287 } while (get_timer(start_time) < 1 * 1000 * 1000); 288 289 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 290 debug("EEPROM read operation timeout\n"); 291 return -1; 292 } 293 return 0; 294 } 295 296 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length, 297 u8 *data) 298 { 299 u32 val; 300 int i, ret; 301 302 ret = smsc95xx_eeprom_confirm_not_busy(dev); 303 if (ret) 304 return ret; 305 306 for (i = 0; i < length; i++) { 307 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 308 smsc95xx_write_reg(dev, E2P_CMD, val); 309 310 ret = smsc95xx_wait_eeprom(dev); 311 if (ret < 0) 312 return ret; 313 314 smsc95xx_read_reg(dev, E2P_DATA, &val); 315 data[i] = val & 0xFF; 316 offset++; 317 } 318 return 0; 319 } 320 321 /* 322 * mii_nway_restart - restart NWay (autonegotiation) for this interface 323 * 324 * Returns 0 on success, negative on error. 325 */ 326 static int mii_nway_restart(struct ueth_data *dev) 327 { 328 int bmcr; 329 int r = -1; 330 331 /* if autoneg is off, it's an error */ 332 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR); 333 334 if (bmcr & BMCR_ANENABLE) { 335 bmcr |= BMCR_ANRESTART; 336 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 337 r = 0; 338 } 339 return r; 340 } 341 342 static int smsc95xx_phy_initialize(struct ueth_data *dev) 343 { 344 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 345 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 346 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 347 ADVERTISE_PAUSE_ASYM); 348 349 /* read to clear */ 350 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC); 351 352 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK, 353 PHY_INT_MASK_DEFAULT_); 354 mii_nway_restart(dev); 355 356 debug("phy initialised succesfully\n"); 357 return 0; 358 } 359 360 static int smsc95xx_init_mac_address(struct eth_device *eth, 361 struct ueth_data *dev) 362 { 363 /* try reading mac address from EEPROM */ 364 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 365 eth->enetaddr) == 0) { 366 if (is_valid_ether_addr(eth->enetaddr)) { 367 /* eeprom values are valid so use them */ 368 debug("MAC address read from EEPROM\n"); 369 return 0; 370 } 371 } 372 373 /* 374 * No eeprom, or eeprom values are invalid. Generating a random MAC 375 * address is not safe. Just return an error. 376 */ 377 return -1; 378 } 379 380 static int smsc95xx_write_hwaddr(struct eth_device *eth) 381 { 382 struct ueth_data *dev = (struct ueth_data *)eth->priv; 383 struct smsc95xx_private *priv = dev->dev_priv; 384 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]); 385 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]); 386 int ret; 387 388 /* set hardware address */ 389 debug("** %s()\n", __func__); 390 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); 391 if (ret < 0) 392 return ret; 393 394 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); 395 if (ret < 0) 396 return ret; 397 398 debug("MAC %pM\n", eth->enetaddr); 399 priv->have_hwaddr = 1; 400 return 0; 401 } 402 403 /* Enable or disable Tx & Rx checksum offload engines */ 404 static int smsc95xx_set_csums(struct ueth_data *dev, 405 int use_tx_csum, int use_rx_csum) 406 { 407 u32 read_buf; 408 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); 409 if (ret < 0) 410 return ret; 411 412 if (use_tx_csum) 413 read_buf |= Tx_COE_EN_; 414 else 415 read_buf &= ~Tx_COE_EN_; 416 417 if (use_rx_csum) 418 read_buf |= Rx_COE_EN_; 419 else 420 read_buf &= ~Rx_COE_EN_; 421 422 ret = smsc95xx_write_reg(dev, COE_CR, read_buf); 423 if (ret < 0) 424 return ret; 425 426 debug("COE_CR = 0x%08x\n", read_buf); 427 return 0; 428 } 429 430 static void smsc95xx_set_multicast(struct ueth_data *dev) 431 { 432 struct smsc95xx_private *priv = dev->dev_priv; 433 434 /* No multicast in u-boot */ 435 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 436 } 437 438 /* starts the TX path */ 439 static void smsc95xx_start_tx_path(struct ueth_data *dev) 440 { 441 struct smsc95xx_private *priv = dev->dev_priv; 442 u32 reg_val; 443 444 /* Enable Tx at MAC */ 445 priv->mac_cr |= MAC_CR_TXEN_; 446 447 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 448 449 /* Enable Tx at SCSRs */ 450 reg_val = TX_CFG_ON_; 451 smsc95xx_write_reg(dev, TX_CFG, reg_val); 452 } 453 454 /* Starts the Receive path */ 455 static void smsc95xx_start_rx_path(struct ueth_data *dev) 456 { 457 struct smsc95xx_private *priv = dev->dev_priv; 458 459 priv->mac_cr |= MAC_CR_RXEN_; 460 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); 461 } 462 463 /* 464 * Smsc95xx callbacks 465 */ 466 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 467 { 468 int ret; 469 u32 write_buf; 470 u32 read_buf; 471 u32 burst_cap; 472 int timeout; 473 struct ueth_data *dev = (struct ueth_data *)eth->priv; 474 struct smsc95xx_private *priv = 475 (struct smsc95xx_private *)dev->dev_priv; 476 #define TIMEOUT_RESOLUTION 50 /* ms */ 477 int link_detected; 478 479 debug("** %s()\n", __func__); 480 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 481 482 write_buf = HW_CFG_LRST_; 483 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf); 484 if (ret < 0) 485 return ret; 486 487 timeout = 0; 488 do { 489 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 490 if (ret < 0) 491 return ret; 492 udelay(10 * 1000); 493 timeout++; 494 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 495 496 if (timeout >= 100) { 497 debug("timeout waiting for completion of Lite Reset\n"); 498 return -1; 499 } 500 501 write_buf = PM_CTL_PHY_RST_; 502 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf); 503 if (ret < 0) 504 return ret; 505 506 timeout = 0; 507 do { 508 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); 509 if (ret < 0) 510 return ret; 511 udelay(10 * 1000); 512 timeout++; 513 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 514 if (timeout >= 100) { 515 debug("timeout waiting for PHY Reset\n"); 516 return -1; 517 } 518 if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) 519 priv->have_hwaddr = 1; 520 if (!priv->have_hwaddr) { 521 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 522 return -1; 523 } 524 if (smsc95xx_write_hwaddr(eth) < 0) 525 return -1; 526 527 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 528 if (ret < 0) 529 return ret; 530 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 531 532 read_buf |= HW_CFG_BIR_; 533 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 534 if (ret < 0) 535 return ret; 536 537 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 538 if (ret < 0) 539 return ret; 540 debug("Read Value from HW_CFG after writing " 541 "HW_CFG_BIR_: 0x%08x\n", read_buf); 542 543 #ifdef TURBO_MODE 544 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 545 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 546 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 547 } else { 548 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 549 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 550 } 551 #else 552 burst_cap = 0; 553 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 554 #endif 555 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); 556 557 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); 558 if (ret < 0) 559 return ret; 560 561 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); 562 if (ret < 0) 563 return ret; 564 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 565 566 read_buf = DEFAULT_BULK_IN_DELAY; 567 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf); 568 if (ret < 0) 569 return ret; 570 571 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); 572 if (ret < 0) 573 return ret; 574 debug("Read Value from BULK_IN_DLY after writing: " 575 "0x%08x\n", read_buf); 576 577 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 578 if (ret < 0) 579 return ret; 580 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 581 582 #ifdef TURBO_MODE 583 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 584 #endif 585 read_buf &= ~HW_CFG_RXDOFF_; 586 587 #define NET_IP_ALIGN 0 588 read_buf |= NET_IP_ALIGN << 9; 589 590 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 591 if (ret < 0) 592 return ret; 593 594 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 595 if (ret < 0) 596 return ret; 597 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 598 599 write_buf = 0xFFFFFFFF; 600 ret = smsc95xx_write_reg(dev, INT_STS, write_buf); 601 if (ret < 0) 602 return ret; 603 604 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); 605 if (ret < 0) 606 return ret; 607 debug("ID_REV = 0x%08x\n", read_buf); 608 609 /* Init Tx */ 610 write_buf = 0; 611 ret = smsc95xx_write_reg(dev, FLOW, write_buf); 612 if (ret < 0) 613 return ret; 614 615 read_buf = AFC_CFG_DEFAULT; 616 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf); 617 if (ret < 0) 618 return ret; 619 620 ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr); 621 if (ret < 0) 622 return ret; 623 624 /* Init Rx. Set Vlan */ 625 write_buf = (u32)ETH_P_8021Q; 626 ret = smsc95xx_write_reg(dev, VLAN1, write_buf); 627 if (ret < 0) 628 return ret; 629 630 /* Disable checksum offload engines */ 631 ret = smsc95xx_set_csums(dev, 0, 0); 632 if (ret < 0) { 633 debug("Failed to set csum offload: %d\n", ret); 634 return ret; 635 } 636 smsc95xx_set_multicast(dev); 637 638 if (smsc95xx_phy_initialize(dev) < 0) 639 return -1; 640 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); 641 if (ret < 0) 642 return ret; 643 644 /* enable PHY interrupts */ 645 read_buf |= INT_EP_CTL_PHY_INT_; 646 647 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); 648 if (ret < 0) 649 return ret; 650 651 smsc95xx_start_tx_path(dev); 652 smsc95xx_start_rx_path(dev); 653 654 timeout = 0; 655 do { 656 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR) 657 & BMSR_LSTATUS; 658 if (!link_detected) { 659 if (timeout == 0) 660 printf("Waiting for Ethernet connection... "); 661 udelay(TIMEOUT_RESOLUTION * 1000); 662 timeout += TIMEOUT_RESOLUTION; 663 } 664 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 665 if (link_detected) { 666 if (timeout != 0) 667 printf("done.\n"); 668 } else { 669 printf("unable to connect.\n"); 670 return -1; 671 } 672 return 0; 673 } 674 675 static int smsc95xx_send(struct eth_device *eth, void* packet, int length) 676 { 677 struct ueth_data *dev = (struct ueth_data *)eth->priv; 678 int err; 679 int actual_len; 680 u32 tx_cmd_a; 681 u32 tx_cmd_b; 682 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 683 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); 684 685 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 686 if (length > PKTSIZE) 687 return -1; 688 689 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 690 tx_cmd_b = (u32)length; 691 cpu_to_le32s(&tx_cmd_a); 692 cpu_to_le32s(&tx_cmd_b); 693 694 /* prepend cmd_a and cmd_b */ 695 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 696 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 697 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 698 length); 699 err = usb_bulk_msg(dev->pusb_dev, 700 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 701 (void *)msg, 702 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 703 &actual_len, 704 USB_BULK_SEND_TIMEOUT); 705 debug("Tx: len = %u, actual = %u, err = %d\n", 706 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 707 actual_len, err); 708 return err; 709 } 710 711 static int smsc95xx_recv(struct eth_device *eth) 712 { 713 struct ueth_data *dev = (struct ueth_data *)eth->priv; 714 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); 715 unsigned char *buf_ptr; 716 int err; 717 int actual_len; 718 u32 packet_len; 719 int cur_buf_align; 720 721 debug("** %s()\n", __func__); 722 err = usb_bulk_msg(dev->pusb_dev, 723 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 724 (void *)recv_buf, 725 AX_RX_URB_SIZE, 726 &actual_len, 727 USB_BULK_RECV_TIMEOUT); 728 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 729 actual_len, err); 730 if (err != 0) { 731 debug("Rx: failed to receive\n"); 732 return -1; 733 } 734 if (actual_len > AX_RX_URB_SIZE) { 735 debug("Rx: received too many bytes %d\n", actual_len); 736 return -1; 737 } 738 739 buf_ptr = recv_buf; 740 while (actual_len > 0) { 741 /* 742 * 1st 4 bytes contain the length of the actual data plus error 743 * info. Extract data length. 744 */ 745 if (actual_len < sizeof(packet_len)) { 746 debug("Rx: incomplete packet length\n"); 747 return -1; 748 } 749 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 750 le32_to_cpus(&packet_len); 751 if (packet_len & RX_STS_ES_) { 752 debug("Rx: Error header=%#x", packet_len); 753 return -1; 754 } 755 packet_len = ((packet_len & RX_STS_FL_) >> 16); 756 757 if (packet_len > actual_len - sizeof(packet_len)) { 758 debug("Rx: too large packet: %d\n", packet_len); 759 return -1; 760 } 761 762 /* Notify net stack */ 763 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4); 764 765 /* Adjust for next iteration */ 766 actual_len -= sizeof(packet_len) + packet_len; 767 buf_ptr += sizeof(packet_len) + packet_len; 768 cur_buf_align = (int)buf_ptr - (int)recv_buf; 769 770 if (cur_buf_align & 0x03) { 771 int align = 4 - (cur_buf_align & 0x03); 772 773 actual_len -= align; 774 buf_ptr += align; 775 } 776 } 777 return err; 778 } 779 780 static void smsc95xx_halt(struct eth_device *eth) 781 { 782 debug("** %s()\n", __func__); 783 } 784 785 /* 786 * SMSC probing functions 787 */ 788 void smsc95xx_eth_before_probe(void) 789 { 790 curr_eth_dev = 0; 791 } 792 793 struct smsc95xx_dongle { 794 unsigned short vendor; 795 unsigned short product; 796 }; 797 798 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 799 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 800 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 801 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ 802 { 0x0000, 0x0000 } /* END - Do not remove */ 803 }; 804 805 /* Probe to see if a new device is actually an SMSC device */ 806 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 807 struct ueth_data *ss) 808 { 809 struct usb_interface *iface; 810 struct usb_interface_descriptor *iface_desc; 811 int i; 812 813 /* let's examine the device now */ 814 iface = &dev->config.if_desc[ifnum]; 815 iface_desc = &dev->config.if_desc[ifnum].desc; 816 817 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 818 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 819 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 820 /* Found a supported dongle */ 821 break; 822 } 823 if (smsc95xx_dongles[i].vendor == 0) 824 return 0; 825 826 /* At this point, we know we've got a live one */ 827 debug("\n\nUSB Ethernet device detected\n"); 828 memset(ss, '\0', sizeof(struct ueth_data)); 829 830 /* Initialize the ueth_data structure with some useful info */ 831 ss->ifnum = ifnum; 832 ss->pusb_dev = dev; 833 ss->subclass = iface_desc->bInterfaceSubClass; 834 ss->protocol = iface_desc->bInterfaceProtocol; 835 836 /* 837 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 838 * We will ignore any others. 839 */ 840 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 841 /* is it an BULK endpoint? */ 842 if ((iface->ep_desc[i].bmAttributes & 843 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 844 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 845 ss->ep_in = 846 iface->ep_desc[i].bEndpointAddress & 847 USB_ENDPOINT_NUMBER_MASK; 848 else 849 ss->ep_out = 850 iface->ep_desc[i].bEndpointAddress & 851 USB_ENDPOINT_NUMBER_MASK; 852 } 853 854 /* is it an interrupt endpoint? */ 855 if ((iface->ep_desc[i].bmAttributes & 856 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 857 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 858 USB_ENDPOINT_NUMBER_MASK; 859 ss->irqinterval = iface->ep_desc[i].bInterval; 860 } 861 } 862 debug("Endpoints In %d Out %d Int %d\n", 863 ss->ep_in, ss->ep_out, ss->ep_int); 864 865 /* Do some basic sanity checks, and bail if we find a problem */ 866 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 867 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 868 debug("Problems with device\n"); 869 return 0; 870 } 871 dev->privptr = (void *)ss; 872 873 /* alloc driver private */ 874 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); 875 if (!ss->dev_priv) 876 return 0; 877 878 return 1; 879 } 880 881 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 882 struct eth_device *eth) 883 { 884 debug("** %s()\n", __func__); 885 if (!eth) { 886 debug("%s: missing parameter.\n", __func__); 887 return 0; 888 } 889 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 890 eth->init = smsc95xx_init; 891 eth->send = smsc95xx_send; 892 eth->recv = smsc95xx_recv; 893 eth->halt = smsc95xx_halt; 894 eth->write_hwaddr = smsc95xx_write_hwaddr; 895 eth->priv = ss; 896 return 1; 897 } 898