1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. 4 * 5 */ 6 7 #ifndef _RTL8152_ETH_H 8 #define _RTL8152_ETH_H 9 10 #define R8152_BASE_NAME "r8152" 11 12 #define PLA_IDR 0xc000 13 #define PLA_RCR 0xc010 14 #define PLA_RMS 0xc016 15 #define PLA_RXFIFO_CTRL0 0xc0a0 16 #define PLA_RXFIFO_CTRL1 0xc0a4 17 #define PLA_RXFIFO_CTRL2 0xc0a8 18 #define PLA_DMY_REG0 0xc0b0 19 #define PLA_FMC 0xc0b4 20 #define PLA_CFG_WOL 0xc0b6 21 #define PLA_TEREDO_CFG 0xc0bc 22 #define PLA_MAR 0xcd00 23 #define PLA_BACKUP 0xd000 24 #define PAL_BDC_CR 0xd1a0 25 #define PLA_TEREDO_TIMER 0xd2cc 26 #define PLA_REALWOW_TIMER 0xd2e8 27 #define PLA_LEDSEL 0xdd90 28 #define PLA_LED_FEATURE 0xdd92 29 #define PLA_PHYAR 0xde00 30 #define PLA_BOOT_CTRL 0xe004 31 #define PLA_GPHY_INTR_IMR 0xe022 32 #define PLA_EEE_CR 0xe040 33 #define PLA_EEEP_CR 0xe080 34 #define PLA_MAC_PWR_CTRL 0xe0c0 35 #define PLA_MAC_PWR_CTRL2 0xe0ca 36 #define PLA_MAC_PWR_CTRL3 0xe0cc 37 #define PLA_MAC_PWR_CTRL4 0xe0ce 38 #define PLA_WDT6_CTRL 0xe428 39 #define PLA_TCR0 0xe610 40 #define PLA_TCR1 0xe612 41 #define PLA_MTPS 0xe615 42 #define PLA_TXFIFO_CTRL 0xe618 43 #define PLA_RSTTALLY 0xe800 44 #define BIST_CTRL 0xe810 45 #define PLA_CR 0xe813 46 #define PLA_CRWECR 0xe81c 47 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 48 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 49 #define PLA_CONFIG5 0xe822 50 #define PLA_PHY_PWR 0xe84c 51 #define PLA_OOB_CTRL 0xe84f 52 #define PLA_CPCR 0xe854 53 #define PLA_MISC_0 0xe858 54 #define PLA_MISC_1 0xe85a 55 #define PLA_OCP_GPHY_BASE 0xe86c 56 #define PLA_TALLYCNT 0xe890 57 #define PLA_SFF_STS_7 0xe8de 58 #define PLA_PHYSTATUS 0xe908 59 #define PLA_BP_BA 0xfc26 60 #define PLA_BP_0 0xfc28 61 #define PLA_BP_1 0xfc2a 62 #define PLA_BP_2 0xfc2c 63 #define PLA_BP_3 0xfc2e 64 #define PLA_BP_4 0xfc30 65 #define PLA_BP_5 0xfc32 66 #define PLA_BP_6 0xfc34 67 #define PLA_BP_7 0xfc36 68 #define PLA_BP_EN 0xfc38 69 70 #define USB_USB2PHY 0xb41e 71 #define USB_SSPHYLINK2 0xb428 72 #define USB_U2P3_CTRL 0xb460 73 #define USB_CSR_DUMMY1 0xb464 74 #define USB_CSR_DUMMY2 0xb466 75 #define USB_DEV_STAT 0xb808 76 #define USB_CONNECT_TIMER 0xcbf8 77 #define USB_BURST_SIZE 0xcfc0 78 #define USB_USB_CTRL 0xd406 79 #define USB_PHY_CTRL 0xd408 80 #define USB_TX_AGG 0xd40a 81 #define USB_RX_BUF_TH 0xd40c 82 #define USB_USB_TIMER 0xd428 83 #define USB_RX_EARLY_TIMEOUT 0xd42c 84 #define USB_RX_EARLY_SIZE 0xd42e 85 #define USB_PM_CTRL_STATUS 0xd432 86 #define USB_TX_DMA 0xd434 87 #define USB_TOLERANCE 0xd490 88 #define USB_LPM_CTRL 0xd41a 89 #define USB_UPS_CTRL 0xd800 90 #define USB_MISC_0 0xd81a 91 #define USB_POWER_CUT 0xd80a 92 #define USB_AFE_CTRL2 0xd824 93 #define USB_WDT11_CTRL 0xe43c 94 #define USB_BP_BA 0xfc26 95 #define USB_BP_0 0xfc28 96 #define USB_BP_1 0xfc2a 97 #define USB_BP_2 0xfc2c 98 #define USB_BP_3 0xfc2e 99 #define USB_BP_4 0xfc30 100 #define USB_BP_5 0xfc32 101 #define USB_BP_6 0xfc34 102 #define USB_BP_7 0xfc36 103 #define USB_BP_EN 0xfc38 104 105 /* OCP Registers */ 106 #define OCP_ALDPS_CONFIG 0x2010 107 #define OCP_EEE_CONFIG1 0x2080 108 #define OCP_EEE_CONFIG2 0x2092 109 #define OCP_EEE_CONFIG3 0x2094 110 #define OCP_BASE_MII 0xa400 111 #define OCP_EEE_AR 0xa41a 112 #define OCP_EEE_DATA 0xa41c 113 #define OCP_PHY_STATUS 0xa420 114 #define OCP_POWER_CFG 0xa430 115 #define OCP_EEE_CFG 0xa432 116 #define OCP_SRAM_ADDR 0xa436 117 #define OCP_SRAM_DATA 0xa438 118 #define OCP_DOWN_SPEED 0xa442 119 #define OCP_EEE_ABLE 0xa5c4 120 #define OCP_EEE_ADV 0xa5d0 121 #define OCP_EEE_LPABLE 0xa5d2 122 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 123 #define OCP_ADC_CFG 0xbc06 124 125 /* SRAM Register */ 126 #define SRAM_LPF_CFG 0x8012 127 #define SRAM_10M_AMP1 0x8080 128 #define SRAM_10M_AMP2 0x8082 129 #define SRAM_IMPEDANCE 0x8084 130 131 /* PLA_RCR */ 132 #define RCR_AAP 0x00000001 133 #define RCR_APM 0x00000002 134 #define RCR_AM 0x00000004 135 #define RCR_AB 0x00000008 136 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 137 138 /* PLA_RXFIFO_CTRL0 */ 139 #define RXFIFO_THR1_NORMAL 0x00080002 140 #define RXFIFO_THR1_OOB 0x01800003 141 142 /* PLA_RXFIFO_CTRL1 */ 143 #define RXFIFO_THR2_FULL 0x00000060 144 #define RXFIFO_THR2_HIGH 0x00000038 145 #define RXFIFO_THR2_OOB 0x0000004a 146 #define RXFIFO_THR2_NORMAL 0x00a0 147 148 /* PLA_RXFIFO_CTRL2 */ 149 #define RXFIFO_THR3_FULL 0x00000078 150 #define RXFIFO_THR3_HIGH 0x00000048 151 #define RXFIFO_THR3_OOB 0x0000005a 152 #define RXFIFO_THR3_NORMAL 0x0110 153 154 /* PLA_TXFIFO_CTRL */ 155 #define TXFIFO_THR_NORMAL 0x00400008 156 #define TXFIFO_THR_NORMAL2 0x01000008 157 158 /* PLA_DMY_REG0 */ 159 #define ECM_ALDPS 0x0002 160 161 /* PLA_FMC */ 162 #define FMC_FCR_MCU_EN 0x0001 163 164 /* PLA_EEEP_CR */ 165 #define EEEP_CR_EEEP_TX 0x0002 166 167 /* PLA_WDT6_CTRL */ 168 #define WDT6_SET_MODE 0x0010 169 170 /* PLA_TCR0 */ 171 #define TCR0_TX_EMPTY 0x0800 172 #define TCR0_AUTO_FIFO 0x0080 173 174 /* PLA_TCR1 */ 175 #define VERSION_MASK 0x7cf0 176 177 /* PLA_MTPS */ 178 #define MTPS_JUMBO (12 * 1024 / 64) 179 #define MTPS_DEFAULT (6 * 1024 / 64) 180 181 /* PLA_RSTTALLY */ 182 #define TALLY_RESET 0x0001 183 184 /* PLA_CR */ 185 #define PLA_CR_RST 0x10 186 #define PLA_CR_RE 0x08 187 #define PLA_CR_TE 0x04 188 189 /* PLA_BIST_CTRL */ 190 #define BIST_CTRL_SW_RESET (0x10 << 24) 191 192 /* PLA_CRWECR */ 193 #define CRWECR_NORAML 0x00 194 #define CRWECR_CONFIG 0xc0 195 196 /* PLA_OOB_CTRL */ 197 #define NOW_IS_OOB 0x80 198 #define TXFIFO_EMPTY 0x20 199 #define RXFIFO_EMPTY 0x10 200 #define LINK_LIST_READY 0x02 201 #define DIS_MCU_CLROOB 0x01 202 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 203 204 /* PLA_PHY_PWR */ 205 #define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24) 206 #define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24) 207 208 /* PLA_MISC_1 */ 209 #define RXDY_GATED_EN 0x0008 210 211 /* PLA_SFF_STS_7 */ 212 #define RE_INIT_LL 0x8000 213 #define MCU_BORW_EN 0x4000 214 215 /* PLA_CPCR */ 216 #define CPCR_RX_VLAN 0x0040 217 218 /* PLA_CFG_WOL */ 219 #define MAGIC_EN 0x0001 220 221 /* PLA_TEREDO_CFG */ 222 #define TEREDO_SEL 0x8000 223 #define TEREDO_WAKE_MASK 0x7f00 224 #define TEREDO_RS_EVENT_MASK 0x00fe 225 #define OOB_TEREDO_EN 0x0001 226 227 /* PAL_BDC_CR */ 228 #define ALDPS_PROXY_MODE 0x0001 229 230 /* PLA_CONFIG34 */ 231 #define LINK_ON_WAKE_EN 0x0010 232 #define LINK_OFF_WAKE_EN 0x0008 233 234 /* PLA_CONFIG5 */ 235 #define BWF_EN 0x0040 236 #define MWF_EN 0x0020 237 #define UWF_EN 0x0010 238 #define LAN_WAKE_EN 0x0002 239 240 /* PLA_LED_FEATURE */ 241 #define LED_MODE_MASK 0x0700 242 243 /* PLA_PHY_PWR */ 244 #define TX_10M_IDLE_EN 0x0080 245 #define PFM_PWM_SWITCH 0x0040 246 247 /* PLA_MAC_PWR_CTRL */ 248 #define D3_CLK_GATED_EN 0x00004000 249 #define MCU_CLK_RATIO 0x07010f07 250 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 251 #define ALDPS_SPDWN_RATIO 0x0f87 252 253 /* PLA_MAC_PWR_CTRL2 */ 254 #define EEE_SPDWN_RATIO 0x8007 255 256 /* PLA_MAC_PWR_CTRL3 */ 257 #define PKT_AVAIL_SPDWN_EN 0x0100 258 #define SUSPEND_SPDWN_EN 0x0004 259 #define U1U2_SPDWN_EN 0x0002 260 #define L1_SPDWN_EN 0x0001 261 262 /* PLA_MAC_PWR_CTRL4 */ 263 #define PWRSAVE_SPDWN_EN 0x1000 264 #define RXDV_SPDWN_EN 0x0800 265 #define TX10MIDLE_EN 0x0100 266 #define TP100_SPDWN_EN 0x0020 267 #define TP500_SPDWN_EN 0x0010 268 #define TP1000_SPDWN_EN 0x0008 269 #define EEE_SPDWN_EN 0x0001 270 271 /* PLA_GPHY_INTR_IMR */ 272 #define GPHY_STS_MSK 0x0001 273 #define SPEED_DOWN_MSK 0x0002 274 #define SPDWN_RXDV_MSK 0x0004 275 #define SPDWN_LINKCHG_MSK 0x0008 276 277 /* PLA_PHYAR */ 278 #define PHYAR_FLAG 0x80000000 279 280 /* PLA_EEE_CR */ 281 #define EEE_RX_EN 0x0001 282 #define EEE_TX_EN 0x0002 283 284 /* PLA_BOOT_CTRL */ 285 #define AUTOLOAD_DONE 0x0002 286 287 /* USB_USB2PHY */ 288 #define USB2PHY_SUSPEND 0x0001 289 #define USB2PHY_L1 0x0002 290 291 /* USB_SSPHYLINK2 */ 292 #define pwd_dn_scale_mask 0x3ffe 293 #define pwd_dn_scale(x) ((x) << 1) 294 295 /* USB_CSR_DUMMY1 */ 296 #define DYNAMIC_BURST 0x0001 297 298 /* USB_CSR_DUMMY2 */ 299 #define EP4_FULL_FC 0x0001 300 301 /* USB_DEV_STAT */ 302 #define STAT_SPEED_MASK 0x0006 303 #define STAT_SPEED_HIGH 0x0000 304 #define STAT_SPEED_FULL 0x0002 305 306 /* USB_TX_AGG */ 307 #define TX_AGG_MAX_THRESHOLD 0x03 308 309 /* USB_RX_BUF_TH */ 310 #define RX_THR_SUPPER 0x0c350180 311 #define RX_THR_HIGH 0x7a120180 312 #define RX_THR_SLOW 0xffff0180 313 314 /* USB_TX_DMA */ 315 #define TEST_MODE_DISABLE 0x00000001 316 #define TX_SIZE_ADJUST1 0x00000100 317 318 /* USB_UPS_CTRL */ 319 #define POWER_CUT 0x0100 320 321 /* USB_PM_CTRL_STATUS */ 322 #define RESUME_INDICATE 0x0001 323 324 /* USB_USB_CTRL */ 325 #define RX_AGG_DISABLE 0x0010 326 #define RX_ZERO_EN 0x0080 327 328 /* USB_U2P3_CTRL */ 329 #define U2P3_ENABLE 0x0001 330 331 /* USB_POWER_CUT */ 332 #define PWR_EN 0x0001 333 #define PHASE2_EN 0x0008 334 335 /* USB_MISC_0 */ 336 #define PCUT_STATUS 0x0001 337 338 /* USB_RX_EARLY_TIMEOUT */ 339 #define COALESCE_SUPER 85000U 340 #define COALESCE_HIGH 250000U 341 #define COALESCE_SLOW 524280U 342 343 /* USB_WDT11_CTRL */ 344 #define TIMER11_EN 0x0001 345 346 /* USB_LPM_CTRL */ 347 /* bit 4 ~ 5: fifo empty boundary */ 348 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 349 /* bit 2 ~ 3: LMP timer */ 350 #define LPM_TIMER_MASK 0x0c 351 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 352 #define LPM_TIMER_500US 0x0c /* 500 us */ 353 #define ROK_EXIT_LPM 0x02 354 355 /* USB_AFE_CTRL2 */ 356 #define SEN_VAL_MASK 0xf800 357 #define SEN_VAL_NORMAL 0xa000 358 #define SEL_RXIDLE 0x0100 359 360 /* OCP_ALDPS_CONFIG */ 361 #define ENPWRSAVE 0x8000 362 #define ENPDNPS 0x0200 363 #define LINKENA 0x0100 364 #define DIS_SDSAVE 0x0010 365 366 /* OCP_PHY_STATUS */ 367 #define PHY_STAT_MASK 0x0007 368 #define PHY_STAT_LAN_ON 3 369 #define PHY_STAT_PWRDN 5 370 371 /* OCP_POWER_CFG */ 372 #define EEE_CLKDIV_EN 0x8000 373 #define EN_ALDPS 0x0004 374 #define EN_10M_PLLOFF 0x0001 375 376 /* OCP_EEE_CONFIG1 */ 377 #define RG_TXLPI_MSK_HFDUP 0x8000 378 #define RG_MATCLR_EN 0x4000 379 #define EEE_10_CAP 0x2000 380 #define EEE_NWAY_EN 0x1000 381 #define TX_QUIET_EN 0x0200 382 #define RX_QUIET_EN 0x0100 383 #define sd_rise_time_mask 0x0070 384 #define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */ 385 #define RG_RXLPI_MSK_HFDUP 0x0008 386 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 387 388 /* OCP_EEE_CONFIG2 */ 389 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 390 #define RG_DACQUIET_EN 0x0400 391 #define RG_LDVQUIET_EN 0x0200 392 #define RG_CKRSEL 0x0020 393 #define RG_EEEPRG_EN 0x0010 394 395 /* OCP_EEE_CONFIG3 */ 396 #define fast_snr_mask 0xff80 397 #define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */ 398 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 399 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 400 401 /* OCP_EEE_AR */ 402 /* bit[15:14] function */ 403 #define FUN_ADDR 0x0000 404 #define FUN_DATA 0x4000 405 /* bit[4:0] device addr */ 406 407 /* OCP_EEE_CFG */ 408 #define CTAP_SHORT_EN 0x0040 409 #define EEE10_EN 0x0010 410 411 /* OCP_DOWN_SPEED */ 412 #define EN_10M_BGOFF 0x0080 413 414 /* OCP_PHY_STATE */ 415 #define TXDIS_STATE 0x01 416 #define ABD_STATE 0x02 417 418 /* OCP_ADC_CFG */ 419 #define CKADSEL_L 0x0100 420 #define ADC_EN 0x0080 421 #define EN_EMI_L 0x0040 422 423 /* SRAM_LPF_CFG */ 424 #define LPF_AUTO_TUNE 0x8000 425 426 /* SRAM_10M_AMP1 */ 427 #define GDAC_IB_UPALL 0x0008 428 429 /* SRAM_10M_AMP2 */ 430 #define AMP_DN 0x0200 431 432 /* SRAM_IMPEDANCE */ 433 #define RX_DRIVING_MASK 0x6000 434 435 #define RTL8152_MAX_TX 4 436 #define RTL8152_MAX_RX 10 437 #define INTBUFSIZE 2 438 #define CRC_SIZE 4 439 #define TX_ALIGN 4 440 #define RX_ALIGN 8 441 442 #define INTR_LINK 0x0004 443 444 #define RTL8152_REQT_READ 0xc0 445 #define RTL8152_REQT_WRITE 0x40 446 #define RTL8152_REQ_GET_REGS 0x05 447 #define RTL8152_REQ_SET_REGS 0x05 448 449 #define BYTE_EN_DWORD 0xff 450 #define BYTE_EN_WORD 0x33 451 #define BYTE_EN_BYTE 0x11 452 #define BYTE_EN_SIX_BYTES 0x3f 453 #define BYTE_EN_START_MASK 0x0f 454 #define BYTE_EN_END_MASK 0xf0 455 456 #define RTL8152_ETH_FRAME_LEN 1514 457 #define RTL8152_AGG_BUF_SZ 2048 458 459 #define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE) 460 #define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE) 461 #define RTL8152_TX_TIMEOUT (5 * HZ) 462 463 #define MCU_TYPE_PLA 0x0100 464 #define MCU_TYPE_USB 0x0000 465 466 /* The forced speed, 10Mb, 100Mb, gigabit. */ 467 #define SPEED_10 10 468 #define SPEED_100 100 469 #define SPEED_1000 1000 470 471 #define SPEED_UNKNOWN -1 472 473 /* Duplex, half or full. */ 474 #define DUPLEX_HALF 0x00 475 #define DUPLEX_FULL 0x01 476 #define DUPLEX_UNKNOWN 0xff 477 478 /* Enable or disable autonegotiation. */ 479 #define AUTONEG_DISABLE 0x00 480 #define AUTONEG_ENABLE 0x01 481 482 /* Generic MII registers. */ 483 #define MII_BMCR 0x00 /* Basic mode control register */ 484 #define MII_BMSR 0x01 /* Basic mode status register */ 485 #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 486 #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 487 #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 488 #define MII_LPA 0x05 /* Link partner ability reg */ 489 #define MII_EXPANSION 0x06 /* Expansion register */ 490 #define MII_CTRL1000 0x09 /* 1000BASE-T control */ 491 #define MII_STAT1000 0x0a /* 1000BASE-T status */ 492 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 493 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 494 #define MII_ESTATUS 0x0f /* Extended Status */ 495 #define MII_DCOUNTER 0x12 /* Disconnect counter */ 496 #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 497 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 498 #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 499 #define MII_SREVISION 0x16 /* Silicon revision */ 500 #define MII_RESV1 0x17 /* Reserved... */ 501 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 502 #define MII_PHYADDR 0x19 /* PHY address */ 503 #define MII_RESV2 0x1a /* Reserved... */ 504 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 505 #define MII_NCONFIG 0x1c /* Network interface config */ 506 507 #define TIMEOUT_RESOLUTION 50 508 #define PHY_CONNECT_TIMEOUT 5000 509 #define USB_BULK_SEND_TIMEOUT 5000 510 #define USB_BULK_RECV_TIMEOUT 5000 511 #define R8152_WAIT_TIMEOUT 2000 512 513 struct rx_desc { 514 __le32 opts1; 515 #define RD_CRC BIT(15) 516 #define RX_LEN_MASK 0x7fff 517 518 __le32 opts2; 519 #define RD_UDP_CS BIT(23) 520 #define RD_TCP_CS BIT(22) 521 #define RD_IPV6_CS BIT(20) 522 #define RD_IPV4_CS BIT(19) 523 524 __le32 opts3; 525 #define IPF BIT(23) /* IP checksum fail */ 526 #define UDPF BIT(22) /* UDP checksum fail */ 527 #define TCPF BIT(21) /* TCP checksum fail */ 528 #define RX_VLAN_TAG BIT(16) 529 530 __le32 opts4; 531 __le32 opts5; 532 __le32 opts6; 533 }; 534 535 struct tx_desc { 536 __le32 opts1; 537 #define TX_FS BIT(31) /* First segment of a packet */ 538 #define TX_LS BIT(30) /* Final segment of a packet */ 539 #define LGSEND BIT(29) 540 #define GTSENDV4 BIT(28) 541 #define GTSENDV6 BIT(27) 542 #define GTTCPHO_SHIFT 18 543 #define GTTCPHO_MAX 0x7fU 544 #define TX_LEN_MAX 0x3ffffU 545 546 __le32 opts2; 547 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 548 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 549 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 550 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 551 #define MSS_SHIFT 17 552 #define MSS_MAX 0x7ffU 553 #define TCPHO_SHIFT 17 554 #define TCPHO_MAX 0x7ffU 555 #define TX_VLAN_TAG BIT(16) 556 }; 557 558 enum rtl_version { 559 RTL_VER_UNKNOWN = 0, 560 RTL_VER_01, 561 RTL_VER_02, 562 RTL_VER_03, 563 RTL_VER_04, 564 RTL_VER_05, 565 RTL_VER_06, 566 RTL_VER_07, 567 RTL_VER_MAX 568 }; 569 570 enum rtl_register_content { 571 _1000bps = 0x10, 572 _100bps = 0x08, 573 _10bps = 0x04, 574 LINK_STATUS = 0x02, 575 FULL_DUP = 0x01, 576 }; 577 578 struct r8152 { 579 struct usb_device *udev; 580 struct usb_interface *intf; 581 bool supports_gmii; 582 583 struct rtl_ops { 584 void (*init)(struct r8152 *); 585 int (*enable)(struct r8152 *); 586 void (*disable)(struct r8152 *); 587 void (*up)(struct r8152 *); 588 void (*down)(struct r8152 *); 589 void (*unload)(struct r8152 *); 590 } rtl_ops; 591 592 u32 coalesce; 593 u16 ocp_base; 594 595 u8 version; 596 597 #ifdef CONFIG_DM_ETH 598 struct ueth_data ueth; 599 #endif 600 }; 601 602 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 603 u16 size, void *data, u16 type); 604 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 605 void *data, u16 type); 606 607 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data); 608 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 609 u16 size, void *data); 610 611 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data); 612 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 613 u16 size, void *data); 614 615 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index); 616 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data); 617 618 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index); 619 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data); 620 621 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index); 622 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data); 623 624 u16 ocp_reg_read(struct r8152 *tp, u16 addr); 625 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data); 626 627 void sram_write(struct r8152 *tp, u16 addr, u16 data); 628 629 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index, 630 const u32 mask, bool set, unsigned int timeout); 631 632 void r8152b_firmware(struct r8152 *tp); 633 void r8153_firmware(struct r8152 *tp); 634 #endif 635