1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. 4 * 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <memalign.h> 12 #include <usb.h> 13 #include <linux/mii.h> 14 #include <linux/bitops.h> 15 #include "usb_ether.h" 16 #include "r8152.h" 17 18 #ifndef CONFIG_DM_ETH 19 /* local vars */ 20 static int curr_eth_dev; /* index for name of next device detected */ 21 22 struct r8152_dongle { 23 unsigned short vendor; 24 unsigned short product; 25 }; 26 27 static const struct r8152_dongle r8152_dongles[] = { 28 /* Realtek */ 29 { 0x0bda, 0x8050 }, 30 { 0x0bda, 0x8152 }, 31 { 0x0bda, 0x8153 }, 32 33 /* Samsung */ 34 { 0x04e8, 0xa101 }, 35 36 /* Lenovo */ 37 { 0x17ef, 0x304f }, 38 { 0x17ef, 0x3052 }, 39 { 0x17ef, 0x3054 }, 40 { 0x17ef, 0x3057 }, 41 { 0x17ef, 0x7205 }, 42 { 0x17ef, 0x720a }, 43 { 0x17ef, 0x720b }, 44 { 0x17ef, 0x720c }, 45 46 /* TP-LINK */ 47 { 0x2357, 0x0601 }, 48 49 /* Nvidia */ 50 { 0x0955, 0x09ff }, 51 }; 52 #endif 53 54 struct r8152_version { 55 unsigned short tcr; 56 unsigned short version; 57 bool gmii; 58 }; 59 60 static const struct r8152_version r8152_versions[] = { 61 { 0x4c00, RTL_VER_01, 0 }, 62 { 0x4c10, RTL_VER_02, 0 }, 63 { 0x5c00, RTL_VER_03, 1 }, 64 { 0x5c10, RTL_VER_04, 1 }, 65 { 0x5c20, RTL_VER_05, 1 }, 66 { 0x5c30, RTL_VER_06, 1 }, 67 { 0x4800, RTL_VER_07, 0 }, 68 }; 69 70 static 71 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 72 { 73 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size); 74 int ret; 75 76 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 77 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 78 value, index, tmp, size, 500); 79 memcpy(data, tmp, size); 80 return ret; 81 } 82 83 static 84 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 85 { 86 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size); 87 88 memcpy(tmp, data, size); 89 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 90 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 91 value, index, tmp, size, 500); 92 } 93 94 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 95 void *data, u16 type) 96 { 97 u16 burst_size = 64; 98 int ret; 99 int txsize; 100 101 /* both size and index must be 4 bytes align */ 102 if ((size & 3) || !size || (index & 3) || !data) 103 return -EINVAL; 104 105 if (index + size > 0xffff) 106 return -EINVAL; 107 108 while (size) { 109 txsize = min(size, burst_size); 110 ret = get_registers(tp, index, type, txsize, data); 111 if (ret < 0) 112 break; 113 114 index += txsize; 115 data += txsize; 116 size -= txsize; 117 } 118 119 return ret; 120 } 121 122 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 123 u16 size, void *data, u16 type) 124 { 125 int ret; 126 u16 byteen_start, byteen_end, byte_en_to_hw; 127 u16 burst_size = 512; 128 int txsize; 129 130 /* both size and index must be 4 bytes align */ 131 if ((size & 3) || !size || (index & 3) || !data) 132 return -EINVAL; 133 134 if (index + size > 0xffff) 135 return -EINVAL; 136 137 byteen_start = byteen & BYTE_EN_START_MASK; 138 byteen_end = byteen & BYTE_EN_END_MASK; 139 140 byte_en_to_hw = byteen_start | (byteen_start << 4); 141 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data); 142 if (ret < 0) 143 return ret; 144 145 index += 4; 146 data += 4; 147 size -= 4; 148 149 if (size) { 150 size -= 4; 151 152 while (size) { 153 txsize = min(size, burst_size); 154 155 ret = set_registers(tp, index, 156 type | BYTE_EN_DWORD, 157 txsize, data); 158 if (ret < 0) 159 return ret; 160 161 index += txsize; 162 data += txsize; 163 size -= txsize; 164 } 165 166 byte_en_to_hw = byteen_end | (byteen_end >> 4); 167 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data); 168 if (ret < 0) 169 return ret; 170 } 171 172 return ret; 173 } 174 175 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 176 { 177 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 178 } 179 180 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 181 { 182 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 183 } 184 185 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 186 { 187 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 188 } 189 190 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 191 { 192 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 193 } 194 195 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 196 { 197 __le32 data; 198 199 generic_ocp_read(tp, index, sizeof(data), &data, type); 200 201 return __le32_to_cpu(data); 202 } 203 204 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 205 { 206 __le32 tmp = __cpu_to_le32(data); 207 208 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 209 } 210 211 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 212 { 213 u32 data; 214 __le32 tmp; 215 u8 shift = index & 2; 216 217 index &= ~3; 218 219 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 220 221 data = __le32_to_cpu(tmp); 222 data >>= (shift * 8); 223 data &= 0xffff; 224 225 return data; 226 } 227 228 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 229 { 230 u32 mask = 0xffff; 231 __le32 tmp; 232 u16 byen = BYTE_EN_WORD; 233 u8 shift = index & 2; 234 235 data &= mask; 236 237 if (index & 2) { 238 byen <<= shift; 239 mask <<= (shift * 8); 240 data <<= (shift * 8); 241 index &= ~3; 242 } 243 244 tmp = __cpu_to_le32(data); 245 246 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 247 } 248 249 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 250 { 251 u32 data; 252 __le32 tmp; 253 u8 shift = index & 3; 254 255 index &= ~3; 256 257 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 258 259 data = __le32_to_cpu(tmp); 260 data >>= (shift * 8); 261 data &= 0xff; 262 263 return data; 264 } 265 266 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 267 { 268 u32 mask = 0xff; 269 __le32 tmp; 270 u16 byen = BYTE_EN_BYTE; 271 u8 shift = index & 3; 272 273 data &= mask; 274 275 if (index & 3) { 276 byen <<= shift; 277 mask <<= (shift * 8); 278 data <<= (shift * 8); 279 index &= ~3; 280 } 281 282 tmp = __cpu_to_le32(data); 283 284 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 285 } 286 287 u16 ocp_reg_read(struct r8152 *tp, u16 addr) 288 { 289 u16 ocp_base, ocp_index; 290 291 ocp_base = addr & 0xf000; 292 if (ocp_base != tp->ocp_base) { 293 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 294 tp->ocp_base = ocp_base; 295 } 296 297 ocp_index = (addr & 0x0fff) | 0xb000; 298 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 299 } 300 301 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 302 { 303 u16 ocp_base, ocp_index; 304 305 ocp_base = addr & 0xf000; 306 if (ocp_base != tp->ocp_base) { 307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 308 tp->ocp_base = ocp_base; 309 } 310 311 ocp_index = (addr & 0x0fff) | 0xb000; 312 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 313 } 314 315 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 316 { 317 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 318 } 319 320 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 321 { 322 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 323 } 324 325 void sram_write(struct r8152 *tp, u16 addr, u16 data) 326 { 327 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 328 ocp_reg_write(tp, OCP_SRAM_DATA, data); 329 } 330 331 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index, 332 const u32 mask, bool set, unsigned int timeout) 333 { 334 u32 val; 335 336 while (--timeout) { 337 if (ocp_reg) 338 val = ocp_reg_read(tp, index); 339 else 340 val = ocp_read_dword(tp, type, index); 341 342 if (!set) 343 val = ~val; 344 345 if ((val & mask) == mask) 346 return 0; 347 348 mdelay(1); 349 } 350 351 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n", 352 __func__, index, mask, timeout); 353 354 return -ETIMEDOUT; 355 } 356 357 static void r8152b_reset_packet_filter(struct r8152 *tp) 358 { 359 u32 ocp_data; 360 361 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 362 ocp_data &= ~FMC_FCR_MCU_EN; 363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 364 ocp_data |= FMC_FCR_MCU_EN; 365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 366 } 367 368 static void rtl8152_wait_fifo_empty(struct r8152 *tp) 369 { 370 int ret; 371 372 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 373 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT); 374 if (ret) 375 debug("Timeout waiting for FIFO empty\n"); 376 377 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0, 378 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT); 379 if (ret) 380 debug("Timeout waiting for TX empty\n"); 381 } 382 383 static void rtl8152_nic_reset(struct r8152 *tp) 384 { 385 int ret; 386 u32 ocp_data; 387 388 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL); 389 ocp_data |= BIST_CTRL_SW_RESET; 390 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data); 391 392 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL, 393 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT); 394 if (ret) 395 debug("Timeout waiting for NIC reset\n"); 396 } 397 398 static u8 rtl8152_get_speed(struct r8152 *tp) 399 { 400 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 401 } 402 403 static void rtl_set_eee_plus(struct r8152 *tp) 404 { 405 u32 ocp_data; 406 407 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 408 ocp_data &= ~EEEP_CR_EEEP_TX; 409 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 410 } 411 412 static void rxdy_gated_en(struct r8152 *tp, bool enable) 413 { 414 u32 ocp_data; 415 416 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 417 if (enable) 418 ocp_data |= RXDY_GATED_EN; 419 else 420 ocp_data &= ~RXDY_GATED_EN; 421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 422 } 423 424 static void rtl8152_set_rx_mode(struct r8152 *tp) 425 { 426 u32 ocp_data; 427 __le32 tmp[2]; 428 429 tmp[0] = 0xffffffff; 430 tmp[1] = 0xffffffff; 431 432 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 433 434 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 435 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 436 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 437 } 438 439 static int rtl_enable(struct r8152 *tp) 440 { 441 u32 ocp_data; 442 443 r8152b_reset_packet_filter(tp); 444 445 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 446 ocp_data |= PLA_CR_RE | PLA_CR_TE; 447 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 448 449 rxdy_gated_en(tp, false); 450 451 rtl8152_set_rx_mode(tp); 452 453 return 0; 454 } 455 456 static int rtl8152_enable(struct r8152 *tp) 457 { 458 rtl_set_eee_plus(tp); 459 460 return rtl_enable(tp); 461 } 462 463 static void r8153_set_rx_early_timeout(struct r8152 *tp) 464 { 465 u32 ocp_data = tp->coalesce / 8; 466 467 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); 468 } 469 470 static void r8153_set_rx_early_size(struct r8152 *tp) 471 { 472 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4; 473 474 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); 475 } 476 477 static int rtl8153_enable(struct r8152 *tp) 478 { 479 rtl_set_eee_plus(tp); 480 r8153_set_rx_early_timeout(tp); 481 r8153_set_rx_early_size(tp); 482 483 return rtl_enable(tp); 484 } 485 486 static void rtl_disable(struct r8152 *tp) 487 { 488 u32 ocp_data; 489 490 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 491 ocp_data &= ~RCR_ACPT_ALL; 492 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 493 494 rxdy_gated_en(tp, true); 495 496 rtl8152_wait_fifo_empty(tp); 497 rtl8152_nic_reset(tp); 498 } 499 500 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 501 { 502 u32 ocp_data; 503 504 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 505 if (enable) 506 ocp_data |= POWER_CUT; 507 else 508 ocp_data &= ~POWER_CUT; 509 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 510 511 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 512 ocp_data &= ~RESUME_INDICATE; 513 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 514 } 515 516 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 517 { 518 u32 ocp_data; 519 520 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 521 if (enable) 522 ocp_data |= CPCR_RX_VLAN; 523 else 524 ocp_data &= ~CPCR_RX_VLAN; 525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 526 } 527 528 static void r8153_u1u2en(struct r8152 *tp, bool enable) 529 { 530 u8 u1u2[8]; 531 532 if (enable) 533 memset(u1u2, 0xff, sizeof(u1u2)); 534 else 535 memset(u1u2, 0x00, sizeof(u1u2)); 536 537 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 538 } 539 540 static void r8153_u2p3en(struct r8152 *tp, bool enable) 541 { 542 u32 ocp_data; 543 544 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 545 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 546 ocp_data |= U2P3_ENABLE; 547 else 548 ocp_data &= ~U2P3_ENABLE; 549 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 550 } 551 552 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 553 { 554 u32 ocp_data; 555 556 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 557 if (enable) 558 ocp_data |= PWR_EN | PHASE2_EN; 559 else 560 ocp_data &= ~(PWR_EN | PHASE2_EN); 561 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 562 563 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 564 ocp_data &= ~PCUT_STATUS; 565 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 566 } 567 568 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr) 569 { 570 int ret; 571 unsigned char enetaddr[8] = {0}; 572 573 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr); 574 if (ret < 0) 575 return ret; 576 577 memcpy(macaddr, enetaddr, ETH_ALEN); 578 return 0; 579 } 580 581 static void r8152b_disable_aldps(struct r8152 *tp) 582 { 583 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 584 mdelay(20); 585 } 586 587 static void r8152b_enable_aldps(struct r8152 *tp) 588 { 589 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 590 LINKENA | DIS_SDSAVE); 591 } 592 593 static void rtl8152_disable(struct r8152 *tp) 594 { 595 r8152b_disable_aldps(tp); 596 rtl_disable(tp); 597 r8152b_enable_aldps(tp); 598 } 599 600 static void r8152b_hw_phy_cfg(struct r8152 *tp) 601 { 602 u16 data; 603 604 data = r8152_mdio_read(tp, MII_BMCR); 605 if (data & BMCR_PDOWN) { 606 data &= ~BMCR_PDOWN; 607 r8152_mdio_write(tp, MII_BMCR, data); 608 } 609 610 r8152b_firmware(tp); 611 } 612 613 static void rtl8152_reinit_ll(struct r8152 *tp) 614 { 615 u32 ocp_data; 616 int ret; 617 618 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 619 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); 620 if (ret) 621 debug("Timeout waiting for link list ready\n"); 622 623 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 624 ocp_data |= RE_INIT_LL; 625 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 626 627 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 628 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); 629 if (ret) 630 debug("Timeout waiting for link list ready\n"); 631 } 632 633 static void r8152b_exit_oob(struct r8152 *tp) 634 { 635 u32 ocp_data; 636 637 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 638 ocp_data &= ~RCR_ACPT_ALL; 639 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 640 641 rxdy_gated_en(tp, true); 642 r8152b_hw_phy_cfg(tp); 643 644 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 645 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 646 647 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 648 ocp_data &= ~NOW_IS_OOB; 649 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 650 651 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 652 ocp_data &= ~MCU_BORW_EN; 653 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 654 655 rtl8152_reinit_ll(tp); 656 rtl8152_nic_reset(tp); 657 658 /* rx share fifo credit full threshold */ 659 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 660 661 if (tp->udev->speed == USB_SPEED_FULL || 662 tp->udev->speed == USB_SPEED_LOW) { 663 /* rx share fifo credit near full threshold */ 664 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 665 RXFIFO_THR2_FULL); 666 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 667 RXFIFO_THR3_FULL); 668 } else { 669 /* rx share fifo credit near full threshold */ 670 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 671 RXFIFO_THR2_HIGH); 672 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 673 RXFIFO_THR3_HIGH); 674 } 675 676 /* TX share fifo free credit full threshold */ 677 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 678 679 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 680 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 681 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 682 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 683 684 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 685 686 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 687 ocp_data |= TCR0_AUTO_FIFO; 688 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 689 } 690 691 static void r8152b_enter_oob(struct r8152 *tp) 692 { 693 u32 ocp_data; 694 695 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 696 ocp_data &= ~NOW_IS_OOB; 697 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 698 699 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 700 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 702 703 rtl_disable(tp); 704 705 rtl8152_reinit_ll(tp); 706 707 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 708 709 rtl_rx_vlan_en(tp, false); 710 711 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 712 ocp_data |= ALDPS_PROXY_MODE; 713 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 714 715 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 716 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 717 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 718 719 rxdy_gated_en(tp, false); 720 721 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 722 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 723 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 724 } 725 726 static void r8153_hw_phy_cfg(struct r8152 *tp) 727 { 728 u32 ocp_data; 729 u16 data; 730 731 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 732 tp->version == RTL_VER_05) 733 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 734 735 data = r8152_mdio_read(tp, MII_BMCR); 736 if (data & BMCR_PDOWN) { 737 data &= ~BMCR_PDOWN; 738 r8152_mdio_write(tp, MII_BMCR, data); 739 } 740 741 r8153_firmware(tp); 742 743 if (tp->version == RTL_VER_03) { 744 data = ocp_reg_read(tp, OCP_EEE_CFG); 745 data &= ~CTAP_SHORT_EN; 746 ocp_reg_write(tp, OCP_EEE_CFG, data); 747 } 748 749 data = ocp_reg_read(tp, OCP_POWER_CFG); 750 data |= EEE_CLKDIV_EN; 751 ocp_reg_write(tp, OCP_POWER_CFG, data); 752 753 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 754 data |= EN_10M_BGOFF; 755 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 756 data = ocp_reg_read(tp, OCP_POWER_CFG); 757 data |= EN_10M_PLLOFF; 758 ocp_reg_write(tp, OCP_POWER_CFG, data); 759 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 760 761 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 762 ocp_data |= PFM_PWM_SWITCH; 763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 764 765 /* Enable LPF corner auto tune */ 766 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 767 768 /* Adjust 10M Amplitude */ 769 sram_write(tp, SRAM_10M_AMP1, 0x00af); 770 sram_write(tp, SRAM_10M_AMP2, 0x0208); 771 } 772 773 static void r8153_first_init(struct r8152 *tp) 774 { 775 u32 ocp_data; 776 777 rxdy_gated_en(tp, true); 778 779 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 780 ocp_data &= ~RCR_ACPT_ALL; 781 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 782 783 r8153_hw_phy_cfg(tp); 784 785 rtl8152_nic_reset(tp); 786 787 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 788 ocp_data &= ~NOW_IS_OOB; 789 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 790 791 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 792 ocp_data &= ~MCU_BORW_EN; 793 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 794 795 rtl8152_reinit_ll(tp); 796 797 rtl_rx_vlan_en(tp, false); 798 799 ocp_data = RTL8153_RMS; 800 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 801 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 802 803 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 804 ocp_data |= TCR0_AUTO_FIFO; 805 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 806 807 rtl8152_nic_reset(tp); 808 809 /* rx share fifo credit full threshold */ 810 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 811 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 812 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 813 /* TX share fifo free credit full threshold */ 814 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 815 816 /* rx aggregation */ 817 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 818 819 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 820 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 821 } 822 823 static void r8153_enter_oob(struct r8152 *tp) 824 { 825 u32 ocp_data; 826 827 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 828 ocp_data &= ~NOW_IS_OOB; 829 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 830 831 rtl_disable(tp); 832 833 rtl8152_reinit_ll(tp); 834 835 ocp_data = RTL8153_RMS; 836 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 837 838 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 839 ocp_data &= ~TEREDO_WAKE_MASK; 840 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 841 842 rtl_rx_vlan_en(tp, false); 843 844 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 845 ocp_data |= ALDPS_PROXY_MODE; 846 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 847 848 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 849 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 850 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 851 852 rxdy_gated_en(tp, false); 853 854 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 855 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 856 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 857 } 858 859 static void r8153_disable_aldps(struct r8152 *tp) 860 { 861 u16 data; 862 863 data = ocp_reg_read(tp, OCP_POWER_CFG); 864 data &= ~EN_ALDPS; 865 ocp_reg_write(tp, OCP_POWER_CFG, data); 866 mdelay(20); 867 } 868 869 static void rtl8153_disable(struct r8152 *tp) 870 { 871 r8153_disable_aldps(tp); 872 rtl_disable(tp); 873 } 874 875 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 876 { 877 u16 bmcr, anar, gbcr; 878 879 anar = r8152_mdio_read(tp, MII_ADVERTISE); 880 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 881 ADVERTISE_100HALF | ADVERTISE_100FULL); 882 if (tp->supports_gmii) { 883 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 884 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 885 } else { 886 gbcr = 0; 887 } 888 889 if (autoneg == AUTONEG_DISABLE) { 890 if (speed == SPEED_10) { 891 bmcr = 0; 892 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 893 } else if (speed == SPEED_100) { 894 bmcr = BMCR_SPEED100; 895 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 896 } else if (speed == SPEED_1000 && tp->supports_gmii) { 897 bmcr = BMCR_SPEED1000; 898 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 899 } else { 900 return -EINVAL; 901 } 902 903 if (duplex == DUPLEX_FULL) 904 bmcr |= BMCR_FULLDPLX; 905 } else { 906 if (speed == SPEED_10) { 907 if (duplex == DUPLEX_FULL) 908 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 909 else 910 anar |= ADVERTISE_10HALF; 911 } else if (speed == SPEED_100) { 912 if (duplex == DUPLEX_FULL) { 913 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 914 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 915 } else { 916 anar |= ADVERTISE_10HALF; 917 anar |= ADVERTISE_100HALF; 918 } 919 } else if (speed == SPEED_1000 && tp->supports_gmii) { 920 if (duplex == DUPLEX_FULL) { 921 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 922 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 923 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 924 } else { 925 anar |= ADVERTISE_10HALF; 926 anar |= ADVERTISE_100HALF; 927 gbcr |= ADVERTISE_1000HALF; 928 } 929 } else { 930 return -EINVAL; 931 } 932 933 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 934 } 935 936 if (tp->supports_gmii) 937 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 938 939 r8152_mdio_write(tp, MII_ADVERTISE, anar); 940 r8152_mdio_write(tp, MII_BMCR, bmcr); 941 942 return 0; 943 } 944 945 static void rtl8152_up(struct r8152 *tp) 946 { 947 r8152b_disable_aldps(tp); 948 r8152b_exit_oob(tp); 949 r8152b_enable_aldps(tp); 950 } 951 952 static void rtl8152_down(struct r8152 *tp) 953 { 954 r8152_power_cut_en(tp, false); 955 r8152b_disable_aldps(tp); 956 r8152b_enter_oob(tp); 957 r8152b_enable_aldps(tp); 958 } 959 960 static void rtl8153_up(struct r8152 *tp) 961 { 962 r8153_u1u2en(tp, false); 963 r8153_disable_aldps(tp); 964 r8153_first_init(tp); 965 r8153_u2p3en(tp, false); 966 } 967 968 static void rtl8153_down(struct r8152 *tp) 969 { 970 r8153_u1u2en(tp, false); 971 r8153_u2p3en(tp, false); 972 r8153_power_cut_en(tp, false); 973 r8153_disable_aldps(tp); 974 r8153_enter_oob(tp); 975 } 976 977 static void r8152b_get_version(struct r8152 *tp) 978 { 979 u32 ocp_data; 980 u16 tcr; 981 int i; 982 983 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 984 tcr = (u16)(ocp_data & VERSION_MASK); 985 986 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) { 987 if (tcr == r8152_versions[i].tcr) { 988 /* Found a supported version */ 989 tp->version = r8152_versions[i].version; 990 tp->supports_gmii = r8152_versions[i].gmii; 991 break; 992 } 993 } 994 995 if (tp->version == RTL_VER_UNKNOWN) 996 debug("r8152 Unknown tcr version 0x%04x\n", tcr); 997 } 998 999 static void r8152b_enable_fc(struct r8152 *tp) 1000 { 1001 u16 anar; 1002 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1003 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1004 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1005 } 1006 1007 static void rtl_tally_reset(struct r8152 *tp) 1008 { 1009 u32 ocp_data; 1010 1011 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 1012 ocp_data |= TALLY_RESET; 1013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 1014 } 1015 1016 static void r8152b_init(struct r8152 *tp) 1017 { 1018 u32 ocp_data; 1019 1020 r8152b_disable_aldps(tp); 1021 1022 if (tp->version == RTL_VER_01) { 1023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1024 ocp_data &= ~LED_MODE_MASK; 1025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1026 } 1027 1028 r8152_power_cut_en(tp, false); 1029 1030 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 1031 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 1032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 1033 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 1034 ocp_data &= ~MCU_CLK_RATIO_MASK; 1035 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 1036 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 1037 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 1038 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 1039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 1040 1041 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER); 1042 ocp_data |= BIT(15); 1043 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); 1044 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8); 1045 ocp_data &= ~BIT(15); 1046 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); 1047 1048 r8152b_enable_fc(tp); 1049 rtl_tally_reset(tp); 1050 1051 /* enable rx aggregation */ 1052 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 1053 1054 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 1055 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 1056 } 1057 1058 static void r8153_init(struct r8152 *tp) 1059 { 1060 int i; 1061 u32 ocp_data; 1062 1063 r8153_disable_aldps(tp); 1064 r8153_u1u2en(tp, false); 1065 1066 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL, 1067 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT); 1068 1069 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) { 1070 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 1071 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 1072 break; 1073 1074 mdelay(1); 1075 } 1076 1077 r8153_u2p3en(tp, false); 1078 1079 if (tp->version == RTL_VER_04) { 1080 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 1081 ocp_data &= ~pwd_dn_scale_mask; 1082 ocp_data |= pwd_dn_scale(96); 1083 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 1084 1085 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 1086 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 1087 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 1088 } else if (tp->version == RTL_VER_05) { 1089 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 1090 ocp_data &= ~ECM_ALDPS; 1091 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 1092 1093 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 1094 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 1095 ocp_data &= ~DYNAMIC_BURST; 1096 else 1097 ocp_data |= DYNAMIC_BURST; 1098 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 1099 } else if (tp->version == RTL_VER_06) { 1100 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 1101 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 1102 ocp_data &= ~DYNAMIC_BURST; 1103 else 1104 ocp_data |= DYNAMIC_BURST; 1105 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 1106 } 1107 1108 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 1109 ocp_data |= EP4_FULL_FC; 1110 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 1111 1112 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 1113 ocp_data &= ~TIMER11_EN; 1114 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 1115 1116 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1117 ocp_data &= ~LED_MODE_MASK; 1118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1119 1120 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 1121 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) 1122 ocp_data |= LPM_TIMER_500MS; 1123 else 1124 ocp_data |= LPM_TIMER_500US; 1125 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 1126 1127 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 1128 ocp_data &= ~SEN_VAL_MASK; 1129 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 1130 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 1131 1132 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 1133 1134 r8153_power_cut_en(tp, false); 1135 1136 r8152b_enable_fc(tp); 1137 rtl_tally_reset(tp); 1138 } 1139 1140 static void rtl8152_unload(struct r8152 *tp) 1141 { 1142 if (tp->version != RTL_VER_01) 1143 r8152_power_cut_en(tp, true); 1144 } 1145 1146 static void rtl8153_unload(struct r8152 *tp) 1147 { 1148 r8153_power_cut_en(tp, false); 1149 } 1150 1151 static int rtl_ops_init(struct r8152 *tp) 1152 { 1153 struct rtl_ops *ops = &tp->rtl_ops; 1154 int ret = 0; 1155 1156 switch (tp->version) { 1157 case RTL_VER_01: 1158 case RTL_VER_02: 1159 case RTL_VER_07: 1160 ops->init = r8152b_init; 1161 ops->enable = rtl8152_enable; 1162 ops->disable = rtl8152_disable; 1163 ops->up = rtl8152_up; 1164 ops->down = rtl8152_down; 1165 ops->unload = rtl8152_unload; 1166 break; 1167 1168 case RTL_VER_03: 1169 case RTL_VER_04: 1170 case RTL_VER_05: 1171 case RTL_VER_06: 1172 ops->init = r8153_init; 1173 ops->enable = rtl8153_enable; 1174 ops->disable = rtl8153_disable; 1175 ops->up = rtl8153_up; 1176 ops->down = rtl8153_down; 1177 ops->unload = rtl8153_unload; 1178 break; 1179 1180 default: 1181 ret = -ENODEV; 1182 printf("r8152 Unknown Device\n"); 1183 break; 1184 } 1185 1186 return ret; 1187 } 1188 1189 static int r8152_init_common(struct r8152 *tp) 1190 { 1191 u8 speed; 1192 int timeout = 0; 1193 int link_detected; 1194 1195 debug("** %s()\n", __func__); 1196 1197 do { 1198 speed = rtl8152_get_speed(tp); 1199 1200 link_detected = speed & LINK_STATUS; 1201 if (!link_detected) { 1202 if (timeout == 0) 1203 printf("Waiting for Ethernet connection... "); 1204 mdelay(TIMEOUT_RESOLUTION); 1205 timeout += TIMEOUT_RESOLUTION; 1206 } 1207 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 1208 if (link_detected) { 1209 tp->rtl_ops.enable(tp); 1210 1211 if (timeout != 0) 1212 printf("done.\n"); 1213 } else { 1214 printf("unable to connect.\n"); 1215 } 1216 1217 return 0; 1218 } 1219 1220 static int r8152_send_common(struct ueth_data *ueth, void *packet, int length) 1221 { 1222 struct usb_device *udev = ueth->pusb_dev; 1223 u32 opts1, opts2 = 0; 1224 int err; 1225 int actual_len; 1226 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg, 1227 PKTSIZE + sizeof(struct tx_desc)); 1228 struct tx_desc *tx_desc = (struct tx_desc *)msg; 1229 1230 debug("** %s(), len %d\n", __func__, length); 1231 1232 opts1 = length | TX_FS | TX_LS; 1233 1234 tx_desc->opts2 = cpu_to_le32(opts2); 1235 tx_desc->opts1 = cpu_to_le32(opts1); 1236 1237 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length); 1238 1239 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out), 1240 (void *)msg, length + sizeof(struct tx_desc), 1241 &actual_len, USB_BULK_SEND_TIMEOUT); 1242 debug("Tx: len = %zu, actual = %u, err = %d\n", 1243 length + sizeof(struct tx_desc), actual_len, err); 1244 1245 return err; 1246 } 1247 1248 #ifndef CONFIG_DM_ETH 1249 static int r8152_init(struct eth_device *eth, bd_t *bd) 1250 { 1251 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1252 struct r8152 *tp = (struct r8152 *)dev->dev_priv; 1253 1254 return r8152_init_common(tp); 1255 } 1256 1257 static int r8152_send(struct eth_device *eth, void *packet, int length) 1258 { 1259 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1260 1261 return r8152_send_common(dev, packet, length); 1262 } 1263 1264 static int r8152_recv(struct eth_device *eth) 1265 { 1266 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1267 1268 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ); 1269 unsigned char *pkt_ptr; 1270 int err; 1271 int actual_len; 1272 u16 packet_len; 1273 1274 u32 bytes_process = 0; 1275 struct rx_desc *rx_desc; 1276 1277 debug("** %s()\n", __func__); 1278 1279 err = usb_bulk_msg(dev->pusb_dev, 1280 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 1281 (void *)recv_buf, 1282 RTL8152_AGG_BUF_SZ, 1283 &actual_len, 1284 USB_BULK_RECV_TIMEOUT); 1285 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ, 1286 actual_len, err); 1287 if (err != 0) { 1288 debug("Rx: failed to receive\n"); 1289 return -1; 1290 } 1291 if (actual_len > RTL8152_AGG_BUF_SZ) { 1292 debug("Rx: received too many bytes %d\n", actual_len); 1293 return -1; 1294 } 1295 1296 while (bytes_process < actual_len) { 1297 rx_desc = (struct rx_desc *)(recv_buf + bytes_process); 1298 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process; 1299 1300 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1301 packet_len -= CRC_SIZE; 1302 1303 net_process_received_packet(pkt_ptr, packet_len); 1304 1305 bytes_process += 1306 (packet_len + sizeof(struct rx_desc) + CRC_SIZE); 1307 1308 if (bytes_process % 8) 1309 bytes_process = bytes_process + 8 - (bytes_process % 8); 1310 } 1311 1312 return 0; 1313 } 1314 1315 static void r8152_halt(struct eth_device *eth) 1316 { 1317 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1318 struct r8152 *tp = (struct r8152 *)dev->dev_priv; 1319 1320 debug("** %s()\n", __func__); 1321 1322 tp->rtl_ops.disable(tp); 1323 } 1324 1325 static int r8152_write_hwaddr(struct eth_device *eth) 1326 { 1327 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1328 struct r8152 *tp = (struct r8152 *)dev->dev_priv; 1329 1330 unsigned char enetaddr[8] = {0}; 1331 1332 memcpy(enetaddr, eth->enetaddr, ETH_ALEN); 1333 1334 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1335 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); 1336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1337 1338 debug("MAC %pM\n", eth->enetaddr); 1339 return 0; 1340 } 1341 1342 void r8152_eth_before_probe(void) 1343 { 1344 curr_eth_dev = 0; 1345 } 1346 1347 /* Probe to see if a new device is actually an realtek device */ 1348 int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, 1349 struct ueth_data *ss) 1350 { 1351 struct usb_interface *iface; 1352 struct usb_interface_descriptor *iface_desc; 1353 int ep_in_found = 0, ep_out_found = 0; 1354 int i; 1355 1356 struct r8152 *tp; 1357 1358 /* let's examine the device now */ 1359 iface = &dev->config.if_desc[ifnum]; 1360 iface_desc = &dev->config.if_desc[ifnum].desc; 1361 1362 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) { 1363 if (dev->descriptor.idVendor == r8152_dongles[i].vendor && 1364 dev->descriptor.idProduct == r8152_dongles[i].product) 1365 /* Found a supported dongle */ 1366 break; 1367 } 1368 1369 if (i == ARRAY_SIZE(r8152_dongles)) 1370 return 0; 1371 1372 memset(ss, 0, sizeof(struct ueth_data)); 1373 1374 /* At this point, we know we've got a live one */ 1375 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 1376 dev->descriptor.idVendor, dev->descriptor.idProduct); 1377 1378 /* Initialize the ueth_data structure with some useful info */ 1379 ss->ifnum = ifnum; 1380 ss->pusb_dev = dev; 1381 ss->subclass = iface_desc->bInterfaceSubClass; 1382 ss->protocol = iface_desc->bInterfaceProtocol; 1383 1384 /* alloc driver private */ 1385 ss->dev_priv = calloc(1, sizeof(struct r8152)); 1386 1387 if (!ss->dev_priv) 1388 return 0; 1389 1390 /* 1391 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 1392 * int. We will ignore any others. 1393 */ 1394 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 1395 /* is it an BULK endpoint? */ 1396 if ((iface->ep_desc[i].bmAttributes & 1397 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 1398 u8 ep_addr = iface->ep_desc[i].bEndpointAddress; 1399 if ((ep_addr & USB_DIR_IN) && !ep_in_found) { 1400 ss->ep_in = ep_addr & 1401 USB_ENDPOINT_NUMBER_MASK; 1402 ep_in_found = 1; 1403 } else { 1404 if (!ep_out_found) { 1405 ss->ep_out = ep_addr & 1406 USB_ENDPOINT_NUMBER_MASK; 1407 ep_out_found = 1; 1408 } 1409 } 1410 } 1411 1412 /* is it an interrupt endpoint? */ 1413 if ((iface->ep_desc[i].bmAttributes & 1414 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 1415 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 1416 USB_ENDPOINT_NUMBER_MASK; 1417 ss->irqinterval = iface->ep_desc[i].bInterval; 1418 } 1419 } 1420 1421 debug("Endpoints In %d Out %d Int %d\n", 1422 ss->ep_in, ss->ep_out, ss->ep_int); 1423 1424 /* Do some basic sanity checks, and bail if we find a problem */ 1425 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 1426 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 1427 debug("Problems with device\n"); 1428 return 0; 1429 } 1430 1431 dev->privptr = (void *)ss; 1432 1433 tp = ss->dev_priv; 1434 tp->udev = dev; 1435 tp->intf = iface; 1436 1437 r8152b_get_version(tp); 1438 1439 if (rtl_ops_init(tp)) 1440 return 0; 1441 1442 tp->rtl_ops.init(tp); 1443 tp->rtl_ops.up(tp); 1444 1445 rtl8152_set_speed(tp, AUTONEG_ENABLE, 1446 tp->supports_gmii ? SPEED_1000 : SPEED_100, 1447 DUPLEX_FULL); 1448 1449 return 1; 1450 } 1451 1452 int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 1453 struct eth_device *eth) 1454 { 1455 if (!eth) { 1456 debug("%s: missing parameter.\n", __func__); 1457 return 0; 1458 } 1459 1460 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++); 1461 eth->init = r8152_init; 1462 eth->send = r8152_send; 1463 eth->recv = r8152_recv; 1464 eth->halt = r8152_halt; 1465 eth->write_hwaddr = r8152_write_hwaddr; 1466 eth->priv = ss; 1467 1468 /* Get the MAC address */ 1469 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0) 1470 return 0; 1471 1472 debug("MAC %pM\n", eth->enetaddr); 1473 return 1; 1474 } 1475 #endif /* !CONFIG_DM_ETH */ 1476 1477 #ifdef CONFIG_DM_ETH 1478 static int r8152_eth_start(struct udevice *dev) 1479 { 1480 struct r8152 *tp = dev_get_priv(dev); 1481 1482 debug("** %s (%d)\n", __func__, __LINE__); 1483 1484 return r8152_init_common(tp); 1485 } 1486 1487 void r8152_eth_stop(struct udevice *dev) 1488 { 1489 struct r8152 *tp = dev_get_priv(dev); 1490 1491 debug("** %s (%d)\n", __func__, __LINE__); 1492 1493 tp->rtl_ops.disable(tp); 1494 } 1495 1496 int r8152_eth_send(struct udevice *dev, void *packet, int length) 1497 { 1498 struct r8152 *tp = dev_get_priv(dev); 1499 1500 return r8152_send_common(&tp->ueth, packet, length); 1501 } 1502 1503 int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp) 1504 { 1505 struct r8152 *tp = dev_get_priv(dev); 1506 struct ueth_data *ueth = &tp->ueth; 1507 uint8_t *ptr; 1508 int ret, len; 1509 struct rx_desc *rx_desc; 1510 u16 packet_len; 1511 1512 len = usb_ether_get_rx_bytes(ueth, &ptr); 1513 debug("%s: first try, len=%d\n", __func__, len); 1514 if (!len) { 1515 if (!(flags & ETH_RECV_CHECK_DEVICE)) 1516 return -EAGAIN; 1517 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ); 1518 if (ret) 1519 return ret; 1520 1521 len = usb_ether_get_rx_bytes(ueth, &ptr); 1522 debug("%s: second try, len=%d\n", __func__, len); 1523 } 1524 1525 rx_desc = (struct rx_desc *)ptr; 1526 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1527 packet_len -= CRC_SIZE; 1528 1529 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) { 1530 debug("Rx: too large packet: %d\n", packet_len); 1531 goto err; 1532 } 1533 1534 *packetp = ptr + sizeof(struct rx_desc); 1535 return packet_len; 1536 1537 err: 1538 usb_ether_advance_rxbuf(ueth, -1); 1539 return -ENOSPC; 1540 } 1541 1542 static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len) 1543 { 1544 struct r8152 *tp = dev_get_priv(dev); 1545 1546 packet_len += sizeof(struct rx_desc) + CRC_SIZE; 1547 packet_len = ALIGN(packet_len, 8); 1548 usb_ether_advance_rxbuf(&tp->ueth, packet_len); 1549 1550 return 0; 1551 } 1552 1553 static int r8152_write_hwaddr(struct udevice *dev) 1554 { 1555 struct eth_pdata *pdata = dev_get_platdata(dev); 1556 struct r8152 *tp = dev_get_priv(dev); 1557 1558 unsigned char enetaddr[8] = { 0 }; 1559 1560 debug("** %s (%d)\n", __func__, __LINE__); 1561 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN); 1562 1563 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1564 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); 1565 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1566 1567 debug("MAC %pM\n", pdata->enetaddr); 1568 return 0; 1569 } 1570 1571 int r8152_read_rom_hwaddr(struct udevice *dev) 1572 { 1573 struct eth_pdata *pdata = dev_get_platdata(dev); 1574 struct r8152 *tp = dev_get_priv(dev); 1575 1576 debug("** %s (%d)\n", __func__, __LINE__); 1577 r8152_read_mac(tp, pdata->enetaddr); 1578 return 0; 1579 } 1580 1581 static int r8152_eth_probe(struct udevice *dev) 1582 { 1583 struct usb_device *udev = dev_get_parent_priv(dev); 1584 struct eth_pdata *pdata = dev_get_platdata(dev); 1585 struct r8152 *tp = dev_get_priv(dev); 1586 struct ueth_data *ueth = &tp->ueth; 1587 int ret; 1588 1589 tp->udev = udev; 1590 r8152_read_mac(tp, pdata->enetaddr); 1591 1592 r8152b_get_version(tp); 1593 1594 ret = rtl_ops_init(tp); 1595 if (ret) 1596 return ret; 1597 1598 tp->rtl_ops.init(tp); 1599 tp->rtl_ops.up(tp); 1600 1601 rtl8152_set_speed(tp, AUTONEG_ENABLE, 1602 tp->supports_gmii ? SPEED_1000 : SPEED_100, 1603 DUPLEX_FULL); 1604 1605 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ); 1606 } 1607 1608 static const struct eth_ops r8152_eth_ops = { 1609 .start = r8152_eth_start, 1610 .send = r8152_eth_send, 1611 .recv = r8152_eth_recv, 1612 .free_pkt = r8152_free_pkt, 1613 .stop = r8152_eth_stop, 1614 .write_hwaddr = r8152_write_hwaddr, 1615 .read_rom_hwaddr = r8152_read_rom_hwaddr, 1616 }; 1617 1618 U_BOOT_DRIVER(r8152_eth) = { 1619 .name = "r8152_eth", 1620 .id = UCLASS_ETH, 1621 .probe = r8152_eth_probe, 1622 .ops = &r8152_eth_ops, 1623 .priv_auto_alloc_size = sizeof(struct r8152), 1624 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1625 }; 1626 1627 static const struct usb_device_id r8152_eth_id_table[] = { 1628 /* Realtek */ 1629 { USB_DEVICE(0x0bda, 0x8050) }, 1630 { USB_DEVICE(0x0bda, 0x8152) }, 1631 { USB_DEVICE(0x0bda, 0x8153) }, 1632 1633 /* Samsung */ 1634 { USB_DEVICE(0x04e8, 0xa101) }, 1635 1636 /* Lenovo */ 1637 { USB_DEVICE(0x17ef, 0x304f) }, 1638 { USB_DEVICE(0x17ef, 0x3052) }, 1639 { USB_DEVICE(0x17ef, 0x3054) }, 1640 { USB_DEVICE(0x17ef, 0x3057) }, 1641 { USB_DEVICE(0x17ef, 0x7205) }, 1642 { USB_DEVICE(0x17ef, 0x720a) }, 1643 { USB_DEVICE(0x17ef, 0x720b) }, 1644 { USB_DEVICE(0x17ef, 0x720c) }, 1645 1646 /* TP-LINK */ 1647 { USB_DEVICE(0x2357, 0x0601) }, 1648 1649 /* Nvidia */ 1650 { USB_DEVICE(0x0955, 0x09ff) }, 1651 1652 { } /* Terminating entry */ 1653 }; 1654 1655 U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); 1656 #endif /* CONFIG_DM_ETH */ 1657 1658