1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. 4 * 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <memalign.h> 12 #include <usb.h> 13 #include <usb/lin_gadget_compat.h> 14 #include <linux/mii.h> 15 #include <linux/bitops.h> 16 #include "usb_ether.h" 17 #include "r8152.h" 18 19 #ifndef CONFIG_DM_ETH 20 /* local vars */ 21 static int curr_eth_dev; /* index for name of next device detected */ 22 23 struct r8152_dongle { 24 unsigned short vendor; 25 unsigned short product; 26 }; 27 28 static const struct r8152_dongle r8152_dongles[] = { 29 /* Realtek */ 30 { 0x0bda, 0x8050 }, 31 { 0x0bda, 0x8152 }, 32 { 0x0bda, 0x8153 }, 33 34 /* Samsung */ 35 { 0x04e8, 0xa101 }, 36 37 /* Lenovo */ 38 { 0x17ef, 0x304f }, 39 { 0x17ef, 0x3052 }, 40 { 0x17ef, 0x3054 }, 41 { 0x17ef, 0x3057 }, 42 { 0x17ef, 0x7205 }, 43 { 0x17ef, 0x720a }, 44 { 0x17ef, 0x720b }, 45 { 0x17ef, 0x720c }, 46 47 /* TP-LINK */ 48 { 0x2357, 0x0601 }, 49 50 /* Nvidia */ 51 { 0x0955, 0x09ff }, 52 }; 53 #endif 54 55 struct r8152_version { 56 unsigned short tcr; 57 unsigned short version; 58 bool gmii; 59 }; 60 61 static const struct r8152_version r8152_versions[] = { 62 { 0x4c00, RTL_VER_01, 0 }, 63 { 0x4c10, RTL_VER_02, 0 }, 64 { 0x5c00, RTL_VER_03, 1 }, 65 { 0x5c10, RTL_VER_04, 1 }, 66 { 0x5c20, RTL_VER_05, 1 }, 67 { 0x5c30, RTL_VER_06, 1 }, 68 { 0x4800, RTL_VER_07, 0 }, 69 }; 70 71 static 72 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 73 { 74 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size); 75 int ret; 76 77 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 78 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 79 value, index, tmp, size, 500); 80 memcpy(data, tmp, size); 81 return ret; 82 } 83 84 static 85 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 86 { 87 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size); 88 89 memcpy(tmp, data, size); 90 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 91 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 92 value, index, tmp, size, 500); 93 } 94 95 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 96 void *data, u16 type) 97 { 98 u16 burst_size = 64; 99 int ret; 100 int txsize; 101 102 /* both size and index must be 4 bytes align */ 103 if ((size & 3) || !size || (index & 3) || !data) 104 return -EINVAL; 105 106 if (index + size > 0xffff) 107 return -EINVAL; 108 109 while (size) { 110 txsize = min(size, burst_size); 111 ret = get_registers(tp, index, type, txsize, data); 112 if (ret < 0) 113 break; 114 115 index += txsize; 116 data += txsize; 117 size -= txsize; 118 } 119 120 return ret; 121 } 122 123 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 124 u16 size, void *data, u16 type) 125 { 126 int ret; 127 u16 byteen_start, byteen_end, byte_en_to_hw; 128 u16 burst_size = 512; 129 int txsize; 130 131 /* both size and index must be 4 bytes align */ 132 if ((size & 3) || !size || (index & 3) || !data) 133 return -EINVAL; 134 135 if (index + size > 0xffff) 136 return -EINVAL; 137 138 byteen_start = byteen & BYTE_EN_START_MASK; 139 byteen_end = byteen & BYTE_EN_END_MASK; 140 141 byte_en_to_hw = byteen_start | (byteen_start << 4); 142 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data); 143 if (ret < 0) 144 return ret; 145 146 index += 4; 147 data += 4; 148 size -= 4; 149 150 if (size) { 151 size -= 4; 152 153 while (size) { 154 txsize = min(size, burst_size); 155 156 ret = set_registers(tp, index, 157 type | BYTE_EN_DWORD, 158 txsize, data); 159 if (ret < 0) 160 return ret; 161 162 index += txsize; 163 data += txsize; 164 size -= txsize; 165 } 166 167 byte_en_to_hw = byteen_end | (byteen_end >> 4); 168 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data); 169 if (ret < 0) 170 return ret; 171 } 172 173 return ret; 174 } 175 176 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 177 { 178 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 179 } 180 181 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 182 { 183 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 184 } 185 186 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 187 { 188 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 189 } 190 191 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 192 { 193 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 194 } 195 196 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 197 { 198 __le32 data; 199 200 generic_ocp_read(tp, index, sizeof(data), &data, type); 201 202 return __le32_to_cpu(data); 203 } 204 205 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 206 { 207 __le32 tmp = __cpu_to_le32(data); 208 209 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 210 } 211 212 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 213 { 214 u32 data; 215 __le32 tmp; 216 u8 shift = index & 2; 217 218 index &= ~3; 219 220 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 221 222 data = __le32_to_cpu(tmp); 223 data >>= (shift * 8); 224 data &= 0xffff; 225 226 return data; 227 } 228 229 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 230 { 231 u32 mask = 0xffff; 232 __le32 tmp; 233 u16 byen = BYTE_EN_WORD; 234 u8 shift = index & 2; 235 236 data &= mask; 237 238 if (index & 2) { 239 byen <<= shift; 240 mask <<= (shift * 8); 241 data <<= (shift * 8); 242 index &= ~3; 243 } 244 245 tmp = __cpu_to_le32(data); 246 247 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 248 } 249 250 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 251 { 252 u32 data; 253 __le32 tmp; 254 u8 shift = index & 3; 255 256 index &= ~3; 257 258 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 259 260 data = __le32_to_cpu(tmp); 261 data >>= (shift * 8); 262 data &= 0xff; 263 264 return data; 265 } 266 267 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 268 { 269 u32 mask = 0xff; 270 __le32 tmp; 271 u16 byen = BYTE_EN_BYTE; 272 u8 shift = index & 3; 273 274 data &= mask; 275 276 if (index & 3) { 277 byen <<= shift; 278 mask <<= (shift * 8); 279 data <<= (shift * 8); 280 index &= ~3; 281 } 282 283 tmp = __cpu_to_le32(data); 284 285 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 286 } 287 288 u16 ocp_reg_read(struct r8152 *tp, u16 addr) 289 { 290 u16 ocp_base, ocp_index; 291 292 ocp_base = addr & 0xf000; 293 if (ocp_base != tp->ocp_base) { 294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 295 tp->ocp_base = ocp_base; 296 } 297 298 ocp_index = (addr & 0x0fff) | 0xb000; 299 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 300 } 301 302 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 303 { 304 u16 ocp_base, ocp_index; 305 306 ocp_base = addr & 0xf000; 307 if (ocp_base != tp->ocp_base) { 308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 309 tp->ocp_base = ocp_base; 310 } 311 312 ocp_index = (addr & 0x0fff) | 0xb000; 313 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 314 } 315 316 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 317 { 318 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 319 } 320 321 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 322 { 323 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 324 } 325 326 void sram_write(struct r8152 *tp, u16 addr, u16 data) 327 { 328 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 329 ocp_reg_write(tp, OCP_SRAM_DATA, data); 330 } 331 332 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index, 333 const u32 mask, bool set, unsigned int timeout) 334 { 335 u32 val; 336 337 while (--timeout) { 338 if (ocp_reg) 339 val = ocp_reg_read(tp, index); 340 else 341 val = ocp_read_dword(tp, type, index); 342 343 if (!set) 344 val = ~val; 345 346 if ((val & mask) == mask) 347 return 0; 348 349 mdelay(1); 350 } 351 352 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n", 353 __func__, index, mask, timeout); 354 355 return -ETIMEDOUT; 356 } 357 358 static void r8152b_reset_packet_filter(struct r8152 *tp) 359 { 360 u32 ocp_data; 361 362 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 363 ocp_data &= ~FMC_FCR_MCU_EN; 364 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 365 ocp_data |= FMC_FCR_MCU_EN; 366 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 367 } 368 369 static void rtl8152_wait_fifo_empty(struct r8152 *tp) 370 { 371 int ret; 372 373 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 374 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT); 375 if (ret) 376 debug("Timeout waiting for FIFO empty\n"); 377 378 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0, 379 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT); 380 if (ret) 381 debug("Timeout waiting for TX empty\n"); 382 } 383 384 static void rtl8152_nic_reset(struct r8152 *tp) 385 { 386 int ret; 387 u32 ocp_data; 388 389 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL); 390 ocp_data |= BIST_CTRL_SW_RESET; 391 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data); 392 393 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL, 394 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT); 395 if (ret) 396 debug("Timeout waiting for NIC reset\n"); 397 } 398 399 static u8 rtl8152_get_speed(struct r8152 *tp) 400 { 401 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 402 } 403 404 static void rtl_set_eee_plus(struct r8152 *tp) 405 { 406 u32 ocp_data; 407 408 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 409 ocp_data &= ~EEEP_CR_EEEP_TX; 410 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 411 } 412 413 static void rxdy_gated_en(struct r8152 *tp, bool enable) 414 { 415 u32 ocp_data; 416 417 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 418 if (enable) 419 ocp_data |= RXDY_GATED_EN; 420 else 421 ocp_data &= ~RXDY_GATED_EN; 422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 423 } 424 425 static void rtl8152_set_rx_mode(struct r8152 *tp) 426 { 427 u32 ocp_data; 428 __le32 tmp[2]; 429 430 tmp[0] = 0xffffffff; 431 tmp[1] = 0xffffffff; 432 433 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 434 435 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 436 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 437 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 438 } 439 440 static int rtl_enable(struct r8152 *tp) 441 { 442 u32 ocp_data; 443 444 r8152b_reset_packet_filter(tp); 445 446 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 447 ocp_data |= PLA_CR_RE | PLA_CR_TE; 448 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 449 450 rxdy_gated_en(tp, false); 451 452 rtl8152_set_rx_mode(tp); 453 454 return 0; 455 } 456 457 static int rtl8152_enable(struct r8152 *tp) 458 { 459 rtl_set_eee_plus(tp); 460 461 return rtl_enable(tp); 462 } 463 464 static void r8153_set_rx_early_timeout(struct r8152 *tp) 465 { 466 u32 ocp_data = tp->coalesce / 8; 467 468 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); 469 } 470 471 static void r8153_set_rx_early_size(struct r8152 *tp) 472 { 473 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4; 474 475 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); 476 } 477 478 static int rtl8153_enable(struct r8152 *tp) 479 { 480 rtl_set_eee_plus(tp); 481 r8153_set_rx_early_timeout(tp); 482 r8153_set_rx_early_size(tp); 483 484 return rtl_enable(tp); 485 } 486 487 static void rtl_disable(struct r8152 *tp) 488 { 489 u32 ocp_data; 490 491 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 492 ocp_data &= ~RCR_ACPT_ALL; 493 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 494 495 rxdy_gated_en(tp, true); 496 497 rtl8152_wait_fifo_empty(tp); 498 rtl8152_nic_reset(tp); 499 } 500 501 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 502 { 503 u32 ocp_data; 504 505 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 506 if (enable) 507 ocp_data |= POWER_CUT; 508 else 509 ocp_data &= ~POWER_CUT; 510 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 511 512 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 513 ocp_data &= ~RESUME_INDICATE; 514 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 515 } 516 517 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 518 { 519 u32 ocp_data; 520 521 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 522 if (enable) 523 ocp_data |= CPCR_RX_VLAN; 524 else 525 ocp_data &= ~CPCR_RX_VLAN; 526 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 527 } 528 529 static void r8153_u1u2en(struct r8152 *tp, bool enable) 530 { 531 u8 u1u2[8]; 532 533 if (enable) 534 memset(u1u2, 0xff, sizeof(u1u2)); 535 else 536 memset(u1u2, 0x00, sizeof(u1u2)); 537 538 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 539 } 540 541 static void r8153_u2p3en(struct r8152 *tp, bool enable) 542 { 543 u32 ocp_data; 544 545 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 546 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 547 ocp_data |= U2P3_ENABLE; 548 else 549 ocp_data &= ~U2P3_ENABLE; 550 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 551 } 552 553 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 554 { 555 u32 ocp_data; 556 557 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 558 if (enable) 559 ocp_data |= PWR_EN | PHASE2_EN; 560 else 561 ocp_data &= ~(PWR_EN | PHASE2_EN); 562 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 563 564 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 565 ocp_data &= ~PCUT_STATUS; 566 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 567 } 568 569 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr) 570 { 571 int ret; 572 unsigned char enetaddr[8] = {0}; 573 574 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr); 575 if (ret < 0) 576 return ret; 577 578 memcpy(macaddr, enetaddr, ETH_ALEN); 579 return 0; 580 } 581 582 static void r8152b_disable_aldps(struct r8152 *tp) 583 { 584 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 585 mdelay(20); 586 } 587 588 static void r8152b_enable_aldps(struct r8152 *tp) 589 { 590 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 591 LINKENA | DIS_SDSAVE); 592 } 593 594 static void rtl8152_disable(struct r8152 *tp) 595 { 596 r8152b_disable_aldps(tp); 597 rtl_disable(tp); 598 r8152b_enable_aldps(tp); 599 } 600 601 static void r8152b_hw_phy_cfg(struct r8152 *tp) 602 { 603 u16 data; 604 605 data = r8152_mdio_read(tp, MII_BMCR); 606 if (data & BMCR_PDOWN) { 607 data &= ~BMCR_PDOWN; 608 r8152_mdio_write(tp, MII_BMCR, data); 609 } 610 611 r8152b_firmware(tp); 612 } 613 614 static void rtl8152_reinit_ll(struct r8152 *tp) 615 { 616 u32 ocp_data; 617 int ret; 618 619 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 620 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); 621 if (ret) 622 debug("Timeout waiting for link list ready\n"); 623 624 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 625 ocp_data |= RE_INIT_LL; 626 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 627 628 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 629 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); 630 if (ret) 631 debug("Timeout waiting for link list ready\n"); 632 } 633 634 static void r8152b_exit_oob(struct r8152 *tp) 635 { 636 u32 ocp_data; 637 638 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 639 ocp_data &= ~RCR_ACPT_ALL; 640 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 641 642 rxdy_gated_en(tp, true); 643 r8152b_hw_phy_cfg(tp); 644 645 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 646 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 647 648 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 649 ocp_data &= ~NOW_IS_OOB; 650 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 651 652 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 653 ocp_data &= ~MCU_BORW_EN; 654 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 655 656 rtl8152_reinit_ll(tp); 657 rtl8152_nic_reset(tp); 658 659 /* rx share fifo credit full threshold */ 660 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 661 662 if (tp->udev->speed == USB_SPEED_FULL || 663 tp->udev->speed == USB_SPEED_LOW) { 664 /* rx share fifo credit near full threshold */ 665 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 666 RXFIFO_THR2_FULL); 667 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 668 RXFIFO_THR3_FULL); 669 } else { 670 /* rx share fifo credit near full threshold */ 671 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 672 RXFIFO_THR2_HIGH); 673 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 674 RXFIFO_THR3_HIGH); 675 } 676 677 /* TX share fifo free credit full threshold */ 678 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 679 680 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 681 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 682 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 683 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 684 685 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 686 687 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 688 ocp_data |= TCR0_AUTO_FIFO; 689 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 690 } 691 692 static void r8152b_enter_oob(struct r8152 *tp) 693 { 694 u32 ocp_data; 695 696 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 697 ocp_data &= ~NOW_IS_OOB; 698 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 699 700 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 702 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 703 704 rtl_disable(tp); 705 706 rtl8152_reinit_ll(tp); 707 708 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 709 710 rtl_rx_vlan_en(tp, false); 711 712 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 713 ocp_data |= ALDPS_PROXY_MODE; 714 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 715 716 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 717 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 718 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 719 720 rxdy_gated_en(tp, false); 721 722 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 723 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 724 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 725 } 726 727 static void r8153_hw_phy_cfg(struct r8152 *tp) 728 { 729 u32 ocp_data; 730 u16 data; 731 732 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 733 tp->version == RTL_VER_05) 734 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 735 736 data = r8152_mdio_read(tp, MII_BMCR); 737 if (data & BMCR_PDOWN) { 738 data &= ~BMCR_PDOWN; 739 r8152_mdio_write(tp, MII_BMCR, data); 740 } 741 742 r8153_firmware(tp); 743 744 if (tp->version == RTL_VER_03) { 745 data = ocp_reg_read(tp, OCP_EEE_CFG); 746 data &= ~CTAP_SHORT_EN; 747 ocp_reg_write(tp, OCP_EEE_CFG, data); 748 } 749 750 data = ocp_reg_read(tp, OCP_POWER_CFG); 751 data |= EEE_CLKDIV_EN; 752 ocp_reg_write(tp, OCP_POWER_CFG, data); 753 754 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 755 data |= EN_10M_BGOFF; 756 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 757 data = ocp_reg_read(tp, OCP_POWER_CFG); 758 data |= EN_10M_PLLOFF; 759 ocp_reg_write(tp, OCP_POWER_CFG, data); 760 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 761 762 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 763 ocp_data |= PFM_PWM_SWITCH; 764 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 765 766 /* Enable LPF corner auto tune */ 767 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 768 769 /* Adjust 10M Amplitude */ 770 sram_write(tp, SRAM_10M_AMP1, 0x00af); 771 sram_write(tp, SRAM_10M_AMP2, 0x0208); 772 } 773 774 static void r8153_first_init(struct r8152 *tp) 775 { 776 u32 ocp_data; 777 778 rxdy_gated_en(tp, true); 779 780 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 781 ocp_data &= ~RCR_ACPT_ALL; 782 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 783 784 r8153_hw_phy_cfg(tp); 785 786 rtl8152_nic_reset(tp); 787 788 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 789 ocp_data &= ~NOW_IS_OOB; 790 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 791 792 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 793 ocp_data &= ~MCU_BORW_EN; 794 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 795 796 rtl8152_reinit_ll(tp); 797 798 rtl_rx_vlan_en(tp, false); 799 800 ocp_data = RTL8153_RMS; 801 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 802 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 803 804 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 805 ocp_data |= TCR0_AUTO_FIFO; 806 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 807 808 rtl8152_nic_reset(tp); 809 810 /* rx share fifo credit full threshold */ 811 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 812 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 813 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 814 /* TX share fifo free credit full threshold */ 815 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 816 817 /* rx aggregation */ 818 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 819 820 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 821 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 822 } 823 824 static void r8153_enter_oob(struct r8152 *tp) 825 { 826 u32 ocp_data; 827 828 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 829 ocp_data &= ~NOW_IS_OOB; 830 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 831 832 rtl_disable(tp); 833 834 rtl8152_reinit_ll(tp); 835 836 ocp_data = RTL8153_RMS; 837 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 838 839 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 840 ocp_data &= ~TEREDO_WAKE_MASK; 841 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 842 843 rtl_rx_vlan_en(tp, false); 844 845 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 846 ocp_data |= ALDPS_PROXY_MODE; 847 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 848 849 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 850 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 851 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 852 853 rxdy_gated_en(tp, false); 854 855 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 856 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 857 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 858 } 859 860 static void r8153_disable_aldps(struct r8152 *tp) 861 { 862 u16 data; 863 864 data = ocp_reg_read(tp, OCP_POWER_CFG); 865 data &= ~EN_ALDPS; 866 ocp_reg_write(tp, OCP_POWER_CFG, data); 867 mdelay(20); 868 } 869 870 static void rtl8153_disable(struct r8152 *tp) 871 { 872 r8153_disable_aldps(tp); 873 rtl_disable(tp); 874 } 875 876 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 877 { 878 u16 bmcr, anar, gbcr; 879 880 anar = r8152_mdio_read(tp, MII_ADVERTISE); 881 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 882 ADVERTISE_100HALF | ADVERTISE_100FULL); 883 if (tp->supports_gmii) { 884 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 885 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 886 } else { 887 gbcr = 0; 888 } 889 890 if (autoneg == AUTONEG_DISABLE) { 891 if (speed == SPEED_10) { 892 bmcr = 0; 893 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 894 } else if (speed == SPEED_100) { 895 bmcr = BMCR_SPEED100; 896 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 897 } else if (speed == SPEED_1000 && tp->supports_gmii) { 898 bmcr = BMCR_SPEED1000; 899 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 900 } else { 901 return -EINVAL; 902 } 903 904 if (duplex == DUPLEX_FULL) 905 bmcr |= BMCR_FULLDPLX; 906 } else { 907 if (speed == SPEED_10) { 908 if (duplex == DUPLEX_FULL) 909 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 910 else 911 anar |= ADVERTISE_10HALF; 912 } else if (speed == SPEED_100) { 913 if (duplex == DUPLEX_FULL) { 914 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 915 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 916 } else { 917 anar |= ADVERTISE_10HALF; 918 anar |= ADVERTISE_100HALF; 919 } 920 } else if (speed == SPEED_1000 && tp->supports_gmii) { 921 if (duplex == DUPLEX_FULL) { 922 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 923 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 924 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 925 } else { 926 anar |= ADVERTISE_10HALF; 927 anar |= ADVERTISE_100HALF; 928 gbcr |= ADVERTISE_1000HALF; 929 } 930 } else { 931 return -EINVAL; 932 } 933 934 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 935 } 936 937 if (tp->supports_gmii) 938 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 939 940 r8152_mdio_write(tp, MII_ADVERTISE, anar); 941 r8152_mdio_write(tp, MII_BMCR, bmcr); 942 943 return 0; 944 } 945 946 static void rtl8152_up(struct r8152 *tp) 947 { 948 r8152b_disable_aldps(tp); 949 r8152b_exit_oob(tp); 950 r8152b_enable_aldps(tp); 951 } 952 953 static void rtl8152_down(struct r8152 *tp) 954 { 955 r8152_power_cut_en(tp, false); 956 r8152b_disable_aldps(tp); 957 r8152b_enter_oob(tp); 958 r8152b_enable_aldps(tp); 959 } 960 961 static void rtl8153_up(struct r8152 *tp) 962 { 963 r8153_u1u2en(tp, false); 964 r8153_disable_aldps(tp); 965 r8153_first_init(tp); 966 r8153_u2p3en(tp, false); 967 } 968 969 static void rtl8153_down(struct r8152 *tp) 970 { 971 r8153_u1u2en(tp, false); 972 r8153_u2p3en(tp, false); 973 r8153_power_cut_en(tp, false); 974 r8153_disable_aldps(tp); 975 r8153_enter_oob(tp); 976 } 977 978 static void r8152b_get_version(struct r8152 *tp) 979 { 980 u32 ocp_data; 981 u16 tcr; 982 int i; 983 984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 985 tcr = (u16)(ocp_data & VERSION_MASK); 986 987 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) { 988 if (tcr == r8152_versions[i].tcr) { 989 /* Found a supported version */ 990 tp->version = r8152_versions[i].version; 991 tp->supports_gmii = r8152_versions[i].gmii; 992 break; 993 } 994 } 995 996 if (tp->version == RTL_VER_UNKNOWN) 997 debug("r8152 Unknown tcr version 0x%04x\n", tcr); 998 } 999 1000 static void r8152b_enable_fc(struct r8152 *tp) 1001 { 1002 u16 anar; 1003 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1004 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1005 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1006 } 1007 1008 static void rtl_tally_reset(struct r8152 *tp) 1009 { 1010 u32 ocp_data; 1011 1012 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 1013 ocp_data |= TALLY_RESET; 1014 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 1015 } 1016 1017 static void r8152b_init(struct r8152 *tp) 1018 { 1019 u32 ocp_data; 1020 1021 r8152b_disable_aldps(tp); 1022 1023 if (tp->version == RTL_VER_01) { 1024 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1025 ocp_data &= ~LED_MODE_MASK; 1026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1027 } 1028 1029 r8152_power_cut_en(tp, false); 1030 1031 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 1032 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 1033 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 1034 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 1035 ocp_data &= ~MCU_CLK_RATIO_MASK; 1036 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 1037 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 1038 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 1039 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 1040 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 1041 1042 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER); 1043 ocp_data |= BIT(15); 1044 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); 1045 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8); 1046 ocp_data &= ~BIT(15); 1047 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); 1048 1049 r8152b_enable_fc(tp); 1050 rtl_tally_reset(tp); 1051 1052 /* enable rx aggregation */ 1053 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 1054 1055 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 1056 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 1057 } 1058 1059 static void r8153_init(struct r8152 *tp) 1060 { 1061 int i; 1062 u32 ocp_data; 1063 1064 r8153_disable_aldps(tp); 1065 r8153_u1u2en(tp, false); 1066 1067 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL, 1068 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT); 1069 1070 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) { 1071 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 1072 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 1073 break; 1074 1075 mdelay(1); 1076 } 1077 1078 r8153_u2p3en(tp, false); 1079 1080 if (tp->version == RTL_VER_04) { 1081 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 1082 ocp_data &= ~pwd_dn_scale_mask; 1083 ocp_data |= pwd_dn_scale(96); 1084 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 1085 1086 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 1087 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 1088 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 1089 } else if (tp->version == RTL_VER_05) { 1090 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 1091 ocp_data &= ~ECM_ALDPS; 1092 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 1093 1094 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 1095 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 1096 ocp_data &= ~DYNAMIC_BURST; 1097 else 1098 ocp_data |= DYNAMIC_BURST; 1099 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 1100 } else if (tp->version == RTL_VER_06) { 1101 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 1102 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 1103 ocp_data &= ~DYNAMIC_BURST; 1104 else 1105 ocp_data |= DYNAMIC_BURST; 1106 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 1107 } 1108 1109 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 1110 ocp_data |= EP4_FULL_FC; 1111 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 1112 1113 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 1114 ocp_data &= ~TIMER11_EN; 1115 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 1116 1117 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1118 ocp_data &= ~LED_MODE_MASK; 1119 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1120 1121 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 1122 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) 1123 ocp_data |= LPM_TIMER_500MS; 1124 else 1125 ocp_data |= LPM_TIMER_500US; 1126 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 1127 1128 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 1129 ocp_data &= ~SEN_VAL_MASK; 1130 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 1131 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 1132 1133 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 1134 1135 r8153_power_cut_en(tp, false); 1136 1137 r8152b_enable_fc(tp); 1138 rtl_tally_reset(tp); 1139 } 1140 1141 static void rtl8152_unload(struct r8152 *tp) 1142 { 1143 if (tp->version != RTL_VER_01) 1144 r8152_power_cut_en(tp, true); 1145 } 1146 1147 static void rtl8153_unload(struct r8152 *tp) 1148 { 1149 r8153_power_cut_en(tp, false); 1150 } 1151 1152 static int rtl_ops_init(struct r8152 *tp) 1153 { 1154 struct rtl_ops *ops = &tp->rtl_ops; 1155 int ret = 0; 1156 1157 switch (tp->version) { 1158 case RTL_VER_01: 1159 case RTL_VER_02: 1160 case RTL_VER_07: 1161 ops->init = r8152b_init; 1162 ops->enable = rtl8152_enable; 1163 ops->disable = rtl8152_disable; 1164 ops->up = rtl8152_up; 1165 ops->down = rtl8152_down; 1166 ops->unload = rtl8152_unload; 1167 break; 1168 1169 case RTL_VER_03: 1170 case RTL_VER_04: 1171 case RTL_VER_05: 1172 case RTL_VER_06: 1173 ops->init = r8153_init; 1174 ops->enable = rtl8153_enable; 1175 ops->disable = rtl8153_disable; 1176 ops->up = rtl8153_up; 1177 ops->down = rtl8153_down; 1178 ops->unload = rtl8153_unload; 1179 break; 1180 1181 default: 1182 ret = -ENODEV; 1183 printf("r8152 Unknown Device\n"); 1184 break; 1185 } 1186 1187 return ret; 1188 } 1189 1190 static int r8152_init_common(struct r8152 *tp) 1191 { 1192 u8 speed; 1193 int timeout = 0; 1194 int link_detected; 1195 1196 debug("** %s()\n", __func__); 1197 1198 do { 1199 speed = rtl8152_get_speed(tp); 1200 1201 link_detected = speed & LINK_STATUS; 1202 if (!link_detected) { 1203 if (timeout == 0) 1204 printf("Waiting for Ethernet connection... "); 1205 mdelay(TIMEOUT_RESOLUTION); 1206 timeout += TIMEOUT_RESOLUTION; 1207 } 1208 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 1209 if (link_detected) { 1210 tp->rtl_ops.enable(tp); 1211 1212 if (timeout != 0) 1213 printf("done.\n"); 1214 } else { 1215 printf("unable to connect.\n"); 1216 } 1217 1218 return 0; 1219 } 1220 1221 static int r8152_send_common(struct ueth_data *ueth, void *packet, int length) 1222 { 1223 struct usb_device *udev = ueth->pusb_dev; 1224 u32 opts1, opts2 = 0; 1225 int err; 1226 int actual_len; 1227 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg, 1228 PKTSIZE + sizeof(struct tx_desc)); 1229 struct tx_desc *tx_desc = (struct tx_desc *)msg; 1230 1231 debug("** %s(), len %d\n", __func__, length); 1232 1233 opts1 = length | TX_FS | TX_LS; 1234 1235 tx_desc->opts2 = cpu_to_le32(opts2); 1236 tx_desc->opts1 = cpu_to_le32(opts1); 1237 1238 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length); 1239 1240 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out), 1241 (void *)msg, length + sizeof(struct tx_desc), 1242 &actual_len, USB_BULK_SEND_TIMEOUT); 1243 debug("Tx: len = %zu, actual = %u, err = %d\n", 1244 length + sizeof(struct tx_desc), actual_len, err); 1245 1246 return err; 1247 } 1248 1249 #ifndef CONFIG_DM_ETH 1250 static int r8152_init(struct eth_device *eth, bd_t *bd) 1251 { 1252 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1253 struct r8152 *tp = (struct r8152 *)dev->dev_priv; 1254 1255 return r8152_init_common(tp); 1256 } 1257 1258 static int r8152_send(struct eth_device *eth, void *packet, int length) 1259 { 1260 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1261 1262 return r8152_send_common(dev, packet, length); 1263 } 1264 1265 static int r8152_recv(struct eth_device *eth) 1266 { 1267 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1268 1269 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ); 1270 unsigned char *pkt_ptr; 1271 int err; 1272 int actual_len; 1273 u16 packet_len; 1274 1275 u32 bytes_process = 0; 1276 struct rx_desc *rx_desc; 1277 1278 debug("** %s()\n", __func__); 1279 1280 err = usb_bulk_msg(dev->pusb_dev, 1281 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 1282 (void *)recv_buf, 1283 RTL8152_AGG_BUF_SZ, 1284 &actual_len, 1285 USB_BULK_RECV_TIMEOUT); 1286 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ, 1287 actual_len, err); 1288 if (err != 0) { 1289 debug("Rx: failed to receive\n"); 1290 return -1; 1291 } 1292 if (actual_len > RTL8152_AGG_BUF_SZ) { 1293 debug("Rx: received too many bytes %d\n", actual_len); 1294 return -1; 1295 } 1296 1297 while (bytes_process < actual_len) { 1298 rx_desc = (struct rx_desc *)(recv_buf + bytes_process); 1299 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process; 1300 1301 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1302 packet_len -= CRC_SIZE; 1303 1304 net_process_received_packet(pkt_ptr, packet_len); 1305 1306 bytes_process += 1307 (packet_len + sizeof(struct rx_desc) + CRC_SIZE); 1308 1309 if (bytes_process % 8) 1310 bytes_process = bytes_process + 8 - (bytes_process % 8); 1311 } 1312 1313 return 0; 1314 } 1315 1316 static void r8152_halt(struct eth_device *eth) 1317 { 1318 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1319 struct r8152 *tp = (struct r8152 *)dev->dev_priv; 1320 1321 debug("** %s()\n", __func__); 1322 1323 tp->rtl_ops.disable(tp); 1324 } 1325 1326 static int r8152_write_hwaddr(struct eth_device *eth) 1327 { 1328 struct ueth_data *dev = (struct ueth_data *)eth->priv; 1329 struct r8152 *tp = (struct r8152 *)dev->dev_priv; 1330 1331 unsigned char enetaddr[8] = {0}; 1332 1333 memcpy(enetaddr, eth->enetaddr, ETH_ALEN); 1334 1335 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1336 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); 1337 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1338 1339 debug("MAC %pM\n", eth->enetaddr); 1340 return 0; 1341 } 1342 1343 void r8152_eth_before_probe(void) 1344 { 1345 curr_eth_dev = 0; 1346 } 1347 1348 /* Probe to see if a new device is actually an realtek device */ 1349 int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, 1350 struct ueth_data *ss) 1351 { 1352 struct usb_interface *iface; 1353 struct usb_interface_descriptor *iface_desc; 1354 int ep_in_found = 0, ep_out_found = 0; 1355 int i; 1356 1357 struct r8152 *tp; 1358 1359 /* let's examine the device now */ 1360 iface = &dev->config.if_desc[ifnum]; 1361 iface_desc = &dev->config.if_desc[ifnum].desc; 1362 1363 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) { 1364 if (dev->descriptor.idVendor == r8152_dongles[i].vendor && 1365 dev->descriptor.idProduct == r8152_dongles[i].product) 1366 /* Found a supported dongle */ 1367 break; 1368 } 1369 1370 if (i == ARRAY_SIZE(r8152_dongles)) 1371 return 0; 1372 1373 memset(ss, 0, sizeof(struct ueth_data)); 1374 1375 /* At this point, we know we've got a live one */ 1376 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 1377 dev->descriptor.idVendor, dev->descriptor.idProduct); 1378 1379 /* Initialize the ueth_data structure with some useful info */ 1380 ss->ifnum = ifnum; 1381 ss->pusb_dev = dev; 1382 ss->subclass = iface_desc->bInterfaceSubClass; 1383 ss->protocol = iface_desc->bInterfaceProtocol; 1384 1385 /* alloc driver private */ 1386 ss->dev_priv = calloc(1, sizeof(struct r8152)); 1387 1388 if (!ss->dev_priv) 1389 return 0; 1390 1391 /* 1392 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 1393 * int. We will ignore any others. 1394 */ 1395 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 1396 /* is it an BULK endpoint? */ 1397 if ((iface->ep_desc[i].bmAttributes & 1398 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 1399 u8 ep_addr = iface->ep_desc[i].bEndpointAddress; 1400 if ((ep_addr & USB_DIR_IN) && !ep_in_found) { 1401 ss->ep_in = ep_addr & 1402 USB_ENDPOINT_NUMBER_MASK; 1403 ep_in_found = 1; 1404 } else { 1405 if (!ep_out_found) { 1406 ss->ep_out = ep_addr & 1407 USB_ENDPOINT_NUMBER_MASK; 1408 ep_out_found = 1; 1409 } 1410 } 1411 } 1412 1413 /* is it an interrupt endpoint? */ 1414 if ((iface->ep_desc[i].bmAttributes & 1415 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 1416 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 1417 USB_ENDPOINT_NUMBER_MASK; 1418 ss->irqinterval = iface->ep_desc[i].bInterval; 1419 } 1420 } 1421 1422 debug("Endpoints In %d Out %d Int %d\n", 1423 ss->ep_in, ss->ep_out, ss->ep_int); 1424 1425 /* Do some basic sanity checks, and bail if we find a problem */ 1426 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 1427 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 1428 debug("Problems with device\n"); 1429 return 0; 1430 } 1431 1432 dev->privptr = (void *)ss; 1433 1434 tp = ss->dev_priv; 1435 tp->udev = dev; 1436 tp->intf = iface; 1437 1438 r8152b_get_version(tp); 1439 1440 if (rtl_ops_init(tp)) 1441 return 0; 1442 1443 tp->rtl_ops.init(tp); 1444 tp->rtl_ops.up(tp); 1445 1446 rtl8152_set_speed(tp, AUTONEG_ENABLE, 1447 tp->supports_gmii ? SPEED_1000 : SPEED_100, 1448 DUPLEX_FULL); 1449 1450 return 1; 1451 } 1452 1453 int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 1454 struct eth_device *eth) 1455 { 1456 if (!eth) { 1457 debug("%s: missing parameter.\n", __func__); 1458 return 0; 1459 } 1460 1461 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++); 1462 eth->init = r8152_init; 1463 eth->send = r8152_send; 1464 eth->recv = r8152_recv; 1465 eth->halt = r8152_halt; 1466 eth->write_hwaddr = r8152_write_hwaddr; 1467 eth->priv = ss; 1468 1469 /* Get the MAC address */ 1470 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0) 1471 return 0; 1472 1473 debug("MAC %pM\n", eth->enetaddr); 1474 return 1; 1475 } 1476 #endif /* !CONFIG_DM_ETH */ 1477 1478 #ifdef CONFIG_DM_ETH 1479 static int r8152_eth_start(struct udevice *dev) 1480 { 1481 struct r8152 *tp = dev_get_priv(dev); 1482 1483 debug("** %s (%d)\n", __func__, __LINE__); 1484 1485 return r8152_init_common(tp); 1486 } 1487 1488 void r8152_eth_stop(struct udevice *dev) 1489 { 1490 struct r8152 *tp = dev_get_priv(dev); 1491 1492 debug("** %s (%d)\n", __func__, __LINE__); 1493 1494 tp->rtl_ops.disable(tp); 1495 } 1496 1497 int r8152_eth_send(struct udevice *dev, void *packet, int length) 1498 { 1499 struct r8152 *tp = dev_get_priv(dev); 1500 1501 return r8152_send_common(&tp->ueth, packet, length); 1502 } 1503 1504 int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp) 1505 { 1506 struct r8152 *tp = dev_get_priv(dev); 1507 struct ueth_data *ueth = &tp->ueth; 1508 uint8_t *ptr; 1509 int ret, len; 1510 struct rx_desc *rx_desc; 1511 u16 packet_len; 1512 1513 len = usb_ether_get_rx_bytes(ueth, &ptr); 1514 debug("%s: first try, len=%d\n", __func__, len); 1515 if (!len) { 1516 if (!(flags & ETH_RECV_CHECK_DEVICE)) 1517 return -EAGAIN; 1518 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ); 1519 if (ret) 1520 return ret; 1521 1522 len = usb_ether_get_rx_bytes(ueth, &ptr); 1523 debug("%s: second try, len=%d\n", __func__, len); 1524 } 1525 1526 rx_desc = (struct rx_desc *)ptr; 1527 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1528 packet_len -= CRC_SIZE; 1529 1530 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) { 1531 debug("Rx: too large packet: %d\n", packet_len); 1532 goto err; 1533 } 1534 1535 *packetp = ptr + sizeof(struct rx_desc); 1536 return packet_len; 1537 1538 err: 1539 usb_ether_advance_rxbuf(ueth, -1); 1540 return -ENOSPC; 1541 } 1542 1543 static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len) 1544 { 1545 struct r8152 *tp = dev_get_priv(dev); 1546 1547 packet_len += sizeof(struct rx_desc) + CRC_SIZE; 1548 packet_len = ALIGN(packet_len, 8); 1549 usb_ether_advance_rxbuf(&tp->ueth, packet_len); 1550 1551 return 0; 1552 } 1553 1554 static int r8152_write_hwaddr(struct udevice *dev) 1555 { 1556 struct eth_pdata *pdata = dev_get_platdata(dev); 1557 struct r8152 *tp = dev_get_priv(dev); 1558 1559 unsigned char enetaddr[8] = { 0 }; 1560 1561 debug("** %s (%d)\n", __func__, __LINE__); 1562 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN); 1563 1564 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1565 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); 1566 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1567 1568 debug("MAC %pM\n", pdata->enetaddr); 1569 return 0; 1570 } 1571 1572 int r8152_read_rom_hwaddr(struct udevice *dev) 1573 { 1574 struct eth_pdata *pdata = dev_get_platdata(dev); 1575 struct r8152 *tp = dev_get_priv(dev); 1576 1577 debug("** %s (%d)\n", __func__, __LINE__); 1578 r8152_read_mac(tp, pdata->enetaddr); 1579 return 0; 1580 } 1581 1582 static int r8152_eth_probe(struct udevice *dev) 1583 { 1584 struct usb_device *udev = dev_get_parent_priv(dev); 1585 struct eth_pdata *pdata = dev_get_platdata(dev); 1586 struct r8152 *tp = dev_get_priv(dev); 1587 struct ueth_data *ueth = &tp->ueth; 1588 int ret; 1589 1590 tp->udev = udev; 1591 r8152_read_mac(tp, pdata->enetaddr); 1592 1593 r8152b_get_version(tp); 1594 1595 ret = rtl_ops_init(tp); 1596 if (ret) 1597 return ret; 1598 1599 tp->rtl_ops.init(tp); 1600 tp->rtl_ops.up(tp); 1601 1602 rtl8152_set_speed(tp, AUTONEG_ENABLE, 1603 tp->supports_gmii ? SPEED_1000 : SPEED_100, 1604 DUPLEX_FULL); 1605 1606 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ); 1607 } 1608 1609 static const struct eth_ops r8152_eth_ops = { 1610 .start = r8152_eth_start, 1611 .send = r8152_eth_send, 1612 .recv = r8152_eth_recv, 1613 .free_pkt = r8152_free_pkt, 1614 .stop = r8152_eth_stop, 1615 .write_hwaddr = r8152_write_hwaddr, 1616 .read_rom_hwaddr = r8152_read_rom_hwaddr, 1617 }; 1618 1619 U_BOOT_DRIVER(r8152_eth) = { 1620 .name = "r8152_eth", 1621 .id = UCLASS_ETH, 1622 .probe = r8152_eth_probe, 1623 .ops = &r8152_eth_ops, 1624 .priv_auto_alloc_size = sizeof(struct r8152), 1625 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1626 }; 1627 1628 static const struct usb_device_id r8152_eth_id_table[] = { 1629 /* Realtek */ 1630 { USB_DEVICE(0x0bda, 0x8050) }, 1631 { USB_DEVICE(0x0bda, 0x8152) }, 1632 { USB_DEVICE(0x0bda, 0x8153) }, 1633 1634 /* Samsung */ 1635 { USB_DEVICE(0x04e8, 0xa101) }, 1636 1637 /* Lenovo */ 1638 { USB_DEVICE(0x17ef, 0x304f) }, 1639 { USB_DEVICE(0x17ef, 0x3052) }, 1640 { USB_DEVICE(0x17ef, 0x3054) }, 1641 { USB_DEVICE(0x17ef, 0x3057) }, 1642 { USB_DEVICE(0x17ef, 0x7205) }, 1643 { USB_DEVICE(0x17ef, 0x720a) }, 1644 { USB_DEVICE(0x17ef, 0x720b) }, 1645 { USB_DEVICE(0x17ef, 0x720c) }, 1646 1647 /* TP-LINK */ 1648 { USB_DEVICE(0x2357, 0x0601) }, 1649 1650 /* Nvidia */ 1651 { USB_DEVICE(0x0955, 0x09ff) }, 1652 1653 { } /* Terminating entry */ 1654 }; 1655 1656 U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); 1657 #endif /* CONFIG_DM_ETH */ 1658 1659