1 /* 2 * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <console.h> 8 #include <watchdog.h> 9 10 /* USB Vendor Requests */ 11 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 12 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 13 #define USB_VENDOR_REQUEST_GET_STATS 0xA2 14 15 /* Tx Command A */ 16 #define TX_CMD_A_FCS BIT(22) 17 #define TX_CMD_A_LEN_MASK 0x000FFFFF 18 19 /* Rx Command A */ 20 #define RX_CMD_A_RXE BIT(18) 21 #define RX_CMD_A_LEN_MASK 0x00003FFF 22 23 /* SCSRs */ 24 #define ID_REV 0x00 25 #define ID_REV_CHIP_ID_MASK 0xFFFF0000 26 #define ID_REV_CHIP_ID_7500 0x7500 27 #define ID_REV_CHIP_ID_7800 0x7800 28 #define ID_REV_CHIP_ID_7850 0x7850 29 30 #define INT_STS 0x0C 31 32 #define HW_CFG 0x010 33 #define HW_CFG_LRST BIT(1) 34 35 #define PMT_CTL 0x014 36 #define PMT_CTL_PHY_PWRUP BIT(10) 37 #define PMT_CTL_READY BIT(7) 38 #define PMT_CTL_PHY_RST BIT(4) 39 40 #define E2P_CMD 0x040 41 #define E2P_CMD_EPC_BUSY BIT(31) 42 #define E2P_CMD_EPC_CMD_READ 0x00000000 43 #define E2P_CMD_EPC_TIMEOUT BIT(10) 44 #define E2P_CMD_EPC_ADDR_MASK 0x000001FF 45 46 #define E2P_DATA 0x044 47 48 #define RFE_CTL_BCAST_EN BIT(10) 49 #define RFE_CTL_DA_PERFECT BIT(1) 50 51 #define FCT_RX_CTL_EN BIT(31) 52 53 #define FCT_TX_CTL_EN BIT(31) 54 55 #define MAC_CR 0x100 56 #define MAC_CR_ADP BIT(13) 57 #define MAC_CR_AUTO_DUPLEX BIT(12) 58 #define MAC_CR_AUTO_SPEED BIT(11) 59 60 #define MAC_RX 0x104 61 #define MAC_RX_FCS_STRIP BIT(4) 62 #define MAC_RX_RXEN BIT(0) 63 64 #define MAC_TX 0x108 65 #define MAC_TX_TXEN BIT(0) 66 67 #define FLOW 0x10C 68 #define FLOW_CR_TX_FCEN BIT(30) 69 #define FLOW_CR_RX_FCEN BIT(29) 70 71 #define RX_ADDRH 0x118 72 #define RX_ADDRL 0x11C 73 74 #define MII_ACC 0x120 75 #define MII_ACC_MII_READ 0x00000000 76 #define MII_ACC_MII_WRITE 0x00000002 77 #define MII_ACC_MII_BUSY BIT(0) 78 79 #define MII_DATA 0x124 80 81 #define SS_USB_PKT_SIZE 1024 82 #define HS_USB_PKT_SIZE 512 83 #define FS_USB_PKT_SIZE 64 84 85 #define MAX_RX_FIFO_SIZE (12 * 1024) 86 #define MAX_TX_FIFO_SIZE (12 * 1024) 87 #define DEFAULT_BULK_IN_DELAY 0x0800 88 89 #define EEPROM_INDICATOR 0xA5 90 #define EEPROM_MAC_OFFSET 0x01 91 92 /* Some extra defines */ 93 #define LAN7X_INTERNAL_PHY_ID 1 94 95 #define LAN7X_MAC_RX_MAX_SIZE(mtu) \ 96 ((mtu) << 16) /* Max frame size */ 97 #define LAN7X_MAC_RX_MAX_SIZE_DEFAULT \ 98 LAN7X_MAC_RX_MAX_SIZE(ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */) 99 100 /* Timeouts */ 101 #define USB_CTRL_SET_TIMEOUT_MS 5000 102 #define USB_CTRL_GET_TIMEOUT_MS 5000 103 #define USB_BULK_SEND_TIMEOUT_MS 5000 104 #define USB_BULK_RECV_TIMEOUT_MS 5000 105 #define TIMEOUT_RESOLUTION_MS 50 106 #define PHY_CONNECT_TIMEOUT_MS 5000 107 108 #define RX_URB_SIZE 2048 109 110 /* driver private */ 111 struct lan7x_private { 112 struct ueth_data ueth; 113 u32 chipid; /* Chip or device ID */ 114 struct mii_dev *mdiobus; 115 struct phy_device *phydev; 116 }; 117 118 /* 119 * Lan7x infrastructure commands 120 */ 121 122 int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data); 123 124 int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data); 125 126 static inline int lan7x_wait_for_bit(struct usb_device *udev, 127 const char *prefix, const u32 reg, 128 const u32 mask, const bool set, 129 const unsigned int timeout_ms, 130 const bool breakable) 131 { 132 u32 val; 133 unsigned long start = get_timer(0); 134 135 while (1) { 136 lan7x_read_reg(udev, reg, &val); 137 138 if (!set) 139 val = ~val; 140 141 if ((val & mask) == mask) 142 return 0; 143 144 if (get_timer(start) > timeout_ms) 145 break; 146 147 if (breakable && ctrlc()) { 148 puts("Abort\n"); 149 return -EINTR; 150 } 151 152 udelay(1); 153 WATCHDOG_RESET(); 154 } 155 156 debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg, 157 mask, set); 158 159 return -ETIMEDOUT; 160 } 161 162 int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx); 163 164 void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, 165 int regval); 166 167 static inline int lan7x_mdio_wait_for_bit(struct usb_device *udev, 168 const char *prefix, 169 int phy_id, const u32 reg, 170 const u32 mask, const bool set, 171 const unsigned int timeout_ms, 172 const bool breakable) 173 { 174 u32 val; 175 unsigned long start = get_timer(0); 176 177 while (1) { 178 val = lan7x_mdio_read(udev, phy_id, reg); 179 180 if (!set) 181 val = ~val; 182 183 if ((val & mask) == mask) 184 return 0; 185 186 if (get_timer(start) > timeout_ms) 187 break; 188 189 if (breakable && ctrlc()) { 190 puts("Abort\n"); 191 return -EINTR; 192 } 193 194 udelay(1); 195 WATCHDOG_RESET(); 196 } 197 198 debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg, 199 mask, set); 200 201 return -ETIMEDOUT; 202 } 203 204 int lan7x_phylib_register(struct udevice *udev); 205 206 int lan7x_eth_phylib_connect(struct udevice *udev, struct ueth_data *dev); 207 208 int lan7x_eth_phylib_config_start(struct udevice *udev); 209 210 int lan7x_pmt_phy_reset(struct usb_device *udev, 211 struct ueth_data *dev); 212 213 int lan7x_update_flowcontrol(struct usb_device *udev, 214 struct ueth_data *dev, 215 uint32_t *flow, uint32_t *fct_flow); 216 217 int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev); 218 219 int lan7x_basic_reset(struct usb_device *udev, 220 struct ueth_data *dev); 221 222 void lan7x_eth_stop(struct udevice *dev); 223 224 int lan7x_eth_send(struct udevice *dev, void *packet, int length); 225 226 int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp); 227 228 int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len); 229 230 int lan7x_eth_remove(struct udevice *dev); 231