1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (c) 2017 Microchip Technology Inc. All rights reserved.
4 */
5
6 #include <console.h>
7 #include <watchdog.h>
8
9 /* USB Vendor Requests */
10 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
11 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
12 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
13
14 /* Tx Command A */
15 #define TX_CMD_A_FCS BIT(22)
16 #define TX_CMD_A_LEN_MASK 0x000FFFFF
17
18 /* Rx Command A */
19 #define RX_CMD_A_RXE BIT(18)
20 #define RX_CMD_A_LEN_MASK 0x00003FFF
21
22 /* SCSRs */
23 #define ID_REV 0x00
24 #define ID_REV_CHIP_ID_MASK 0xFFFF0000
25 #define ID_REV_CHIP_ID_7500 0x7500
26 #define ID_REV_CHIP_ID_7800 0x7800
27 #define ID_REV_CHIP_ID_7850 0x7850
28
29 #define INT_STS 0x0C
30
31 #define HW_CFG 0x010
32 #define HW_CFG_LRST BIT(1)
33
34 #define PMT_CTL 0x014
35 #define PMT_CTL_PHY_PWRUP BIT(10)
36 #define PMT_CTL_READY BIT(7)
37 #define PMT_CTL_PHY_RST BIT(4)
38
39 #define E2P_CMD 0x040
40 #define E2P_CMD_EPC_BUSY BIT(31)
41 #define E2P_CMD_EPC_CMD_READ 0x00000000
42 #define E2P_CMD_EPC_TIMEOUT BIT(10)
43 #define E2P_CMD_EPC_ADDR_MASK 0x000001FF
44
45 #define E2P_DATA 0x044
46
47 #define RFE_CTL_BCAST_EN BIT(10)
48 #define RFE_CTL_DA_PERFECT BIT(1)
49
50 #define FCT_RX_CTL_EN BIT(31)
51
52 #define FCT_TX_CTL_EN BIT(31)
53
54 #define MAC_CR 0x100
55 #define MAC_CR_ADP BIT(13)
56 #define MAC_CR_AUTO_DUPLEX BIT(12)
57 #define MAC_CR_AUTO_SPEED BIT(11)
58
59 #define MAC_RX 0x104
60 #define MAC_RX_FCS_STRIP BIT(4)
61 #define MAC_RX_RXEN BIT(0)
62
63 #define MAC_TX 0x108
64 #define MAC_TX_TXEN BIT(0)
65
66 #define FLOW 0x10C
67 #define FLOW_CR_TX_FCEN BIT(30)
68 #define FLOW_CR_RX_FCEN BIT(29)
69
70 #define RX_ADDRH 0x118
71 #define RX_ADDRL 0x11C
72
73 #define MII_ACC 0x120
74 #define MII_ACC_MII_READ 0x00000000
75 #define MII_ACC_MII_WRITE 0x00000002
76 #define MII_ACC_MII_BUSY BIT(0)
77
78 #define MII_DATA 0x124
79
80 #define SS_USB_PKT_SIZE 1024
81 #define HS_USB_PKT_SIZE 512
82 #define FS_USB_PKT_SIZE 64
83
84 #define MAX_RX_FIFO_SIZE (12 * 1024)
85 #define MAX_TX_FIFO_SIZE (12 * 1024)
86 #define DEFAULT_BULK_IN_DELAY 0x0800
87
88 #define EEPROM_INDICATOR 0xA5
89 #define EEPROM_MAC_OFFSET 0x01
90
91 /* Some extra defines */
92 #define LAN7X_INTERNAL_PHY_ID 1
93
94 #define LAN7X_MAC_RX_MAX_SIZE(mtu) \
95 ((mtu) << 16) /* Max frame size */
96 #define LAN7X_MAC_RX_MAX_SIZE_DEFAULT \
97 LAN7X_MAC_RX_MAX_SIZE(PKTSIZE_ALIGN + 4 /* VLAN */ + 4 /* CRC */)
98
99 /* Timeouts */
100 #define USB_CTRL_SET_TIMEOUT_MS 5000
101 #define USB_CTRL_GET_TIMEOUT_MS 5000
102 #define USB_BULK_SEND_TIMEOUT_MS 5000
103 #define USB_BULK_RECV_TIMEOUT_MS 5000
104 #define TIMEOUT_RESOLUTION_MS 50
105 #define PHY_CONNECT_TIMEOUT_MS 5000
106
107 #define RX_URB_SIZE 2048
108
109 /* driver private */
110 struct lan7x_private {
111 struct ueth_data ueth;
112 u32 chipid; /* Chip or device ID */
113 struct mii_dev *mdiobus;
114 struct phy_device *phydev;
115 };
116
117 /*
118 * Lan7x infrastructure commands
119 */
120
121 int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data);
122
123 int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data);
124
lan7x_wait_for_bit(struct usb_device * udev,const char * prefix,const u32 reg,const u32 mask,const bool set,const unsigned int timeout_ms,const bool breakable)125 static inline int lan7x_wait_for_bit(struct usb_device *udev,
126 const char *prefix, const u32 reg,
127 const u32 mask, const bool set,
128 const unsigned int timeout_ms,
129 const bool breakable)
130 {
131 u32 val;
132 unsigned long start = get_timer(0);
133
134 while (1) {
135 lan7x_read_reg(udev, reg, &val);
136
137 if (!set)
138 val = ~val;
139
140 if ((val & mask) == mask)
141 return 0;
142
143 if (get_timer(start) > timeout_ms)
144 break;
145
146 if (breakable && ctrlc()) {
147 puts("Abort\n");
148 return -EINTR;
149 }
150
151 udelay(1);
152 WATCHDOG_RESET();
153 }
154
155 debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,
156 mask, set);
157
158 return -ETIMEDOUT;
159 }
160
161 int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx);
162
163 void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx,
164 int regval);
165
lan7x_mdio_wait_for_bit(struct usb_device * udev,const char * prefix,int phy_id,const u32 reg,const u32 mask,const bool set,const unsigned int timeout_ms,const bool breakable)166 static inline int lan7x_mdio_wait_for_bit(struct usb_device *udev,
167 const char *prefix,
168 int phy_id, const u32 reg,
169 const u32 mask, const bool set,
170 const unsigned int timeout_ms,
171 const bool breakable)
172 {
173 u32 val;
174 unsigned long start = get_timer(0);
175
176 while (1) {
177 val = lan7x_mdio_read(udev, phy_id, reg);
178
179 if (!set)
180 val = ~val;
181
182 if ((val & mask) == mask)
183 return 0;
184
185 if (get_timer(start) > timeout_ms)
186 break;
187
188 if (breakable && ctrlc()) {
189 puts("Abort\n");
190 return -EINTR;
191 }
192
193 udelay(1);
194 WATCHDOG_RESET();
195 }
196
197 debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,
198 mask, set);
199
200 return -ETIMEDOUT;
201 }
202
203 int lan7x_phylib_register(struct udevice *udev);
204
205 int lan7x_eth_phylib_connect(struct udevice *udev, struct ueth_data *dev);
206
207 int lan7x_eth_phylib_config_start(struct udevice *udev);
208
209 int lan7x_pmt_phy_reset(struct usb_device *udev,
210 struct ueth_data *dev);
211
212 int lan7x_update_flowcontrol(struct usb_device *udev,
213 struct ueth_data *dev,
214 uint32_t *flow, uint32_t *fct_flow);
215
216 int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev);
217
218 int lan7x_basic_reset(struct usb_device *udev,
219 struct ueth_data *dev);
220
221 void lan7x_eth_stop(struct udevice *dev);
222
223 int lan7x_eth_send(struct udevice *dev, void *packet, int length);
224
225 int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp);
226
227 int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len);
228
229 int lan7x_eth_remove(struct udevice *dev);
230