1 /* 2 * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de> 3 * based on the U-Boot Asix driver as well as information 4 * from the Linux AX88179_178a driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <usb.h> 11 #include <net.h> 12 #include <linux/mii.h> 13 #include "usb_ether.h" 14 #include <malloc.h> 15 #include <errno.h> 16 17 /* ASIX AX88179 based USB 3.0 Ethernet Devices */ 18 #define AX88179_PHY_ID 0x03 19 #define AX_EEPROM_LEN 0x100 20 #define AX88179_EEPROM_MAGIC 0x17900b95 21 #define AX_MCAST_FLTSIZE 8 22 #define AX_MAX_MCAST 64 23 #define AX_INT_PPLS_LINK (1 << 16) 24 #define AX_RXHDR_L4_TYPE_MASK 0x1c 25 #define AX_RXHDR_L4_TYPE_UDP 4 26 #define AX_RXHDR_L4_TYPE_TCP 16 27 #define AX_RXHDR_L3CSUM_ERR 2 28 #define AX_RXHDR_L4CSUM_ERR 1 29 #define AX_RXHDR_CRC_ERR (1 << 29) 30 #define AX_RXHDR_DROP_ERR (1 << 31) 31 #define AX_ENDPOINT_INT 0x01 32 #define AX_ENDPOINT_IN 0x02 33 #define AX_ENDPOINT_OUT 0x03 34 #define AX_ACCESS_MAC 0x01 35 #define AX_ACCESS_PHY 0x02 36 #define AX_ACCESS_EEPROM 0x04 37 #define AX_ACCESS_EFUS 0x05 38 #define AX_PAUSE_WATERLVL_HIGH 0x54 39 #define AX_PAUSE_WATERLVL_LOW 0x55 40 41 #define PHYSICAL_LINK_STATUS 0x02 42 #define AX_USB_SS (1 << 2) 43 #define AX_USB_HS (1 << 1) 44 45 #define GENERAL_STATUS 0x03 46 #define AX_SECLD (1 << 2) 47 48 #define AX_SROM_ADDR 0x07 49 #define AX_SROM_CMD 0x0a 50 #define EEP_RD (1 << 2) 51 #define EEP_BUSY (1 << 4) 52 53 #define AX_SROM_DATA_LOW 0x08 54 #define AX_SROM_DATA_HIGH 0x09 55 56 #define AX_RX_CTL 0x0b 57 #define AX_RX_CTL_DROPCRCERR (1 << 8) 58 #define AX_RX_CTL_IPE (1 << 9) 59 #define AX_RX_CTL_START (1 << 7) 60 #define AX_RX_CTL_AP (1 << 5) 61 #define AX_RX_CTL_AM (1 << 4) 62 #define AX_RX_CTL_AB (1 << 3) 63 #define AX_RX_CTL_AMALL (1 << 1) 64 #define AX_RX_CTL_PRO (1 << 0) 65 #define AX_RX_CTL_STOP 0 66 67 #define AX_NODE_ID 0x10 68 #define AX_MULFLTARY 0x16 69 70 #define AX_MEDIUM_STATUS_MODE 0x22 71 #define AX_MEDIUM_GIGAMODE (1 << 0) 72 #define AX_MEDIUM_FULL_DUPLEX (1 << 1) 73 #define AX_MEDIUM_EN_125MHZ (1 << 3) 74 #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) 75 #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) 76 #define AX_MEDIUM_RECEIVE_EN (1 << 8) 77 #define AX_MEDIUM_PS (1 << 9) 78 #define AX_MEDIUM_JUMBO_EN 0x8040 79 80 #define AX_MONITOR_MOD 0x24 81 #define AX_MONITOR_MODE_RWLC (1 << 1) 82 #define AX_MONITOR_MODE_RWMP (1 << 2) 83 #define AX_MONITOR_MODE_PMEPOL (1 << 5) 84 #define AX_MONITOR_MODE_PMETYPE (1 << 6) 85 86 #define AX_GPIO_CTRL 0x25 87 #define AX_GPIO_CTRL_GPIO3EN (1 << 7) 88 #define AX_GPIO_CTRL_GPIO2EN (1 << 6) 89 #define AX_GPIO_CTRL_GPIO1EN (1 << 5) 90 91 #define AX_PHYPWR_RSTCTL 0x26 92 #define AX_PHYPWR_RSTCTL_BZ (1 << 4) 93 #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) 94 #define AX_PHYPWR_RSTCTL_AT (1 << 12) 95 96 #define AX_RX_BULKIN_QCTRL 0x2e 97 #define AX_CLK_SELECT 0x33 98 #define AX_CLK_SELECT_BCS (1 << 0) 99 #define AX_CLK_SELECT_ACS (1 << 1) 100 #define AX_CLK_SELECT_ULR (1 << 3) 101 102 #define AX_RXCOE_CTL 0x34 103 #define AX_RXCOE_IP (1 << 0) 104 #define AX_RXCOE_TCP (1 << 1) 105 #define AX_RXCOE_UDP (1 << 2) 106 #define AX_RXCOE_TCPV6 (1 << 5) 107 #define AX_RXCOE_UDPV6 (1 << 6) 108 109 #define AX_TXCOE_CTL 0x35 110 #define AX_TXCOE_IP (1 << 0) 111 #define AX_TXCOE_TCP (1 << 1) 112 #define AX_TXCOE_UDP (1 << 2) 113 #define AX_TXCOE_TCPV6 (1 << 5) 114 #define AX_TXCOE_UDPV6 (1 << 6) 115 116 #define AX_LEDCTRL 0x73 117 118 #define GMII_PHY_PHYSR 0x11 119 #define GMII_PHY_PHYSR_SMASK 0xc000 120 #define GMII_PHY_PHYSR_GIGA (1 << 15) 121 #define GMII_PHY_PHYSR_100 (1 << 14) 122 #define GMII_PHY_PHYSR_FULL (1 << 13) 123 #define GMII_PHY_PHYSR_LINK (1 << 10) 124 125 #define GMII_LED_ACT 0x1a 126 #define GMII_LED_ACTIVE_MASK 0xff8f 127 #define GMII_LED0_ACTIVE (1 << 4) 128 #define GMII_LED1_ACTIVE (1 << 5) 129 #define GMII_LED2_ACTIVE (1 << 6) 130 131 #define GMII_LED_LINK 0x1c 132 #define GMII_LED_LINK_MASK 0xf888 133 #define GMII_LED0_LINK_10 (1 << 0) 134 #define GMII_LED0_LINK_100 (1 << 1) 135 #define GMII_LED0_LINK_1000 (1 << 2) 136 #define GMII_LED1_LINK_10 (1 << 4) 137 #define GMII_LED1_LINK_100 (1 << 5) 138 #define GMII_LED1_LINK_1000 (1 << 6) 139 #define GMII_LED2_LINK_10 (1 << 8) 140 #define GMII_LED2_LINK_100 (1 << 9) 141 #define GMII_LED2_LINK_1000 (1 << 10) 142 #define LED0_ACTIVE (1 << 0) 143 #define LED0_LINK_10 (1 << 1) 144 #define LED0_LINK_100 (1 << 2) 145 #define LED0_LINK_1000 (1 << 3) 146 #define LED0_FD (1 << 4) 147 #define LED0_USB3_MASK 0x001f 148 #define LED1_ACTIVE (1 << 5) 149 #define LED1_LINK_10 (1 << 6) 150 #define LED1_LINK_100 (1 << 7) 151 #define LED1_LINK_1000 (1 << 8) 152 #define LED1_FD (1 << 9) 153 #define LED1_USB3_MASK 0x03e0 154 #define LED2_ACTIVE (1 << 10) 155 #define LED2_LINK_1000 (1 << 13) 156 #define LED2_LINK_100 (1 << 12) 157 #define LED2_LINK_10 (1 << 11) 158 #define LED2_FD (1 << 14) 159 #define LED_VALID (1 << 15) 160 #define LED2_USB3_MASK 0x7c00 161 162 #define GMII_PHYPAGE 0x1e 163 #define GMII_PHY_PAGE_SELECT 0x1f 164 #define GMII_PHY_PGSEL_EXT 0x0007 165 #define GMII_PHY_PGSEL_PAGE0 0x0000 166 167 /* local defines */ 168 #define ASIX_BASE_NAME "axg" 169 #define USB_CTRL_SET_TIMEOUT 5000 170 #define USB_CTRL_GET_TIMEOUT 5000 171 #define USB_BULK_SEND_TIMEOUT 5000 172 #define USB_BULK_RECV_TIMEOUT 5000 173 174 #define AX_RX_URB_SIZE 1024 * 0x12 175 #define BLK_FRAME_SIZE 0x200 176 #define PHY_CONNECT_TIMEOUT 5000 177 178 #define TIMEOUT_RESOLUTION 50 /* ms */ 179 180 #define FLAG_NONE 0 181 #define FLAG_TYPE_AX88179 (1U << 0) 182 #define FLAG_TYPE_AX88178a (1U << 1) 183 #define FLAG_TYPE_DLINK_DUB1312 (1U << 2) 184 #define FLAG_TYPE_SITECOM (1U << 3) 185 #define FLAG_TYPE_SAMSUNG (1U << 4) 186 #define FLAG_TYPE_LENOVO (1U << 5) 187 188 /* local vars */ 189 static const struct { 190 unsigned char ctrl, timer_l, timer_h, size, ifg; 191 } AX88179_BULKIN_SIZE[] = { 192 {7, 0x4f, 0, 0x02, 0xff}, 193 {7, 0x20, 3, 0x03, 0xff}, 194 {7, 0xae, 7, 0x04, 0xff}, 195 {7, 0xcc, 0x4c, 0x04, 8}, 196 }; 197 198 static int curr_eth_dev; /* index for name of next device detected */ 199 200 /* driver private */ 201 struct asix_private { 202 int flags; 203 int rx_urb_size; 204 int maxpacketsize; 205 }; 206 207 /* 208 * Asix infrastructure commands 209 */ 210 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 211 u16 size, void *data) 212 { 213 int len; 214 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 215 216 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 217 cmd, value, index, size); 218 219 memcpy(buf, data, size); 220 221 len = usb_control_msg( 222 dev->pusb_dev, 223 usb_sndctrlpipe(dev->pusb_dev, 0), 224 cmd, 225 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 226 value, 227 index, 228 buf, 229 size, 230 USB_CTRL_SET_TIMEOUT); 231 232 return len == size ? 0 : ECOMM; 233 } 234 235 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 236 u16 size, void *data) 237 { 238 int len; 239 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 240 241 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 242 cmd, value, index, size); 243 244 len = usb_control_msg( 245 dev->pusb_dev, 246 usb_rcvctrlpipe(dev->pusb_dev, 0), 247 cmd, 248 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 249 value, 250 index, 251 buf, 252 size, 253 USB_CTRL_GET_TIMEOUT); 254 255 memcpy(data, buf, size); 256 257 return len == size ? 0 : ECOMM; 258 } 259 260 static int asix_read_mac(struct eth_device *eth) 261 { 262 struct ueth_data *dev = (struct ueth_data *)eth->priv; 263 u8 buf[ETH_ALEN]; 264 265 asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); 266 debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", 267 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); 268 269 memcpy(eth->enetaddr, buf, ETH_ALEN); 270 271 return 0; 272 } 273 274 static int asix_write_mac(struct eth_device *eth) 275 { 276 struct ueth_data *dev = (struct ueth_data *)eth->priv; 277 int ret; 278 279 ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 280 ETH_ALEN, eth->enetaddr); 281 if (ret < 0) 282 debug("Failed to set MAC address: %02x\n", ret); 283 284 return ret; 285 } 286 287 static int asix_basic_reset(struct ueth_data *dev) 288 { 289 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 290 u8 buf[5]; 291 u16 *tmp16; 292 u8 *tmp; 293 294 tmp16 = (u16 *)buf; 295 tmp = (u8 *)buf; 296 297 /* Power up ethernet PHY */ 298 *tmp16 = 0; 299 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 300 301 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 302 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 303 mdelay(200); 304 305 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 306 asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 307 mdelay(200); 308 309 /* RX bulk configuration */ 310 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 311 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 312 313 dev_priv->rx_urb_size = 128 * 20; 314 315 /* Water Level configuration */ 316 *tmp = 0x34; 317 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 318 319 *tmp = 0x52; 320 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp); 321 322 /* Enable checksum offload */ 323 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 324 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 325 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 326 327 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 328 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 329 asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 330 331 /* Configure RX control register => start operation */ 332 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 333 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 334 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 335 336 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 337 AX_MONITOR_MODE_RWMP; 338 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 339 340 /* Configure default medium type => giga */ 341 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 342 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 343 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; 344 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); 345 346 u16 adv = 0; 347 adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | 348 ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; 349 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); 350 351 adv = ADVERTISE_1000FULL; 352 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); 353 354 return 0; 355 } 356 357 static int asix_wait_link(struct ueth_data *dev) 358 { 359 int timeout = 0; 360 int link_detected; 361 u8 buf[2]; 362 u16 *tmp16; 363 364 tmp16 = (u16 *)buf; 365 366 do { 367 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 368 MII_BMSR, 2, buf); 369 link_detected = *tmp16 & BMSR_LSTATUS; 370 if (!link_detected) { 371 if (timeout == 0) 372 printf("Waiting for Ethernet connection... "); 373 mdelay(TIMEOUT_RESOLUTION); 374 timeout += TIMEOUT_RESOLUTION; 375 } 376 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 377 378 if (link_detected) { 379 if (timeout > 0) 380 printf("done.\n"); 381 return 0; 382 } else { 383 printf("unable to connect.\n"); 384 return -ENETUNREACH; 385 } 386 } 387 388 /* 389 * Asix callbacks 390 */ 391 static int asix_init(struct eth_device *eth, bd_t *bd) 392 { 393 struct ueth_data *dev = (struct ueth_data *)eth->priv; 394 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 395 u8 buf[2], tmp[5], link_sts; 396 u16 *tmp16, mode; 397 398 399 tmp16 = (u16 *)buf; 400 401 debug("** %s()\n", __func__); 402 403 /* Configure RX control register => start operation */ 404 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 405 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 406 if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0) 407 goto out_err; 408 409 if (asix_wait_link(dev) != 0) { 410 /*reset device and try again*/ 411 printf("Reset Ethernet Device\n"); 412 asix_basic_reset(dev); 413 if (asix_wait_link(dev) != 0) 414 goto out_err; 415 } 416 417 /* Configure link */ 418 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 419 AX_MEDIUM_RXFLOW_CTRLEN; 420 421 asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 422 1, 1, &link_sts); 423 424 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 425 GMII_PHY_PHYSR, 2, tmp16); 426 427 if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) { 428 return 0; 429 } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 430 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ | 431 AX_MEDIUM_JUMBO_EN; 432 433 if (link_sts & AX_USB_SS) 434 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 435 else if (link_sts & AX_USB_HS) 436 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 437 else 438 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 439 } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 440 mode |= AX_MEDIUM_PS; 441 442 if (link_sts & (AX_USB_SS | AX_USB_HS)) 443 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 444 else 445 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 446 } else { 447 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 448 } 449 450 /* RX bulk configuration */ 451 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 452 453 dev_priv->rx_urb_size = (1024 * (tmp[3] + 2)); 454 if (*tmp16 & GMII_PHY_PHYSR_FULL) 455 mode |= AX_MEDIUM_FULL_DUPLEX; 456 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 457 2, 2, &mode); 458 459 return 0; 460 out_err: 461 return -1; 462 } 463 464 static int asix_send(struct eth_device *eth, void *packet, int length) 465 { 466 struct ueth_data *dev = (struct ueth_data *)eth->priv; 467 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 468 469 int err; 470 u32 packet_len, tx_hdr2; 471 int actual_len, framesize; 472 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 473 PKTSIZE + (2 * sizeof(packet_len))); 474 475 debug("** %s(), len %d\n", __func__, length); 476 477 packet_len = length; 478 cpu_to_le32s(&packet_len); 479 480 memcpy(msg, &packet_len, sizeof(packet_len)); 481 framesize = dev_priv->maxpacketsize; 482 tx_hdr2 = 0; 483 if (((length + 8) % framesize) == 0) 484 tx_hdr2 |= 0x80008000; /* Enable padding */ 485 486 cpu_to_le32s(&tx_hdr2); 487 488 memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2)); 489 490 memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2), 491 (void *)packet, length); 492 493 err = usb_bulk_msg(dev->pusb_dev, 494 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 495 (void *)msg, 496 length + sizeof(packet_len) + sizeof(tx_hdr2), 497 &actual_len, 498 USB_BULK_SEND_TIMEOUT); 499 debug("Tx: len = %u, actual = %u, err = %d\n", 500 length + sizeof(packet_len), actual_len, err); 501 502 return err; 503 } 504 505 static int asix_recv(struct eth_device *eth) 506 { 507 struct ueth_data *dev = (struct ueth_data *)eth->priv; 508 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 509 510 u16 frame_pos; 511 int err; 512 int actual_len; 513 514 int pkt_cnt; 515 u32 rx_hdr; 516 u16 hdr_off; 517 u32 *pkt_hdr; 518 ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size); 519 520 actual_len = -1; 521 522 debug("** %s()\n", __func__); 523 524 err = usb_bulk_msg(dev->pusb_dev, 525 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 526 (void *)recv_buf, 527 dev_priv->rx_urb_size, 528 &actual_len, 529 USB_BULK_RECV_TIMEOUT); 530 debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size, 531 actual_len, err); 532 533 if (err != 0) { 534 debug("Rx: failed to receive\n"); 535 return -ECOMM; 536 } 537 if (actual_len > dev_priv->rx_urb_size) { 538 debug("Rx: received too many bytes %d\n", actual_len); 539 return -EMSGSIZE; 540 } 541 542 543 rx_hdr = *(u32 *)(recv_buf + actual_len - 4); 544 le32_to_cpus(&pkt_hdr); 545 546 pkt_cnt = (u16)rx_hdr; 547 hdr_off = (u16)(rx_hdr >> 16); 548 pkt_hdr = (u32 *)(recv_buf + hdr_off); 549 550 551 frame_pos = 0; 552 553 while (pkt_cnt--) { 554 u16 pkt_len; 555 556 le32_to_cpus(pkt_hdr); 557 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 558 559 frame_pos += 2; 560 561 net_process_received_packet(recv_buf + frame_pos, pkt_len); 562 563 pkt_hdr++; 564 frame_pos += ((pkt_len + 7) & 0xFFF8)-2; 565 566 if (pkt_cnt == 0) 567 return 0; 568 } 569 return err; 570 } 571 572 static void asix_halt(struct eth_device *eth) 573 { 574 debug("** %s()\n", __func__); 575 } 576 577 /* 578 * Asix probing functions 579 */ 580 void ax88179_eth_before_probe(void) 581 { 582 curr_eth_dev = 0; 583 } 584 585 struct asix_dongle { 586 unsigned short vendor; 587 unsigned short product; 588 int flags; 589 }; 590 591 static const struct asix_dongle asix_dongles[] = { 592 { 0x0b95, 0x1790, FLAG_TYPE_AX88179 }, 593 { 0x0b95, 0x178a, FLAG_TYPE_AX88178a }, 594 { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 }, 595 { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, 596 { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, 597 { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, 598 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ 599 }; 600 601 /* Probe to see if a new device is actually an asix device */ 602 int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, 603 struct ueth_data *ss) 604 { 605 struct usb_interface *iface; 606 struct usb_interface_descriptor *iface_desc; 607 struct asix_private *dev_priv; 608 int ep_in_found = 0, ep_out_found = 0; 609 int i; 610 611 /* let's examine the device now */ 612 iface = &dev->config.if_desc[ifnum]; 613 iface_desc = &dev->config.if_desc[ifnum].desc; 614 615 for (i = 0; asix_dongles[i].vendor != 0; i++) { 616 if (dev->descriptor.idVendor == asix_dongles[i].vendor && 617 dev->descriptor.idProduct == asix_dongles[i].product) 618 /* Found a supported dongle */ 619 break; 620 } 621 622 if (asix_dongles[i].vendor == 0) 623 return 0; 624 625 memset(ss, 0, sizeof(struct ueth_data)); 626 627 /* At this point, we know we've got a live one */ 628 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 629 dev->descriptor.idVendor, dev->descriptor.idProduct); 630 631 /* Initialize the ueth_data structure with some useful info */ 632 ss->ifnum = ifnum; 633 ss->pusb_dev = dev; 634 ss->subclass = iface_desc->bInterfaceSubClass; 635 ss->protocol = iface_desc->bInterfaceProtocol; 636 637 /* alloc driver private */ 638 ss->dev_priv = calloc(1, sizeof(struct asix_private)); 639 if (!ss->dev_priv) 640 return 0; 641 dev_priv = ss->dev_priv; 642 dev_priv->flags = asix_dongles[i].flags; 643 644 /* 645 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 646 * int. We will ignore any others. 647 */ 648 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 649 /* is it an interrupt endpoint? */ 650 if ((iface->ep_desc[i].bmAttributes & 651 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 652 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 653 USB_ENDPOINT_NUMBER_MASK; 654 ss->irqinterval = iface->ep_desc[i].bInterval; 655 continue; 656 } 657 658 /* is it an BULK endpoint? */ 659 if (!((iface->ep_desc[i].bmAttributes & 660 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) 661 continue; 662 663 u8 ep_addr = iface->ep_desc[i].bEndpointAddress; 664 if ((ep_addr & USB_DIR_IN) && !ep_in_found) { 665 ss->ep_in = ep_addr & 666 USB_ENDPOINT_NUMBER_MASK; 667 ep_in_found = 1; 668 } 669 if (!(ep_addr & USB_DIR_IN) && !ep_out_found) { 670 ss->ep_out = ep_addr & 671 USB_ENDPOINT_NUMBER_MASK; 672 dev_priv->maxpacketsize = 673 dev->epmaxpacketout[AX_ENDPOINT_OUT]; 674 ep_out_found = 1; 675 } 676 } 677 debug("Endpoints In %d Out %d Int %d\n", 678 ss->ep_in, ss->ep_out, ss->ep_int); 679 680 /* Do some basic sanity checks, and bail if we find a problem */ 681 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 682 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 683 debug("Problems with device\n"); 684 return 0; 685 } 686 dev->privptr = (void *)ss; 687 return 1; 688 } 689 690 int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 691 struct eth_device *eth) 692 { 693 if (!eth) { 694 debug("%s: missing parameter.\n", __func__); 695 return 0; 696 } 697 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); 698 eth->init = asix_init; 699 eth->send = asix_send; 700 eth->recv = asix_recv; 701 eth->halt = asix_halt; 702 eth->write_hwaddr = asix_write_mac; 703 eth->priv = ss; 704 705 if (asix_basic_reset(ss)) 706 return 0; 707 708 /* Get the MAC address */ 709 if (asix_read_mac(eth)) 710 return 0; 711 debug("MAC %pM\n", eth->enetaddr); 712 713 return 1; 714 } 715