1 /* 2 * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de> 3 * based on the U-Boot Asix driver as well as information 4 * from the Linux AX88179_178a driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <usb.h> 11 #include <net.h> 12 #include <linux/mii.h> 13 #include "usb_ether.h" 14 #include <malloc.h> 15 #include <errno.h> 16 17 /* ASIX AX88179 based USB 3.0 Ethernet Devices */ 18 #define AX88179_PHY_ID 0x03 19 #define AX_EEPROM_LEN 0x100 20 #define AX88179_EEPROM_MAGIC 0x17900b95 21 #define AX_MCAST_FLTSIZE 8 22 #define AX_MAX_MCAST 64 23 #define AX_INT_PPLS_LINK (1 << 16) 24 #define AX_RXHDR_L4_TYPE_MASK 0x1c 25 #define AX_RXHDR_L4_TYPE_UDP 4 26 #define AX_RXHDR_L4_TYPE_TCP 16 27 #define AX_RXHDR_L3CSUM_ERR 2 28 #define AX_RXHDR_L4CSUM_ERR 1 29 #define AX_RXHDR_CRC_ERR (1 << 29) 30 #define AX_RXHDR_DROP_ERR (1 << 31) 31 #define AX_ENDPOINT_INT 0x01 32 #define AX_ENDPOINT_IN 0x02 33 #define AX_ENDPOINT_OUT 0x03 34 #define AX_ACCESS_MAC 0x01 35 #define AX_ACCESS_PHY 0x02 36 #define AX_ACCESS_EEPROM 0x04 37 #define AX_ACCESS_EFUS 0x05 38 #define AX_PAUSE_WATERLVL_HIGH 0x54 39 #define AX_PAUSE_WATERLVL_LOW 0x55 40 41 #define PHYSICAL_LINK_STATUS 0x02 42 #define AX_USB_SS (1 << 2) 43 #define AX_USB_HS (1 << 1) 44 45 #define GENERAL_STATUS 0x03 46 #define AX_SECLD (1 << 2) 47 48 #define AX_SROM_ADDR 0x07 49 #define AX_SROM_CMD 0x0a 50 #define EEP_RD (1 << 2) 51 #define EEP_BUSY (1 << 4) 52 53 #define AX_SROM_DATA_LOW 0x08 54 #define AX_SROM_DATA_HIGH 0x09 55 56 #define AX_RX_CTL 0x0b 57 #define AX_RX_CTL_DROPCRCERR (1 << 8) 58 #define AX_RX_CTL_IPE (1 << 9) 59 #define AX_RX_CTL_START (1 << 7) 60 #define AX_RX_CTL_AP (1 << 5) 61 #define AX_RX_CTL_AM (1 << 4) 62 #define AX_RX_CTL_AB (1 << 3) 63 #define AX_RX_CTL_AMALL (1 << 1) 64 #define AX_RX_CTL_PRO (1 << 0) 65 #define AX_RX_CTL_STOP 0 66 67 #define AX_NODE_ID 0x10 68 #define AX_MULFLTARY 0x16 69 70 #define AX_MEDIUM_STATUS_MODE 0x22 71 #define AX_MEDIUM_GIGAMODE (1 << 0) 72 #define AX_MEDIUM_FULL_DUPLEX (1 << 1) 73 #define AX_MEDIUM_EN_125MHZ (1 << 3) 74 #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) 75 #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) 76 #define AX_MEDIUM_RECEIVE_EN (1 << 8) 77 #define AX_MEDIUM_PS (1 << 9) 78 #define AX_MEDIUM_JUMBO_EN 0x8040 79 80 #define AX_MONITOR_MOD 0x24 81 #define AX_MONITOR_MODE_RWLC (1 << 1) 82 #define AX_MONITOR_MODE_RWMP (1 << 2) 83 #define AX_MONITOR_MODE_PMEPOL (1 << 5) 84 #define AX_MONITOR_MODE_PMETYPE (1 << 6) 85 86 #define AX_GPIO_CTRL 0x25 87 #define AX_GPIO_CTRL_GPIO3EN (1 << 7) 88 #define AX_GPIO_CTRL_GPIO2EN (1 << 6) 89 #define AX_GPIO_CTRL_GPIO1EN (1 << 5) 90 91 #define AX_PHYPWR_RSTCTL 0x26 92 #define AX_PHYPWR_RSTCTL_BZ (1 << 4) 93 #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) 94 #define AX_PHYPWR_RSTCTL_AT (1 << 12) 95 96 #define AX_RX_BULKIN_QCTRL 0x2e 97 #define AX_CLK_SELECT 0x33 98 #define AX_CLK_SELECT_BCS (1 << 0) 99 #define AX_CLK_SELECT_ACS (1 << 1) 100 #define AX_CLK_SELECT_ULR (1 << 3) 101 102 #define AX_RXCOE_CTL 0x34 103 #define AX_RXCOE_IP (1 << 0) 104 #define AX_RXCOE_TCP (1 << 1) 105 #define AX_RXCOE_UDP (1 << 2) 106 #define AX_RXCOE_TCPV6 (1 << 5) 107 #define AX_RXCOE_UDPV6 (1 << 6) 108 109 #define AX_TXCOE_CTL 0x35 110 #define AX_TXCOE_IP (1 << 0) 111 #define AX_TXCOE_TCP (1 << 1) 112 #define AX_TXCOE_UDP (1 << 2) 113 #define AX_TXCOE_TCPV6 (1 << 5) 114 #define AX_TXCOE_UDPV6 (1 << 6) 115 116 #define AX_LEDCTRL 0x73 117 118 #define GMII_PHY_PHYSR 0x11 119 #define GMII_PHY_PHYSR_SMASK 0xc000 120 #define GMII_PHY_PHYSR_GIGA (1 << 15) 121 #define GMII_PHY_PHYSR_100 (1 << 14) 122 #define GMII_PHY_PHYSR_FULL (1 << 13) 123 #define GMII_PHY_PHYSR_LINK (1 << 10) 124 125 #define GMII_LED_ACT 0x1a 126 #define GMII_LED_ACTIVE_MASK 0xff8f 127 #define GMII_LED0_ACTIVE (1 << 4) 128 #define GMII_LED1_ACTIVE (1 << 5) 129 #define GMII_LED2_ACTIVE (1 << 6) 130 131 #define GMII_LED_LINK 0x1c 132 #define GMII_LED_LINK_MASK 0xf888 133 #define GMII_LED0_LINK_10 (1 << 0) 134 #define GMII_LED0_LINK_100 (1 << 1) 135 #define GMII_LED0_LINK_1000 (1 << 2) 136 #define GMII_LED1_LINK_10 (1 << 4) 137 #define GMII_LED1_LINK_100 (1 << 5) 138 #define GMII_LED1_LINK_1000 (1 << 6) 139 #define GMII_LED2_LINK_10 (1 << 8) 140 #define GMII_LED2_LINK_100 (1 << 9) 141 #define GMII_LED2_LINK_1000 (1 << 10) 142 #define LED0_ACTIVE (1 << 0) 143 #define LED0_LINK_10 (1 << 1) 144 #define LED0_LINK_100 (1 << 2) 145 #define LED0_LINK_1000 (1 << 3) 146 #define LED0_FD (1 << 4) 147 #define LED0_USB3_MASK 0x001f 148 #define LED1_ACTIVE (1 << 5) 149 #define LED1_LINK_10 (1 << 6) 150 #define LED1_LINK_100 (1 << 7) 151 #define LED1_LINK_1000 (1 << 8) 152 #define LED1_FD (1 << 9) 153 #define LED1_USB3_MASK 0x03e0 154 #define LED2_ACTIVE (1 << 10) 155 #define LED2_LINK_1000 (1 << 13) 156 #define LED2_LINK_100 (1 << 12) 157 #define LED2_LINK_10 (1 << 11) 158 #define LED2_FD (1 << 14) 159 #define LED_VALID (1 << 15) 160 #define LED2_USB3_MASK 0x7c00 161 162 #define GMII_PHYPAGE 0x1e 163 #define GMII_PHY_PAGE_SELECT 0x1f 164 #define GMII_PHY_PGSEL_EXT 0x0007 165 #define GMII_PHY_PGSEL_PAGE0 0x0000 166 167 /* local defines */ 168 #define ASIX_BASE_NAME "axg" 169 #define USB_CTRL_SET_TIMEOUT 5000 170 #define USB_CTRL_GET_TIMEOUT 5000 171 #define USB_BULK_SEND_TIMEOUT 5000 172 #define USB_BULK_RECV_TIMEOUT 5000 173 174 #define AX_RX_URB_SIZE 1024 * 0x12 175 #define BLK_FRAME_SIZE 0x200 176 #define PHY_CONNECT_TIMEOUT 5000 177 178 #define TIMEOUT_RESOLUTION 50 /* ms */ 179 180 #define FLAG_NONE 0 181 #define FLAG_TYPE_AX88179 (1U << 0) 182 #define FLAG_TYPE_AX88178a (1U << 1) 183 #define FLAG_TYPE_DLINK_DUB1312 (1U << 2) 184 #define FLAG_TYPE_SITECOM (1U << 3) 185 #define FLAG_TYPE_SAMSUNG (1U << 4) 186 #define FLAG_TYPE_LENOVO (1U << 5) 187 188 /* local vars */ 189 static const struct { 190 unsigned char ctrl, timer_l, timer_h, size, ifg; 191 } AX88179_BULKIN_SIZE[] = { 192 {7, 0x4f, 0, 0x02, 0xff}, 193 {7, 0x20, 3, 0x03, 0xff}, 194 {7, 0xae, 7, 0x04, 0xff}, 195 {7, 0xcc, 0x4c, 0x04, 8}, 196 }; 197 198 static int curr_eth_dev; /* index for name of next device detected */ 199 200 /* driver private */ 201 struct asix_private { 202 int flags; 203 int rx_urb_size; 204 int maxpacketsize; 205 }; 206 207 /* 208 * Asix infrastructure commands 209 */ 210 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 211 u16 size, void *data) 212 { 213 int len; 214 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 215 216 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 217 cmd, value, index, size); 218 219 memcpy(buf, data, size); 220 221 len = usb_control_msg( 222 dev->pusb_dev, 223 usb_sndctrlpipe(dev->pusb_dev, 0), 224 cmd, 225 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 226 value, 227 index, 228 buf, 229 size, 230 USB_CTRL_SET_TIMEOUT); 231 232 return len == size ? 0 : ECOMM; 233 } 234 235 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 236 u16 size, void *data) 237 { 238 int len; 239 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 240 241 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 242 cmd, value, index, size); 243 244 len = usb_control_msg( 245 dev->pusb_dev, 246 usb_rcvctrlpipe(dev->pusb_dev, 0), 247 cmd, 248 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 249 value, 250 index, 251 buf, 252 size, 253 USB_CTRL_GET_TIMEOUT); 254 255 memcpy(data, buf, size); 256 257 return len == size ? 0 : ECOMM; 258 } 259 260 static int asix_read_mac(struct eth_device *eth) 261 { 262 struct ueth_data *dev = (struct ueth_data *)eth->priv; 263 u8 buf[ETH_ALEN]; 264 265 asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); 266 debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", 267 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); 268 269 memcpy(eth->enetaddr, buf, ETH_ALEN); 270 271 return 0; 272 } 273 274 static int asix_basic_reset(struct ueth_data *dev) 275 { 276 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 277 u8 buf[5]; 278 u16 *tmp16; 279 u8 *tmp; 280 281 tmp16 = (u16 *)buf; 282 tmp = (u8 *)buf; 283 284 /* Power up ethernet PHY */ 285 *tmp16 = 0; 286 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 287 288 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 289 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 290 mdelay(200); 291 292 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 293 asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 294 mdelay(200); 295 296 /* RX bulk configuration */ 297 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 298 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 299 300 dev_priv->rx_urb_size = 128 * 20; 301 302 /* Water Level configuration */ 303 *tmp = 0x34; 304 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 305 306 *tmp = 0x52; 307 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp); 308 309 /* Enable checksum offload */ 310 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 311 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 312 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 313 314 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 315 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 316 asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 317 318 /* Configure RX control register => start operation */ 319 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 320 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 321 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 322 323 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 324 AX_MONITOR_MODE_RWMP; 325 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 326 327 /* Configure default medium type => giga */ 328 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 329 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 330 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; 331 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); 332 333 u16 adv = 0; 334 adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | 335 ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; 336 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); 337 338 adv = ADVERTISE_1000FULL; 339 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); 340 341 return 0; 342 } 343 344 static int asix_wait_link(struct ueth_data *dev) 345 { 346 int timeout = 0; 347 int link_detected; 348 u8 buf[2]; 349 u16 *tmp16; 350 351 tmp16 = (u16 *)buf; 352 353 do { 354 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 355 MII_BMSR, 2, buf); 356 link_detected = *tmp16 & BMSR_LSTATUS; 357 if (!link_detected) { 358 if (timeout == 0) 359 printf("Waiting for Ethernet connection... "); 360 mdelay(TIMEOUT_RESOLUTION); 361 timeout += TIMEOUT_RESOLUTION; 362 } 363 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 364 365 if (link_detected) { 366 if (timeout > 0) 367 printf("done.\n"); 368 return 0; 369 } else { 370 printf("unable to connect.\n"); 371 return -ENETUNREACH; 372 } 373 } 374 375 /* 376 * Asix callbacks 377 */ 378 static int asix_init(struct eth_device *eth, bd_t *bd) 379 { 380 struct ueth_data *dev = (struct ueth_data *)eth->priv; 381 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 382 u8 buf[2], tmp[5], link_sts; 383 u16 *tmp16, mode; 384 385 386 tmp16 = (u16 *)buf; 387 388 debug("** %s()\n", __func__); 389 390 /* Configure RX control register => start operation */ 391 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 392 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 393 if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0) 394 goto out_err; 395 396 if (asix_wait_link(dev) != 0) { 397 /*reset device and try again*/ 398 printf("Reset Ethernet Device\n"); 399 asix_basic_reset(dev); 400 if (asix_wait_link(dev) != 0) 401 goto out_err; 402 } 403 404 /* Configure link */ 405 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 406 AX_MEDIUM_RXFLOW_CTRLEN; 407 408 asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 409 1, 1, &link_sts); 410 411 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 412 GMII_PHY_PHYSR, 2, tmp16); 413 414 if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) { 415 return 0; 416 } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 417 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ | 418 AX_MEDIUM_JUMBO_EN; 419 420 if (link_sts & AX_USB_SS) 421 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 422 else if (link_sts & AX_USB_HS) 423 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 424 else 425 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 426 } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 427 mode |= AX_MEDIUM_PS; 428 429 if (link_sts & (AX_USB_SS | AX_USB_HS)) 430 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 431 else 432 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 433 } else { 434 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 435 } 436 437 /* RX bulk configuration */ 438 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 439 440 dev_priv->rx_urb_size = (1024 * (tmp[3] + 2)); 441 if (*tmp16 & GMII_PHY_PHYSR_FULL) 442 mode |= AX_MEDIUM_FULL_DUPLEX; 443 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 444 2, 2, &mode); 445 446 return 0; 447 out_err: 448 return -1; 449 } 450 451 static int asix_send(struct eth_device *eth, void *packet, int length) 452 { 453 struct ueth_data *dev = (struct ueth_data *)eth->priv; 454 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 455 456 int err; 457 u32 packet_len, tx_hdr2; 458 int actual_len, framesize; 459 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 460 PKTSIZE + (2 * sizeof(packet_len))); 461 462 debug("** %s(), len %d\n", __func__, length); 463 464 packet_len = length; 465 cpu_to_le32s(&packet_len); 466 467 memcpy(msg, &packet_len, sizeof(packet_len)); 468 framesize = dev_priv->maxpacketsize; 469 tx_hdr2 = 0; 470 if (((length + 8) % framesize) == 0) 471 tx_hdr2 |= 0x80008000; /* Enable padding */ 472 473 cpu_to_le32s(&tx_hdr2); 474 475 memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2)); 476 477 memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2), 478 (void *)packet, length); 479 480 err = usb_bulk_msg(dev->pusb_dev, 481 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 482 (void *)msg, 483 length + sizeof(packet_len) + sizeof(tx_hdr2), 484 &actual_len, 485 USB_BULK_SEND_TIMEOUT); 486 debug("Tx: len = %u, actual = %u, err = %d\n", 487 length + sizeof(packet_len), actual_len, err); 488 489 return err; 490 } 491 492 static int asix_recv(struct eth_device *eth) 493 { 494 struct ueth_data *dev = (struct ueth_data *)eth->priv; 495 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 496 497 u16 frame_pos; 498 int err; 499 int actual_len; 500 501 int pkt_cnt; 502 u32 rx_hdr; 503 u16 hdr_off; 504 u32 *pkt_hdr; 505 ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size); 506 507 actual_len = -1; 508 509 debug("** %s()\n", __func__); 510 511 err = usb_bulk_msg(dev->pusb_dev, 512 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 513 (void *)recv_buf, 514 dev_priv->rx_urb_size, 515 &actual_len, 516 USB_BULK_RECV_TIMEOUT); 517 debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size, 518 actual_len, err); 519 520 if (err != 0) { 521 debug("Rx: failed to receive\n"); 522 return -ECOMM; 523 } 524 if (actual_len > dev_priv->rx_urb_size) { 525 debug("Rx: received too many bytes %d\n", actual_len); 526 return -EMSGSIZE; 527 } 528 529 530 rx_hdr = *(u32 *)(recv_buf + actual_len - 4); 531 le32_to_cpus(&pkt_hdr); 532 533 pkt_cnt = (u16)rx_hdr; 534 hdr_off = (u16)(rx_hdr >> 16); 535 pkt_hdr = (u32 *)(recv_buf + hdr_off); 536 537 538 frame_pos = 0; 539 540 while (pkt_cnt--) { 541 u16 pkt_len; 542 543 le32_to_cpus(pkt_hdr); 544 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 545 546 frame_pos += 2; 547 548 NetReceive(recv_buf + frame_pos, pkt_len); 549 550 pkt_hdr++; 551 frame_pos += ((pkt_len + 7) & 0xFFF8)-2; 552 553 if (pkt_cnt == 0) 554 return 0; 555 } 556 return err; 557 } 558 559 static void asix_halt(struct eth_device *eth) 560 { 561 debug("** %s()\n", __func__); 562 } 563 564 /* 565 * Asix probing functions 566 */ 567 void ax88179_eth_before_probe(void) 568 { 569 curr_eth_dev = 0; 570 } 571 572 struct asix_dongle { 573 unsigned short vendor; 574 unsigned short product; 575 int flags; 576 }; 577 578 static const struct asix_dongle asix_dongles[] = { 579 { 0x0b95, 0x1790, FLAG_TYPE_AX88179 }, 580 { 0x0b95, 0x178a, FLAG_TYPE_AX88178a }, 581 { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 }, 582 { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, 583 { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, 584 { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, 585 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ 586 }; 587 588 /* Probe to see if a new device is actually an asix device */ 589 int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, 590 struct ueth_data *ss) 591 { 592 struct usb_interface *iface; 593 struct usb_interface_descriptor *iface_desc; 594 struct asix_private *dev_priv; 595 int ep_in_found = 0, ep_out_found = 0; 596 int i; 597 598 /* let's examine the device now */ 599 iface = &dev->config.if_desc[ifnum]; 600 iface_desc = &dev->config.if_desc[ifnum].desc; 601 602 for (i = 0; asix_dongles[i].vendor != 0; i++) { 603 if (dev->descriptor.idVendor == asix_dongles[i].vendor && 604 dev->descriptor.idProduct == asix_dongles[i].product) 605 /* Found a supported dongle */ 606 break; 607 } 608 609 if (asix_dongles[i].vendor == 0) 610 return 0; 611 612 memset(ss, 0, sizeof(struct ueth_data)); 613 614 /* At this point, we know we've got a live one */ 615 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 616 dev->descriptor.idVendor, dev->descriptor.idProduct); 617 618 /* Initialize the ueth_data structure with some useful info */ 619 ss->ifnum = ifnum; 620 ss->pusb_dev = dev; 621 ss->subclass = iface_desc->bInterfaceSubClass; 622 ss->protocol = iface_desc->bInterfaceProtocol; 623 624 /* alloc driver private */ 625 ss->dev_priv = calloc(1, sizeof(struct asix_private)); 626 if (!ss->dev_priv) 627 return 0; 628 dev_priv = ss->dev_priv; 629 dev_priv->flags = asix_dongles[i].flags; 630 631 /* 632 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 633 * int. We will ignore any others. 634 */ 635 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 636 /* is it an interrupt endpoint? */ 637 if ((iface->ep_desc[i].bmAttributes & 638 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 639 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 640 USB_ENDPOINT_NUMBER_MASK; 641 ss->irqinterval = iface->ep_desc[i].bInterval; 642 continue; 643 } 644 645 /* is it an BULK endpoint? */ 646 if (!((iface->ep_desc[i].bmAttributes & 647 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) 648 continue; 649 650 u8 ep_addr = iface->ep_desc[i].bEndpointAddress; 651 if ((ep_addr & USB_DIR_IN) && !ep_in_found) { 652 ss->ep_in = ep_addr & 653 USB_ENDPOINT_NUMBER_MASK; 654 ep_in_found = 1; 655 } 656 if (!(ep_addr & USB_DIR_IN) && !ep_out_found) { 657 ss->ep_out = ep_addr & 658 USB_ENDPOINT_NUMBER_MASK; 659 dev_priv->maxpacketsize = 660 dev->epmaxpacketout[AX_ENDPOINT_OUT]; 661 ep_out_found = 1; 662 } 663 } 664 debug("Endpoints In %d Out %d Int %d\n", 665 ss->ep_in, ss->ep_out, ss->ep_int); 666 667 /* Do some basic sanity checks, and bail if we find a problem */ 668 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 669 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 670 debug("Problems with device\n"); 671 return 0; 672 } 673 dev->privptr = (void *)ss; 674 return 1; 675 } 676 677 int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 678 struct eth_device *eth) 679 { 680 if (!eth) { 681 debug("%s: missing parameter.\n", __func__); 682 return 0; 683 } 684 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); 685 eth->init = asix_init; 686 eth->send = asix_send; 687 eth->recv = asix_recv; 688 eth->halt = asix_halt; 689 eth->priv = ss; 690 691 if (asix_basic_reset(ss)) 692 return 0; 693 694 /* Get the MAC address */ 695 if (asix_read_mac(eth)) 696 return 0; 697 debug("MAC %pM\n", eth->enetaddr); 698 699 return 1; 700 } 701