xref: /openbmc/u-boot/drivers/usb/eth/asix88179.c (revision 11933975)
1e9954b86SRene Griessl /*
2e9954b86SRene Griessl  * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
3e9954b86SRene Griessl  * based on the U-Boot Asix driver as well as information
4e9954b86SRene Griessl  * from the Linux AX88179_178a driver
5e9954b86SRene Griessl  *
6e9954b86SRene Griessl  * SPDX-License-Identifier:	GPL-2.0+
7e9954b86SRene Griessl  */
8e9954b86SRene Griessl 
9e9954b86SRene Griessl #include <common.h>
10e9954b86SRene Griessl #include <usb.h>
11e9954b86SRene Griessl #include <net.h>
12e9954b86SRene Griessl #include <linux/mii.h>
13e9954b86SRene Griessl #include "usb_ether.h"
14e9954b86SRene Griessl #include <malloc.h>
15e9954b86SRene Griessl #include <errno.h>
16e9954b86SRene Griessl 
17e9954b86SRene Griessl /* ASIX AX88179 based USB 3.0 Ethernet Devices */
18e9954b86SRene Griessl #define AX88179_PHY_ID				0x03
19e9954b86SRene Griessl #define AX_EEPROM_LEN				0x100
20e9954b86SRene Griessl #define AX88179_EEPROM_MAGIC			0x17900b95
21e9954b86SRene Griessl #define AX_MCAST_FLTSIZE			8
22e9954b86SRene Griessl #define AX_MAX_MCAST				64
23e9954b86SRene Griessl #define AX_INT_PPLS_LINK			(1 << 16)
24e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_MASK			0x1c
25e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_UDP			4
26e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_TCP			16
27e9954b86SRene Griessl #define AX_RXHDR_L3CSUM_ERR			2
28e9954b86SRene Griessl #define AX_RXHDR_L4CSUM_ERR			1
29e9954b86SRene Griessl #define AX_RXHDR_CRC_ERR			(1 << 29)
30e9954b86SRene Griessl #define AX_RXHDR_DROP_ERR			(1 << 31)
31e9954b86SRene Griessl #define AX_ENDPOINT_INT				0x01
32e9954b86SRene Griessl #define AX_ENDPOINT_IN				0x02
33e9954b86SRene Griessl #define AX_ENDPOINT_OUT				0x03
34e9954b86SRene Griessl #define AX_ACCESS_MAC				0x01
35e9954b86SRene Griessl #define AX_ACCESS_PHY				0x02
36e9954b86SRene Griessl #define AX_ACCESS_EEPROM			0x04
37e9954b86SRene Griessl #define AX_ACCESS_EFUS				0x05
38e9954b86SRene Griessl #define AX_PAUSE_WATERLVL_HIGH			0x54
39e9954b86SRene Griessl #define AX_PAUSE_WATERLVL_LOW			0x55
40e9954b86SRene Griessl 
41e9954b86SRene Griessl #define PHYSICAL_LINK_STATUS			0x02
42e9954b86SRene Griessl 	#define	AX_USB_SS		(1 << 2)
43e9954b86SRene Griessl 	#define	AX_USB_HS		(1 << 1)
44e9954b86SRene Griessl 
45e9954b86SRene Griessl #define GENERAL_STATUS				0x03
46e9954b86SRene Griessl 	#define	AX_SECLD		(1 << 2)
47e9954b86SRene Griessl 
48e9954b86SRene Griessl #define AX_SROM_ADDR				0x07
49e9954b86SRene Griessl #define AX_SROM_CMD				0x0a
50e9954b86SRene Griessl 	#define EEP_RD			(1 << 2)
51e9954b86SRene Griessl 	#define EEP_BUSY		(1 << 4)
52e9954b86SRene Griessl 
53e9954b86SRene Griessl #define AX_SROM_DATA_LOW			0x08
54e9954b86SRene Griessl #define AX_SROM_DATA_HIGH			0x09
55e9954b86SRene Griessl 
56e9954b86SRene Griessl #define AX_RX_CTL				0x0b
57e9954b86SRene Griessl 	#define AX_RX_CTL_DROPCRCERR	(1 << 8)
58e9954b86SRene Griessl 	#define AX_RX_CTL_IPE		(1 << 9)
59e9954b86SRene Griessl 	#define AX_RX_CTL_START		(1 << 7)
60e9954b86SRene Griessl 	#define AX_RX_CTL_AP		(1 << 5)
61e9954b86SRene Griessl 	#define AX_RX_CTL_AM		(1 << 4)
62e9954b86SRene Griessl 	#define AX_RX_CTL_AB		(1 << 3)
63e9954b86SRene Griessl 	#define AX_RX_CTL_AMALL		(1 << 1)
64e9954b86SRene Griessl 	#define AX_RX_CTL_PRO		(1 << 0)
65e9954b86SRene Griessl 	#define AX_RX_CTL_STOP		0
66e9954b86SRene Griessl 
67e9954b86SRene Griessl #define AX_NODE_ID				0x10
68e9954b86SRene Griessl #define AX_MULFLTARY				0x16
69e9954b86SRene Griessl 
70e9954b86SRene Griessl #define AX_MEDIUM_STATUS_MODE			0x22
71e9954b86SRene Griessl 	#define AX_MEDIUM_GIGAMODE	(1 << 0)
72e9954b86SRene Griessl 	#define AX_MEDIUM_FULL_DUPLEX	(1 << 1)
73e9954b86SRene Griessl 	#define AX_MEDIUM_EN_125MHZ	(1 << 3)
74e9954b86SRene Griessl 	#define AX_MEDIUM_RXFLOW_CTRLEN	(1 << 4)
75e9954b86SRene Griessl 	#define AX_MEDIUM_TXFLOW_CTRLEN	(1 << 5)
76e9954b86SRene Griessl 	#define AX_MEDIUM_RECEIVE_EN	(1 << 8)
77e9954b86SRene Griessl 	#define AX_MEDIUM_PS		(1 << 9)
78e9954b86SRene Griessl 	#define AX_MEDIUM_JUMBO_EN	0x8040
79e9954b86SRene Griessl 
80e9954b86SRene Griessl #define AX_MONITOR_MOD				0x24
81e9954b86SRene Griessl 	#define AX_MONITOR_MODE_RWLC	(1 << 1)
82e9954b86SRene Griessl 	#define AX_MONITOR_MODE_RWMP	(1 << 2)
83e9954b86SRene Griessl 	#define AX_MONITOR_MODE_PMEPOL	(1 << 5)
84e9954b86SRene Griessl 	#define AX_MONITOR_MODE_PMETYPE	(1 << 6)
85e9954b86SRene Griessl 
86e9954b86SRene Griessl #define AX_GPIO_CTRL				0x25
87e9954b86SRene Griessl 	#define AX_GPIO_CTRL_GPIO3EN	(1 << 7)
88e9954b86SRene Griessl 	#define AX_GPIO_CTRL_GPIO2EN	(1 << 6)
89e9954b86SRene Griessl 	#define AX_GPIO_CTRL_GPIO1EN	(1 << 5)
90e9954b86SRene Griessl 
91e9954b86SRene Griessl #define AX_PHYPWR_RSTCTL			0x26
92e9954b86SRene Griessl 	#define AX_PHYPWR_RSTCTL_BZ	(1 << 4)
93e9954b86SRene Griessl 	#define AX_PHYPWR_RSTCTL_IPRL	(1 << 5)
94e9954b86SRene Griessl 	#define AX_PHYPWR_RSTCTL_AT	(1 << 12)
95e9954b86SRene Griessl 
96e9954b86SRene Griessl #define AX_RX_BULKIN_QCTRL			0x2e
97e9954b86SRene Griessl #define AX_CLK_SELECT				0x33
98e9954b86SRene Griessl 	#define AX_CLK_SELECT_BCS	(1 << 0)
99e9954b86SRene Griessl 	#define AX_CLK_SELECT_ACS	(1 << 1)
100e9954b86SRene Griessl 	#define AX_CLK_SELECT_ULR	(1 << 3)
101e9954b86SRene Griessl 
102e9954b86SRene Griessl #define AX_RXCOE_CTL				0x34
103e9954b86SRene Griessl 	#define AX_RXCOE_IP		(1 << 0)
104e9954b86SRene Griessl 	#define AX_RXCOE_TCP		(1 << 1)
105e9954b86SRene Griessl 	#define AX_RXCOE_UDP		(1 << 2)
106e9954b86SRene Griessl 	#define AX_RXCOE_TCPV6		(1 << 5)
107e9954b86SRene Griessl 	#define AX_RXCOE_UDPV6		(1 << 6)
108e9954b86SRene Griessl 
109e9954b86SRene Griessl #define AX_TXCOE_CTL				0x35
110e9954b86SRene Griessl 	#define AX_TXCOE_IP		(1 << 0)
111e9954b86SRene Griessl 	#define AX_TXCOE_TCP		(1 << 1)
112e9954b86SRene Griessl 	#define AX_TXCOE_UDP		(1 << 2)
113e9954b86SRene Griessl 	#define AX_TXCOE_TCPV6		(1 << 5)
114e9954b86SRene Griessl 	#define AX_TXCOE_UDPV6		(1 << 6)
115e9954b86SRene Griessl 
116e9954b86SRene Griessl #define AX_LEDCTRL				0x73
117e9954b86SRene Griessl 
118e9954b86SRene Griessl #define GMII_PHY_PHYSR				0x11
119e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_SMASK	0xc000
120e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_GIGA	(1 << 15)
121e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_100	(1 << 14)
122e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_FULL	(1 << 13)
123e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_LINK	(1 << 10)
124e9954b86SRene Griessl 
125e9954b86SRene Griessl #define GMII_LED_ACT				0x1a
126e9954b86SRene Griessl 	#define	GMII_LED_ACTIVE_MASK	0xff8f
127e9954b86SRene Griessl 	#define	GMII_LED0_ACTIVE	(1 << 4)
128e9954b86SRene Griessl 	#define	GMII_LED1_ACTIVE	(1 << 5)
129e9954b86SRene Griessl 	#define	GMII_LED2_ACTIVE	(1 << 6)
130e9954b86SRene Griessl 
131e9954b86SRene Griessl #define GMII_LED_LINK				0x1c
132e9954b86SRene Griessl 	#define	GMII_LED_LINK_MASK	0xf888
133e9954b86SRene Griessl 	#define	GMII_LED0_LINK_10	(1 << 0)
134e9954b86SRene Griessl 	#define	GMII_LED0_LINK_100	(1 << 1)
135e9954b86SRene Griessl 	#define	GMII_LED0_LINK_1000	(1 << 2)
136e9954b86SRene Griessl 	#define	GMII_LED1_LINK_10	(1 << 4)
137e9954b86SRene Griessl 	#define	GMII_LED1_LINK_100	(1 << 5)
138e9954b86SRene Griessl 	#define	GMII_LED1_LINK_1000	(1 << 6)
139e9954b86SRene Griessl 	#define	GMII_LED2_LINK_10	(1 << 8)
140e9954b86SRene Griessl 	#define	GMII_LED2_LINK_100	(1 << 9)
141e9954b86SRene Griessl 	#define	GMII_LED2_LINK_1000	(1 << 10)
142e9954b86SRene Griessl 	#define	LED0_ACTIVE		(1 << 0)
143e9954b86SRene Griessl 	#define	LED0_LINK_10		(1 << 1)
144e9954b86SRene Griessl 	#define	LED0_LINK_100		(1 << 2)
145e9954b86SRene Griessl 	#define	LED0_LINK_1000		(1 << 3)
146e9954b86SRene Griessl 	#define	LED0_FD			(1 << 4)
147e9954b86SRene Griessl 	#define	LED0_USB3_MASK		0x001f
148e9954b86SRene Griessl 	#define	LED1_ACTIVE		(1 << 5)
149e9954b86SRene Griessl 	#define	LED1_LINK_10		(1 << 6)
150e9954b86SRene Griessl 	#define	LED1_LINK_100		(1 << 7)
151e9954b86SRene Griessl 	#define	LED1_LINK_1000		(1 << 8)
152e9954b86SRene Griessl 	#define	LED1_FD			(1 << 9)
153e9954b86SRene Griessl 	#define	LED1_USB3_MASK		0x03e0
154e9954b86SRene Griessl 	#define	LED2_ACTIVE		(1 << 10)
155e9954b86SRene Griessl 	#define	LED2_LINK_1000		(1 << 13)
156e9954b86SRene Griessl 	#define	LED2_LINK_100		(1 << 12)
157e9954b86SRene Griessl 	#define	LED2_LINK_10		(1 << 11)
158e9954b86SRene Griessl 	#define	LED2_FD			(1 << 14)
159e9954b86SRene Griessl 	#define	LED_VALID		(1 << 15)
160e9954b86SRene Griessl 	#define	LED2_USB3_MASK		0x7c00
161e9954b86SRene Griessl 
162e9954b86SRene Griessl #define GMII_PHYPAGE				0x1e
163e9954b86SRene Griessl #define GMII_PHY_PAGE_SELECT			0x1f
164e9954b86SRene Griessl 	#define GMII_PHY_PGSEL_EXT	0x0007
165e9954b86SRene Griessl 	#define GMII_PHY_PGSEL_PAGE0	0x0000
166e9954b86SRene Griessl 
167e9954b86SRene Griessl /* local defines */
168e9954b86SRene Griessl #define ASIX_BASE_NAME "axg"
169e9954b86SRene Griessl #define USB_CTRL_SET_TIMEOUT 5000
170e9954b86SRene Griessl #define USB_CTRL_GET_TIMEOUT 5000
171e9954b86SRene Griessl #define USB_BULK_SEND_TIMEOUT 5000
172e9954b86SRene Griessl #define USB_BULK_RECV_TIMEOUT 5000
173e9954b86SRene Griessl 
174e9954b86SRene Griessl #define AX_RX_URB_SIZE 1024 * 0x12
175e9954b86SRene Griessl #define BLK_FRAME_SIZE 0x200
176e9954b86SRene Griessl #define PHY_CONNECT_TIMEOUT 5000
177e9954b86SRene Griessl 
178e9954b86SRene Griessl #define TIMEOUT_RESOLUTION 50	/* ms */
179e9954b86SRene Griessl 
180e9954b86SRene Griessl #define FLAG_NONE			0
181e9954b86SRene Griessl #define FLAG_TYPE_AX88179	(1U << 0)
182e9954b86SRene Griessl #define FLAG_TYPE_AX88178a	(1U << 1)
183e9954b86SRene Griessl #define FLAG_TYPE_DLINK_DUB1312	(1U << 2)
184e9954b86SRene Griessl #define FLAG_TYPE_SITECOM	(1U << 3)
185e9954b86SRene Griessl #define FLAG_TYPE_SAMSUNG	(1U << 4)
186e9954b86SRene Griessl #define FLAG_TYPE_LENOVO	(1U << 5)
187e9954b86SRene Griessl 
188e9954b86SRene Griessl /* local vars */
189e9954b86SRene Griessl static const struct {
190e9954b86SRene Griessl 	unsigned char ctrl, timer_l, timer_h, size, ifg;
191e9954b86SRene Griessl } AX88179_BULKIN_SIZE[] =	{
192e9954b86SRene Griessl 	{7, 0x4f, 0,	0x02, 0xff},
193e9954b86SRene Griessl 	{7, 0x20, 3,	0x03, 0xff},
194e9954b86SRene Griessl 	{7, 0xae, 7,	0x04, 0xff},
195e9954b86SRene Griessl 	{7, 0xcc, 0x4c, 0x04, 8},
196e9954b86SRene Griessl };
197e9954b86SRene Griessl 
198e9954b86SRene Griessl static int curr_eth_dev; /* index for name of next device detected */
199e9954b86SRene Griessl 
200e9954b86SRene Griessl /* driver private */
201e9954b86SRene Griessl struct asix_private {
202e9954b86SRene Griessl 	int flags;
203e9954b86SRene Griessl 	int rx_urb_size;
204e9954b86SRene Griessl 	int maxpacketsize;
205e9954b86SRene Griessl };
206e9954b86SRene Griessl 
207e9954b86SRene Griessl /*
208e9954b86SRene Griessl  * Asix infrastructure commands
209e9954b86SRene Griessl  */
210e9954b86SRene Griessl static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
211e9954b86SRene Griessl 			     u16 size, void *data)
212e9954b86SRene Griessl {
213e9954b86SRene Griessl 	int len;
214e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
215e9954b86SRene Griessl 
216e9954b86SRene Griessl 	debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
217e9954b86SRene Griessl 	      cmd, value, index, size);
218e9954b86SRene Griessl 
219e9954b86SRene Griessl 	memcpy(buf, data, size);
220e9954b86SRene Griessl 
221e9954b86SRene Griessl 	len = usb_control_msg(
222e9954b86SRene Griessl 		dev->pusb_dev,
223e9954b86SRene Griessl 		usb_sndctrlpipe(dev->pusb_dev, 0),
224e9954b86SRene Griessl 		cmd,
225e9954b86SRene Griessl 		USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
226e9954b86SRene Griessl 		value,
227e9954b86SRene Griessl 		index,
228e9954b86SRene Griessl 		buf,
229e9954b86SRene Griessl 		size,
230e9954b86SRene Griessl 		USB_CTRL_SET_TIMEOUT);
231e9954b86SRene Griessl 
232e9954b86SRene Griessl 	return len == size ? 0 : ECOMM;
233e9954b86SRene Griessl }
234e9954b86SRene Griessl 
235e9954b86SRene Griessl static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
236e9954b86SRene Griessl 			    u16 size, void *data)
237e9954b86SRene Griessl {
238e9954b86SRene Griessl 	int len;
239e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
240e9954b86SRene Griessl 
241e9954b86SRene Griessl 	debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
242e9954b86SRene Griessl 	      cmd, value, index, size);
243e9954b86SRene Griessl 
244e9954b86SRene Griessl 	len = usb_control_msg(
245e9954b86SRene Griessl 		dev->pusb_dev,
246e9954b86SRene Griessl 		usb_rcvctrlpipe(dev->pusb_dev, 0),
247e9954b86SRene Griessl 		cmd,
248e9954b86SRene Griessl 		USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
249e9954b86SRene Griessl 		value,
250e9954b86SRene Griessl 		index,
251e9954b86SRene Griessl 		buf,
252e9954b86SRene Griessl 		size,
253e9954b86SRene Griessl 		USB_CTRL_GET_TIMEOUT);
254e9954b86SRene Griessl 
255e9954b86SRene Griessl 	memcpy(data, buf, size);
256e9954b86SRene Griessl 
257e9954b86SRene Griessl 	return len == size ? 0 : ECOMM;
258e9954b86SRene Griessl }
259e9954b86SRene Griessl 
260e9954b86SRene Griessl static int asix_read_mac(struct eth_device *eth)
261e9954b86SRene Griessl {
262e9954b86SRene Griessl 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
263e9954b86SRene Griessl 	u8 buf[ETH_ALEN];
264e9954b86SRene Griessl 
265e9954b86SRene Griessl 	asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf);
266e9954b86SRene Griessl 	debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n",
267e9954b86SRene Griessl 	      buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
268e9954b86SRene Griessl 
269e9954b86SRene Griessl 	memcpy(eth->enetaddr, buf, ETH_ALEN);
270e9954b86SRene Griessl 
271e9954b86SRene Griessl 	return 0;
272e9954b86SRene Griessl }
273e9954b86SRene Griessl 
274*11933975SRene Griessl static int asix_write_mac(struct eth_device *eth)
275*11933975SRene Griessl {
276*11933975SRene Griessl 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
277*11933975SRene Griessl 	int ret;
278*11933975SRene Griessl 
279*11933975SRene Griessl 	ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
280*11933975SRene Griessl 				 ETH_ALEN, eth->enetaddr);
281*11933975SRene Griessl 	if (ret < 0)
282*11933975SRene Griessl 		debug("Failed to set MAC address: %02x\n", ret);
283*11933975SRene Griessl 
284*11933975SRene Griessl 	return ret;
285*11933975SRene Griessl }
286*11933975SRene Griessl 
287e9954b86SRene Griessl static int asix_basic_reset(struct ueth_data *dev)
288e9954b86SRene Griessl {
289e9954b86SRene Griessl 	struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
290e9954b86SRene Griessl 	u8 buf[5];
291e9954b86SRene Griessl 	u16 *tmp16;
292e9954b86SRene Griessl 	u8 *tmp;
293e9954b86SRene Griessl 
294e9954b86SRene Griessl 	tmp16 = (u16 *)buf;
295e9954b86SRene Griessl 	tmp = (u8 *)buf;
296e9954b86SRene Griessl 
297e9954b86SRene Griessl 	/* Power up ethernet PHY */
298e9954b86SRene Griessl 	*tmp16 = 0;
299e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
300e9954b86SRene Griessl 
301e9954b86SRene Griessl 	*tmp16 = AX_PHYPWR_RSTCTL_IPRL;
302e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
303e9954b86SRene Griessl 	mdelay(200);
304e9954b86SRene Griessl 
305e9954b86SRene Griessl 	*tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
306e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
307e9954b86SRene Griessl 	mdelay(200);
308e9954b86SRene Griessl 
309e9954b86SRene Griessl 	/* RX bulk configuration */
310e9954b86SRene Griessl 	memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
311e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
312e9954b86SRene Griessl 
313e9954b86SRene Griessl 	dev_priv->rx_urb_size = 128 * 20;
314e9954b86SRene Griessl 
315e9954b86SRene Griessl 	/* Water Level configuration */
316e9954b86SRene Griessl 	*tmp = 0x34;
317e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
318e9954b86SRene Griessl 
319e9954b86SRene Griessl 	*tmp = 0x52;
320e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
321e9954b86SRene Griessl 
322e9954b86SRene Griessl 	/* Enable checksum offload */
323e9954b86SRene Griessl 	*tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
324e9954b86SRene Griessl 	       AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
325e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
326e9954b86SRene Griessl 
327e9954b86SRene Griessl 	*tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
328e9954b86SRene Griessl 	       AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
329e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
330e9954b86SRene Griessl 
331e9954b86SRene Griessl 	/* Configure RX control register => start operation */
332e9954b86SRene Griessl 	*tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
333e9954b86SRene Griessl 		 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
334e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
335e9954b86SRene Griessl 
336e9954b86SRene Griessl 	*tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
337e9954b86SRene Griessl 	       AX_MONITOR_MODE_RWMP;
338e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
339e9954b86SRene Griessl 
340e9954b86SRene Griessl 	/* Configure default medium type => giga */
341e9954b86SRene Griessl 	*tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
342e9954b86SRene Griessl 		 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
343e9954b86SRene Griessl 		 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
344e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
345e9954b86SRene Griessl 
346e9954b86SRene Griessl 	u16 adv = 0;
347e9954b86SRene Griessl 	adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
348e9954b86SRene Griessl 	      ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
349e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
350e9954b86SRene Griessl 
351e9954b86SRene Griessl 	adv = ADVERTISE_1000FULL;
352e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
353e9954b86SRene Griessl 
354e9954b86SRene Griessl 	return 0;
355e9954b86SRene Griessl }
356e9954b86SRene Griessl 
357e9954b86SRene Griessl static int asix_wait_link(struct ueth_data *dev)
358e9954b86SRene Griessl {
359e9954b86SRene Griessl 	int timeout = 0;
360e9954b86SRene Griessl 	int link_detected;
361e9954b86SRene Griessl 	u8 buf[2];
362e9954b86SRene Griessl 	u16 *tmp16;
363e9954b86SRene Griessl 
364e9954b86SRene Griessl 	tmp16 = (u16 *)buf;
365e9954b86SRene Griessl 
366e9954b86SRene Griessl 	do {
367e9954b86SRene Griessl 		asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
368e9954b86SRene Griessl 			      MII_BMSR, 2, buf);
369e9954b86SRene Griessl 		link_detected = *tmp16 & BMSR_LSTATUS;
370e9954b86SRene Griessl 		if (!link_detected) {
371e9954b86SRene Griessl 			if (timeout == 0)
372e9954b86SRene Griessl 				printf("Waiting for Ethernet connection... ");
373e9954b86SRene Griessl 			mdelay(TIMEOUT_RESOLUTION);
374e9954b86SRene Griessl 			timeout += TIMEOUT_RESOLUTION;
375e9954b86SRene Griessl 		}
376e9954b86SRene Griessl 	} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
377e9954b86SRene Griessl 
378e9954b86SRene Griessl 	if (link_detected) {
379e9954b86SRene Griessl 		if (timeout > 0)
380e9954b86SRene Griessl 			printf("done.\n");
381e9954b86SRene Griessl 		return 0;
382e9954b86SRene Griessl 	} else {
383e9954b86SRene Griessl 		printf("unable to connect.\n");
384e9954b86SRene Griessl 		return -ENETUNREACH;
385e9954b86SRene Griessl 	}
386e9954b86SRene Griessl }
387e9954b86SRene Griessl 
388e9954b86SRene Griessl /*
389e9954b86SRene Griessl  * Asix callbacks
390e9954b86SRene Griessl  */
391e9954b86SRene Griessl static int asix_init(struct eth_device *eth, bd_t *bd)
392e9954b86SRene Griessl {
393e9954b86SRene Griessl 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
394e9954b86SRene Griessl 	struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
395e9954b86SRene Griessl 	u8 buf[2], tmp[5], link_sts;
396e9954b86SRene Griessl 	u16 *tmp16, mode;
397e9954b86SRene Griessl 
398e9954b86SRene Griessl 
399e9954b86SRene Griessl 	tmp16 = (u16 *)buf;
400e9954b86SRene Griessl 
401e9954b86SRene Griessl 	debug("** %s()\n", __func__);
402e9954b86SRene Griessl 
403e9954b86SRene Griessl 	/* Configure RX control register => start operation */
404e9954b86SRene Griessl 	*tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
405e9954b86SRene Griessl 		 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
406e9954b86SRene Griessl 	if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
407e9954b86SRene Griessl 		goto out_err;
408e9954b86SRene Griessl 
409e9954b86SRene Griessl 	if (asix_wait_link(dev) != 0) {
410e9954b86SRene Griessl 		/*reset device and try again*/
411e9954b86SRene Griessl 		printf("Reset Ethernet Device\n");
412e9954b86SRene Griessl 		asix_basic_reset(dev);
413e9954b86SRene Griessl 		if (asix_wait_link(dev) != 0)
414e9954b86SRene Griessl 			goto out_err;
415e9954b86SRene Griessl 	}
416e9954b86SRene Griessl 
417e9954b86SRene Griessl 	/* Configure link */
418e9954b86SRene Griessl 	mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
419e9954b86SRene Griessl 	       AX_MEDIUM_RXFLOW_CTRLEN;
420e9954b86SRene Griessl 
421e9954b86SRene Griessl 	asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
422e9954b86SRene Griessl 		      1, 1, &link_sts);
423e9954b86SRene Griessl 
424e9954b86SRene Griessl 	asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
425e9954b86SRene Griessl 		      GMII_PHY_PHYSR, 2, tmp16);
426e9954b86SRene Griessl 
427e9954b86SRene Griessl 	if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
428e9954b86SRene Griessl 		return 0;
429e9954b86SRene Griessl 	} else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
430e9954b86SRene Griessl 		mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
431e9954b86SRene Griessl 			AX_MEDIUM_JUMBO_EN;
432e9954b86SRene Griessl 
433e9954b86SRene Griessl 		if (link_sts & AX_USB_SS)
434e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
435e9954b86SRene Griessl 		else if (link_sts & AX_USB_HS)
436e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
437e9954b86SRene Griessl 		else
438e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
439e9954b86SRene Griessl 	} else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
440e9954b86SRene Griessl 		mode |= AX_MEDIUM_PS;
441e9954b86SRene Griessl 
442e9954b86SRene Griessl 		if (link_sts & (AX_USB_SS | AX_USB_HS))
443e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
444e9954b86SRene Griessl 		else
445e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
446e9954b86SRene Griessl 	} else {
447e9954b86SRene Griessl 		memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
448e9954b86SRene Griessl 	}
449e9954b86SRene Griessl 
450e9954b86SRene Griessl 	/* RX bulk configuration */
451e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
452e9954b86SRene Griessl 
453e9954b86SRene Griessl 	dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
454e9954b86SRene Griessl 	if (*tmp16 & GMII_PHY_PHYSR_FULL)
455e9954b86SRene Griessl 		mode |= AX_MEDIUM_FULL_DUPLEX;
456e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
457e9954b86SRene Griessl 		       2, 2, &mode);
458e9954b86SRene Griessl 
459e9954b86SRene Griessl 	return 0;
460e9954b86SRene Griessl out_err:
461e9954b86SRene Griessl 	return -1;
462e9954b86SRene Griessl }
463e9954b86SRene Griessl 
464e9954b86SRene Griessl static int asix_send(struct eth_device *eth, void *packet, int length)
465e9954b86SRene Griessl {
466e9954b86SRene Griessl 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
467e9954b86SRene Griessl 	struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
468e9954b86SRene Griessl 
469e9954b86SRene Griessl 	int err;
470e9954b86SRene Griessl 	u32 packet_len, tx_hdr2;
471e9954b86SRene Griessl 	int actual_len, framesize;
472e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
473e9954b86SRene Griessl 				 PKTSIZE + (2 * sizeof(packet_len)));
474e9954b86SRene Griessl 
475e9954b86SRene Griessl 	debug("** %s(), len %d\n", __func__, length);
476e9954b86SRene Griessl 
477e9954b86SRene Griessl 	packet_len = length;
478e9954b86SRene Griessl 	cpu_to_le32s(&packet_len);
479e9954b86SRene Griessl 
480e9954b86SRene Griessl 	memcpy(msg, &packet_len, sizeof(packet_len));
481e9954b86SRene Griessl 	framesize = dev_priv->maxpacketsize;
482e9954b86SRene Griessl 	tx_hdr2 = 0;
483e9954b86SRene Griessl 	if (((length + 8) % framesize) == 0)
484e9954b86SRene Griessl 		tx_hdr2 |= 0x80008000;	/* Enable padding */
485e9954b86SRene Griessl 
486e9954b86SRene Griessl 	cpu_to_le32s(&tx_hdr2);
487e9954b86SRene Griessl 
488e9954b86SRene Griessl 	memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
489e9954b86SRene Griessl 
490e9954b86SRene Griessl 	memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
491e9954b86SRene Griessl 	       (void *)packet, length);
492e9954b86SRene Griessl 
493e9954b86SRene Griessl 	err = usb_bulk_msg(dev->pusb_dev,
494e9954b86SRene Griessl 				usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
495e9954b86SRene Griessl 				(void *)msg,
496e9954b86SRene Griessl 				length + sizeof(packet_len) + sizeof(tx_hdr2),
497e9954b86SRene Griessl 				&actual_len,
498e9954b86SRene Griessl 				USB_BULK_SEND_TIMEOUT);
499e9954b86SRene Griessl 	debug("Tx: len = %u, actual = %u, err = %d\n",
500e9954b86SRene Griessl 	      length + sizeof(packet_len), actual_len, err);
501e9954b86SRene Griessl 
502e9954b86SRene Griessl 	return err;
503e9954b86SRene Griessl }
504e9954b86SRene Griessl 
505e9954b86SRene Griessl static int asix_recv(struct eth_device *eth)
506e9954b86SRene Griessl {
507e9954b86SRene Griessl 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
508e9954b86SRene Griessl 	struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
509e9954b86SRene Griessl 
510e9954b86SRene Griessl 	u16 frame_pos;
511e9954b86SRene Griessl 	int err;
512e9954b86SRene Griessl 	int actual_len;
513e9954b86SRene Griessl 
514e9954b86SRene Griessl 	int pkt_cnt;
515e9954b86SRene Griessl 	u32 rx_hdr;
516e9954b86SRene Griessl 	u16 hdr_off;
517e9954b86SRene Griessl 	u32 *pkt_hdr;
518e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
519e9954b86SRene Griessl 
520e9954b86SRene Griessl 	actual_len = -1;
521e9954b86SRene Griessl 
522e9954b86SRene Griessl 	debug("** %s()\n", __func__);
523e9954b86SRene Griessl 
524e9954b86SRene Griessl 	err = usb_bulk_msg(dev->pusb_dev,
525e9954b86SRene Griessl 				usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
526e9954b86SRene Griessl 				(void *)recv_buf,
527e9954b86SRene Griessl 				dev_priv->rx_urb_size,
528e9954b86SRene Griessl 				&actual_len,
529e9954b86SRene Griessl 				USB_BULK_RECV_TIMEOUT);
530e9954b86SRene Griessl 	debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
531e9954b86SRene Griessl 	      actual_len, err);
532e9954b86SRene Griessl 
533e9954b86SRene Griessl 	if (err != 0) {
534e9954b86SRene Griessl 		debug("Rx: failed to receive\n");
535e9954b86SRene Griessl 		return -ECOMM;
536e9954b86SRene Griessl 	}
537e9954b86SRene Griessl 	if (actual_len > dev_priv->rx_urb_size) {
538e9954b86SRene Griessl 		debug("Rx: received too many bytes %d\n", actual_len);
539e9954b86SRene Griessl 		return -EMSGSIZE;
540e9954b86SRene Griessl 	}
541e9954b86SRene Griessl 
542e9954b86SRene Griessl 
543e9954b86SRene Griessl 	rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
544e9954b86SRene Griessl 	le32_to_cpus(&pkt_hdr);
545e9954b86SRene Griessl 
546e9954b86SRene Griessl 	pkt_cnt = (u16)rx_hdr;
547e9954b86SRene Griessl 	hdr_off = (u16)(rx_hdr >> 16);
548e9954b86SRene Griessl 	pkt_hdr = (u32 *)(recv_buf + hdr_off);
549e9954b86SRene Griessl 
550e9954b86SRene Griessl 
551e9954b86SRene Griessl 	frame_pos = 0;
552e9954b86SRene Griessl 
553e9954b86SRene Griessl 	while (pkt_cnt--) {
554e9954b86SRene Griessl 		u16 pkt_len;
555e9954b86SRene Griessl 
556e9954b86SRene Griessl 		le32_to_cpus(pkt_hdr);
557e9954b86SRene Griessl 		pkt_len = (*pkt_hdr >> 16) & 0x1fff;
558e9954b86SRene Griessl 
559e9954b86SRene Griessl 		frame_pos += 2;
560e9954b86SRene Griessl 
561e9954b86SRene Griessl 		NetReceive(recv_buf + frame_pos, pkt_len);
562e9954b86SRene Griessl 
563e9954b86SRene Griessl 		pkt_hdr++;
564e9954b86SRene Griessl 		frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
565e9954b86SRene Griessl 
566e9954b86SRene Griessl 		if (pkt_cnt == 0)
567e9954b86SRene Griessl 			return 0;
568e9954b86SRene Griessl 	}
569e9954b86SRene Griessl 	return err;
570e9954b86SRene Griessl }
571e9954b86SRene Griessl 
572e9954b86SRene Griessl static void asix_halt(struct eth_device *eth)
573e9954b86SRene Griessl {
574e9954b86SRene Griessl 	debug("** %s()\n", __func__);
575e9954b86SRene Griessl }
576e9954b86SRene Griessl 
577e9954b86SRene Griessl /*
578e9954b86SRene Griessl  * Asix probing functions
579e9954b86SRene Griessl  */
580e9954b86SRene Griessl void ax88179_eth_before_probe(void)
581e9954b86SRene Griessl {
582e9954b86SRene Griessl 	curr_eth_dev = 0;
583e9954b86SRene Griessl }
584e9954b86SRene Griessl 
585e9954b86SRene Griessl struct asix_dongle {
586e9954b86SRene Griessl 	unsigned short vendor;
587e9954b86SRene Griessl 	unsigned short product;
588e9954b86SRene Griessl 	int flags;
589e9954b86SRene Griessl };
590e9954b86SRene Griessl 
591e9954b86SRene Griessl static const struct asix_dongle asix_dongles[] = {
592e9954b86SRene Griessl 	{ 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
593e9954b86SRene Griessl 	{ 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
594e9954b86SRene Griessl 	{ 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
595e9954b86SRene Griessl 	{ 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
596e9954b86SRene Griessl 	{ 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
597e9954b86SRene Griessl 	{ 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
598e9954b86SRene Griessl 	{ 0x0000, 0x0000, FLAG_NONE }	/* END - Do not remove */
599e9954b86SRene Griessl };
600e9954b86SRene Griessl 
601e9954b86SRene Griessl /* Probe to see if a new device is actually an asix device */
602e9954b86SRene Griessl int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
603e9954b86SRene Griessl 		      struct ueth_data *ss)
604e9954b86SRene Griessl {
605e9954b86SRene Griessl 	struct usb_interface *iface;
606e9954b86SRene Griessl 	struct usb_interface_descriptor *iface_desc;
607e9954b86SRene Griessl 	struct asix_private *dev_priv;
608e9954b86SRene Griessl 	int ep_in_found = 0, ep_out_found = 0;
609e9954b86SRene Griessl 	int i;
610e9954b86SRene Griessl 
611e9954b86SRene Griessl 	/* let's examine the device now */
612e9954b86SRene Griessl 	iface = &dev->config.if_desc[ifnum];
613e9954b86SRene Griessl 	iface_desc = &dev->config.if_desc[ifnum].desc;
614e9954b86SRene Griessl 
615e9954b86SRene Griessl 	for (i = 0; asix_dongles[i].vendor != 0; i++) {
616e9954b86SRene Griessl 		if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
617e9954b86SRene Griessl 		    dev->descriptor.idProduct == asix_dongles[i].product)
618e9954b86SRene Griessl 			/* Found a supported dongle */
619e9954b86SRene Griessl 			break;
620e9954b86SRene Griessl 	}
621e9954b86SRene Griessl 
622e9954b86SRene Griessl 	if (asix_dongles[i].vendor == 0)
623e9954b86SRene Griessl 		return 0;
624e9954b86SRene Griessl 
625e9954b86SRene Griessl 	memset(ss, 0, sizeof(struct ueth_data));
626e9954b86SRene Griessl 
627e9954b86SRene Griessl 	/* At this point, we know we've got a live one */
628e9954b86SRene Griessl 	debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
629e9954b86SRene Griessl 	      dev->descriptor.idVendor, dev->descriptor.idProduct);
630e9954b86SRene Griessl 
631e9954b86SRene Griessl 	/* Initialize the ueth_data structure with some useful info */
632e9954b86SRene Griessl 	ss->ifnum = ifnum;
633e9954b86SRene Griessl 	ss->pusb_dev = dev;
634e9954b86SRene Griessl 	ss->subclass = iface_desc->bInterfaceSubClass;
635e9954b86SRene Griessl 	ss->protocol = iface_desc->bInterfaceProtocol;
636e9954b86SRene Griessl 
637e9954b86SRene Griessl 	/* alloc driver private */
638e9954b86SRene Griessl 	ss->dev_priv = calloc(1, sizeof(struct asix_private));
639e9954b86SRene Griessl 	if (!ss->dev_priv)
640e9954b86SRene Griessl 		return 0;
641e9954b86SRene Griessl 	dev_priv = ss->dev_priv;
642e9954b86SRene Griessl 	dev_priv->flags = asix_dongles[i].flags;
643e9954b86SRene Griessl 
644e9954b86SRene Griessl 	/*
645e9954b86SRene Griessl 	 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
646e9954b86SRene Griessl 	 * int. We will ignore any others.
647e9954b86SRene Griessl 	 */
648e9954b86SRene Griessl 	for (i = 0; i < iface_desc->bNumEndpoints; i++) {
649e9954b86SRene Griessl 		/* is it an interrupt endpoint? */
650e9954b86SRene Griessl 		if ((iface->ep_desc[i].bmAttributes &
651e9954b86SRene Griessl 		    USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
652e9954b86SRene Griessl 			ss->ep_int = iface->ep_desc[i].bEndpointAddress &
653e9954b86SRene Griessl 				USB_ENDPOINT_NUMBER_MASK;
654e9954b86SRene Griessl 			ss->irqinterval = iface->ep_desc[i].bInterval;
655e9954b86SRene Griessl 			continue;
656e9954b86SRene Griessl 		}
657e9954b86SRene Griessl 
658e9954b86SRene Griessl 		/* is it an BULK endpoint? */
659e9954b86SRene Griessl 		if (!((iface->ep_desc[i].bmAttributes &
660e9954b86SRene Griessl 		     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
661e9954b86SRene Griessl 			continue;
662e9954b86SRene Griessl 
663e9954b86SRene Griessl 		u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
664e9954b86SRene Griessl 		if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
665e9954b86SRene Griessl 			ss->ep_in = ep_addr &
666e9954b86SRene Griessl 				USB_ENDPOINT_NUMBER_MASK;
667e9954b86SRene Griessl 			ep_in_found = 1;
668e9954b86SRene Griessl 		}
669e9954b86SRene Griessl 		if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
670e9954b86SRene Griessl 			ss->ep_out = ep_addr &
671e9954b86SRene Griessl 				USB_ENDPOINT_NUMBER_MASK;
672e9954b86SRene Griessl 			dev_priv->maxpacketsize =
673e9954b86SRene Griessl 				dev->epmaxpacketout[AX_ENDPOINT_OUT];
674e9954b86SRene Griessl 			ep_out_found = 1;
675e9954b86SRene Griessl 		}
676e9954b86SRene Griessl 	}
677e9954b86SRene Griessl 	debug("Endpoints In %d Out %d Int %d\n",
678e9954b86SRene Griessl 	      ss->ep_in, ss->ep_out, ss->ep_int);
679e9954b86SRene Griessl 
680e9954b86SRene Griessl 	/* Do some basic sanity checks, and bail if we find a problem */
681e9954b86SRene Griessl 	if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
682e9954b86SRene Griessl 	    !ss->ep_in || !ss->ep_out || !ss->ep_int) {
683e9954b86SRene Griessl 		debug("Problems with device\n");
684e9954b86SRene Griessl 		return 0;
685e9954b86SRene Griessl 	}
686e9954b86SRene Griessl 	dev->privptr = (void *)ss;
687e9954b86SRene Griessl 	return 1;
688e9954b86SRene Griessl }
689e9954b86SRene Griessl 
690e9954b86SRene Griessl int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
691e9954b86SRene Griessl 				struct eth_device *eth)
692e9954b86SRene Griessl {
693e9954b86SRene Griessl 	if (!eth) {
694e9954b86SRene Griessl 		debug("%s: missing parameter.\n", __func__);
695e9954b86SRene Griessl 		return 0;
696e9954b86SRene Griessl 	}
697e9954b86SRene Griessl 	sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
698e9954b86SRene Griessl 	eth->init = asix_init;
699e9954b86SRene Griessl 	eth->send = asix_send;
700e9954b86SRene Griessl 	eth->recv = asix_recv;
701e9954b86SRene Griessl 	eth->halt = asix_halt;
702*11933975SRene Griessl 	eth->write_hwaddr = asix_write_mac;
703e9954b86SRene Griessl 	eth->priv = ss;
704e9954b86SRene Griessl 
705e9954b86SRene Griessl 	if (asix_basic_reset(ss))
706e9954b86SRene Griessl 		return 0;
707e9954b86SRene Griessl 
708e9954b86SRene Griessl 	/* Get the MAC address */
709e9954b86SRene Griessl 	if (asix_read_mac(eth))
710e9954b86SRene Griessl 		return 0;
711e9954b86SRene Griessl 	debug("MAC %pM\n", eth->enetaddr);
712e9954b86SRene Griessl 
713e9954b86SRene Griessl 	return 1;
714e9954b86SRene Griessl }
715