1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include <common.h> 23 #include <usb.h> 24 #include <linux/mii.h> 25 #include "usb_ether.h" 26 27 28 /* ASIX AX8817X based USB 2.0 Ethernet Devices */ 29 30 #define AX_CMD_SET_SW_MII 0x06 31 #define AX_CMD_READ_MII_REG 0x07 32 #define AX_CMD_WRITE_MII_REG 0x08 33 #define AX_CMD_SET_HW_MII 0x0a 34 #define AX_CMD_READ_RX_CTL 0x0f 35 #define AX_CMD_WRITE_RX_CTL 0x10 36 #define AX_CMD_WRITE_IPG0 0x12 37 #define AX_CMD_READ_NODE_ID 0x13 38 #define AX_CMD_READ_PHY_ID 0x19 39 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b 40 #define AX_CMD_WRITE_GPIOS 0x1f 41 #define AX_CMD_SW_RESET 0x20 42 #define AX_CMD_SW_PHY_SELECT 0x22 43 44 #define AX_SWRESET_CLEAR 0x00 45 #define AX_SWRESET_PRTE 0x04 46 #define AX_SWRESET_PRL 0x08 47 #define AX_SWRESET_IPRL 0x20 48 #define AX_SWRESET_IPPD 0x40 49 50 #define AX88772_IPG0_DEFAULT 0x15 51 #define AX88772_IPG1_DEFAULT 0x0c 52 #define AX88772_IPG2_DEFAULT 0x12 53 54 /* AX88772 & AX88178 Medium Mode Register */ 55 #define AX_MEDIUM_PF 0x0080 56 #define AX_MEDIUM_JFE 0x0040 57 #define AX_MEDIUM_TFC 0x0020 58 #define AX_MEDIUM_RFC 0x0010 59 #define AX_MEDIUM_ENCK 0x0008 60 #define AX_MEDIUM_AC 0x0004 61 #define AX_MEDIUM_FD 0x0002 62 #define AX_MEDIUM_GM 0x0001 63 #define AX_MEDIUM_SM 0x1000 64 #define AX_MEDIUM_SBP 0x0800 65 #define AX_MEDIUM_PS 0x0200 66 #define AX_MEDIUM_RE 0x0100 67 68 #define AX88178_MEDIUM_DEFAULT \ 69 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ 70 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ 71 AX_MEDIUM_RE) 72 73 #define AX88772_MEDIUM_DEFAULT \ 74 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ 75 AX_MEDIUM_TFC | AX_MEDIUM_PS | \ 76 AX_MEDIUM_AC | AX_MEDIUM_RE) 77 78 /* AX88772 & AX88178 RX_CTL values */ 79 #define AX_RX_CTL_SO 0x0080 80 #define AX_RX_CTL_AB 0x0008 81 82 #define AX_DEFAULT_RX_CTL \ 83 (AX_RX_CTL_SO | AX_RX_CTL_AB) 84 85 /* GPIO 2 toggles */ 86 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ 87 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ 88 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ 89 90 /* local defines */ 91 #define ASIX_BASE_NAME "asx" 92 #define USB_CTRL_SET_TIMEOUT 5000 93 #define USB_CTRL_GET_TIMEOUT 5000 94 #define USB_BULK_SEND_TIMEOUT 5000 95 #define USB_BULK_RECV_TIMEOUT 5000 96 97 #define AX_RX_URB_SIZE 2048 98 #define PHY_CONNECT_TIMEOUT 5000 99 100 /* local vars */ 101 static int curr_eth_dev; /* index for name of next device detected */ 102 103 /* 104 * Asix infrastructure commands 105 */ 106 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 107 u16 size, void *data) 108 { 109 int len; 110 111 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x " 112 "size=%d\n", cmd, value, index, size); 113 114 len = usb_control_msg( 115 dev->pusb_dev, 116 usb_sndctrlpipe(dev->pusb_dev, 0), 117 cmd, 118 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 119 value, 120 index, 121 data, 122 size, 123 USB_CTRL_SET_TIMEOUT); 124 125 return len == size ? 0 : -1; 126 } 127 128 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 129 u16 size, void *data) 130 { 131 int len; 132 133 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 134 cmd, value, index, size); 135 136 len = usb_control_msg( 137 dev->pusb_dev, 138 usb_rcvctrlpipe(dev->pusb_dev, 0), 139 cmd, 140 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 141 value, 142 index, 143 data, 144 size, 145 USB_CTRL_GET_TIMEOUT); 146 return len == size ? 0 : -1; 147 } 148 149 static inline int asix_set_sw_mii(struct ueth_data *dev) 150 { 151 int ret; 152 153 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); 154 if (ret < 0) 155 debug("Failed to enable software MII access\n"); 156 return ret; 157 } 158 159 static inline int asix_set_hw_mii(struct ueth_data *dev) 160 { 161 int ret; 162 163 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); 164 if (ret < 0) 165 debug("Failed to enable hardware MII access\n"); 166 return ret; 167 } 168 169 static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc) 170 { 171 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); 172 173 asix_set_sw_mii(dev); 174 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res); 175 asix_set_hw_mii(dev); 176 177 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", 178 phy_id, loc, le16_to_cpu(*res)); 179 180 return le16_to_cpu(*res); 181 } 182 183 static void 184 asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val) 185 { 186 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); 187 *res = cpu_to_le16(val); 188 189 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", 190 phy_id, loc, val); 191 asix_set_sw_mii(dev); 192 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res); 193 asix_set_hw_mii(dev); 194 } 195 196 /* 197 * Asix "high level" commands 198 */ 199 static int asix_sw_reset(struct ueth_data *dev, u8 flags) 200 { 201 int ret; 202 203 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); 204 if (ret < 0) 205 debug("Failed to send software reset: %02x\n", ret); 206 else 207 udelay(150 * 1000); 208 209 return ret; 210 } 211 212 static inline int asix_get_phy_addr(struct ueth_data *dev) 213 { 214 ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2); 215 216 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); 217 218 debug("asix_get_phy_addr()\n"); 219 220 if (ret < 0) { 221 debug("Error reading PHYID register: %02x\n", ret); 222 goto out; 223 } 224 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]); 225 ret = buf[1]; 226 227 out: 228 return ret; 229 } 230 231 static int asix_write_medium_mode(struct ueth_data *dev, u16 mode) 232 { 233 int ret; 234 235 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode); 236 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 237 0, 0, NULL); 238 if (ret < 0) { 239 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n", 240 mode, ret); 241 } 242 return ret; 243 } 244 245 static u16 asix_read_rx_ctl(struct ueth_data *dev) 246 { 247 ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1); 248 249 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v); 250 251 if (ret < 0) 252 debug("Error reading RX_CTL register: %02x\n", ret); 253 else 254 ret = le16_to_cpu(*v); 255 return ret; 256 } 257 258 static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode) 259 { 260 int ret; 261 262 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode); 263 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); 264 if (ret < 0) { 265 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n", 266 mode, ret); 267 } 268 return ret; 269 } 270 271 static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep) 272 { 273 int ret; 274 275 debug("asix_write_gpio() - value = 0x%04x\n", value); 276 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); 277 if (ret < 0) { 278 debug("Failed to write GPIO value 0x%04x: %02x\n", 279 value, ret); 280 } 281 if (sleep) 282 udelay(sleep * 1000); 283 284 return ret; 285 } 286 287 /* 288 * mii commands 289 */ 290 291 /* 292 * mii_nway_restart - restart NWay (autonegotiation) for this interface 293 * 294 * Returns 0 on success, negative on error. 295 */ 296 static int mii_nway_restart(struct ueth_data *dev) 297 { 298 int bmcr; 299 int r = -1; 300 301 /* if autoneg is off, it's an error */ 302 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR); 303 304 if (bmcr & BMCR_ANENABLE) { 305 bmcr |= BMCR_ANRESTART; 306 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 307 r = 0; 308 } 309 310 return r; 311 } 312 313 /* 314 * Asix callbacks 315 */ 316 static int asix_init(struct eth_device *eth, bd_t *bd) 317 { 318 int embd_phy; 319 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN); 320 u16 rx_ctl; 321 struct ueth_data *dev = (struct ueth_data *)eth->priv; 322 int timeout = 0; 323 #define TIMEOUT_RESOLUTION 50 /* ms */ 324 int link_detected; 325 326 debug("** %s()\n", __func__); 327 328 if (asix_write_gpio(dev, 329 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0) 330 goto out_err; 331 332 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */ 333 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); 334 if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 335 embd_phy, 0, 0, NULL) < 0) { 336 debug("Select PHY #1 failed\n"); 337 goto out_err; 338 } 339 340 if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0) 341 goto out_err; 342 343 if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0) 344 goto out_err; 345 346 if (embd_phy) { 347 if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0) 348 goto out_err; 349 } else { 350 if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0) 351 goto out_err; 352 } 353 354 rx_ctl = asix_read_rx_ctl(dev); 355 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl); 356 if (asix_write_rx_ctl(dev, 0x0000) < 0) 357 goto out_err; 358 359 rx_ctl = asix_read_rx_ctl(dev); 360 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); 361 362 /* Get the MAC address */ 363 if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 364 0, 0, ETH_ALEN, buf) < 0) { 365 debug("Failed to read MAC address.\n"); 366 goto out_err; 367 } 368 memcpy(eth->enetaddr, buf, ETH_ALEN); 369 debug("MAC %02x:%02x:%02x:%02x:%02x:%02x\n", 370 eth->enetaddr[0], eth->enetaddr[1], 371 eth->enetaddr[2], eth->enetaddr[3], 372 eth->enetaddr[4], eth->enetaddr[5]); 373 374 dev->phy_id = asix_get_phy_addr(dev); 375 if (dev->phy_id < 0) 376 debug("Failed to read phy id\n"); 377 378 if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0) 379 goto out_err; 380 381 if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0) 382 goto out_err; 383 384 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 385 asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 386 ADVERTISE_ALL | ADVERTISE_CSMA); 387 mii_nway_restart(dev); 388 389 if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0) 390 goto out_err; 391 392 if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 393 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 394 AX88772_IPG2_DEFAULT, 0, NULL) < 0) { 395 debug("Write IPG,IPG1,IPG2 failed\n"); 396 goto out_err; 397 } 398 399 if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0) 400 goto out_err; 401 402 do { 403 link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) & 404 BMSR_LSTATUS; 405 if (!link_detected) { 406 if (timeout == 0) 407 printf("Waiting for Ethernet connection... "); 408 udelay(TIMEOUT_RESOLUTION * 1000); 409 timeout += TIMEOUT_RESOLUTION; 410 } 411 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 412 if (link_detected) { 413 if (timeout != 0) 414 printf("done.\n"); 415 } else { 416 printf("unable to connect.\n"); 417 goto out_err; 418 } 419 420 return 0; 421 out_err: 422 return -1; 423 } 424 425 static int asix_send(struct eth_device *eth, void *packet, int length) 426 { 427 struct ueth_data *dev = (struct ueth_data *)eth->priv; 428 int err; 429 u32 packet_len; 430 int actual_len; 431 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 432 PKTSIZE + sizeof(packet_len)); 433 434 debug("** %s(), len %d\n", __func__, length); 435 436 packet_len = (((length) ^ 0x0000ffff) << 16) + (length); 437 cpu_to_le32s(&packet_len); 438 439 memcpy(msg, &packet_len, sizeof(packet_len)); 440 memcpy(msg + sizeof(packet_len), (void *)packet, length); 441 if (length & 1) 442 length++; 443 444 err = usb_bulk_msg(dev->pusb_dev, 445 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 446 (void *)msg, 447 length + sizeof(packet_len), 448 &actual_len, 449 USB_BULK_SEND_TIMEOUT); 450 debug("Tx: len = %u, actual = %u, err = %d\n", 451 length + sizeof(packet_len), actual_len, err); 452 453 return err; 454 } 455 456 static int asix_recv(struct eth_device *eth) 457 { 458 struct ueth_data *dev = (struct ueth_data *)eth->priv; 459 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); 460 unsigned char *buf_ptr; 461 int err; 462 int actual_len; 463 u32 packet_len; 464 465 debug("** %s()\n", __func__); 466 467 err = usb_bulk_msg(dev->pusb_dev, 468 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 469 (void *)recv_buf, 470 AX_RX_URB_SIZE, 471 &actual_len, 472 USB_BULK_RECV_TIMEOUT); 473 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 474 actual_len, err); 475 if (err != 0) { 476 debug("Rx: failed to receive\n"); 477 return -1; 478 } 479 if (actual_len > AX_RX_URB_SIZE) { 480 debug("Rx: received too many bytes %d\n", actual_len); 481 return -1; 482 } 483 484 buf_ptr = recv_buf; 485 while (actual_len > 0) { 486 /* 487 * 1st 4 bytes contain the length of the actual data as two 488 * complementary 16-bit words. Extract the length of the data. 489 */ 490 if (actual_len < sizeof(packet_len)) { 491 debug("Rx: incomplete packet length\n"); 492 return -1; 493 } 494 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 495 le32_to_cpus(&packet_len); 496 if (((packet_len >> 16) ^ 0xffff) != (packet_len & 0xffff)) { 497 debug("Rx: malformed packet length: %#x (%#x:%#x)\n", 498 packet_len, (packet_len >> 16) ^ 0xffff, 499 packet_len & 0xffff); 500 return -1; 501 } 502 packet_len = packet_len & 0xffff; 503 if (packet_len > actual_len - sizeof(packet_len)) { 504 debug("Rx: too large packet: %d\n", packet_len); 505 return -1; 506 } 507 508 /* Notify net stack */ 509 NetReceive(buf_ptr + sizeof(packet_len), packet_len); 510 511 /* Adjust for next iteration. Packets are padded to 16-bits */ 512 if (packet_len & 1) 513 packet_len++; 514 actual_len -= sizeof(packet_len) + packet_len; 515 buf_ptr += sizeof(packet_len) + packet_len; 516 } 517 518 return err; 519 } 520 521 static void asix_halt(struct eth_device *eth) 522 { 523 debug("** %s()\n", __func__); 524 } 525 526 /* 527 * Asix probing functions 528 */ 529 void asix_eth_before_probe(void) 530 { 531 curr_eth_dev = 0; 532 } 533 534 struct asix_dongle { 535 unsigned short vendor; 536 unsigned short product; 537 }; 538 539 static struct asix_dongle asix_dongles[] = { 540 { 0x05ac, 0x1402 }, /* Apple USB Ethernet Adapter */ 541 { 0x07d1, 0x3c05 }, /* D-Link DUB-E100 H/W Ver B1 */ 542 { 0x0b95, 0x772a }, /* Cables-to-Go USB Ethernet Adapter */ 543 { 0x0b95, 0x7720 }, /* Trendnet TU2-ET100 V3.0R */ 544 { 0x0b95, 0x1720 }, /* SMC */ 545 { 0x0db0, 0xa877 }, /* MSI - ASIX 88772a */ 546 { 0x13b1, 0x0018 }, /* Linksys 200M v2.1 */ 547 { 0x1557, 0x7720 }, /* 0Q0 cable ethernet */ 548 { 0x2001, 0x3c05 }, /* DLink DUB-E100 H/W Ver B1 Alternate */ 549 { 0x0000, 0x0000 } /* END - Do not remove */ 550 }; 551 552 /* Probe to see if a new device is actually an asix device */ 553 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, 554 struct ueth_data *ss) 555 { 556 struct usb_interface *iface; 557 struct usb_interface_descriptor *iface_desc; 558 int i; 559 560 /* let's examine the device now */ 561 iface = &dev->config.if_desc[ifnum]; 562 iface_desc = &dev->config.if_desc[ifnum].desc; 563 564 for (i = 0; asix_dongles[i].vendor != 0; i++) { 565 if (dev->descriptor.idVendor == asix_dongles[i].vendor && 566 dev->descriptor.idProduct == asix_dongles[i].product) 567 /* Found a supported dongle */ 568 break; 569 } 570 571 if (asix_dongles[i].vendor == 0) 572 return 0; 573 574 memset(ss, 0, sizeof(struct ueth_data)); 575 576 /* At this point, we know we've got a live one */ 577 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 578 dev->descriptor.idVendor, dev->descriptor.idProduct); 579 580 /* Initialize the ueth_data structure with some useful info */ 581 ss->ifnum = ifnum; 582 ss->pusb_dev = dev; 583 ss->subclass = iface_desc->bInterfaceSubClass; 584 ss->protocol = iface_desc->bInterfaceProtocol; 585 586 /* 587 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 588 * int. We will ignore any others. 589 */ 590 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 591 /* is it an BULK endpoint? */ 592 if ((iface->ep_desc[i].bmAttributes & 593 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 594 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 595 ss->ep_in = iface->ep_desc[i].bEndpointAddress & 596 USB_ENDPOINT_NUMBER_MASK; 597 else 598 ss->ep_out = 599 iface->ep_desc[i].bEndpointAddress & 600 USB_ENDPOINT_NUMBER_MASK; 601 } 602 603 /* is it an interrupt endpoint? */ 604 if ((iface->ep_desc[i].bmAttributes & 605 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 606 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 607 USB_ENDPOINT_NUMBER_MASK; 608 ss->irqinterval = iface->ep_desc[i].bInterval; 609 } 610 } 611 debug("Endpoints In %d Out %d Int %d\n", 612 ss->ep_in, ss->ep_out, ss->ep_int); 613 614 /* Do some basic sanity checks, and bail if we find a problem */ 615 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 616 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 617 debug("Problems with device\n"); 618 return 0; 619 } 620 dev->privptr = (void *)ss; 621 return 1; 622 } 623 624 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 625 struct eth_device *eth) 626 { 627 if (!eth) { 628 debug("%s: missing parameter.\n", __func__); 629 return 0; 630 } 631 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); 632 eth->init = asix_init; 633 eth->send = asix_send; 634 eth->recv = asix_recv; 635 eth->halt = asix_halt; 636 eth->priv = ss; 637 638 return 1; 639 } 640