1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3 4 * 5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Author: Kishon Vijay Abraham I <kishon@ti.com> 8 * 9 * Taken from Linux Kernel v3.16 (drivers/phy/phy-ti-pipe3.c and 10 * drivers/phy/phy-omap-usb2.c) and ported to uboot. 11 * 12 * "commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload" for 13 * phy-ti-pipe3.c 14 * 15 * "commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe failure 16 * and remove" for phy-omap-usb2.c 17 */ 18 19 #include <common.h> 20 #include <malloc.h> 21 #include <ti-usb-phy-uboot.h> 22 #include <usb/lin_gadget_compat.h> 23 #include <linux/ioport.h> 24 #include <asm/io.h> 25 #include <asm/arch/sys_proto.h> 26 #include <dm.h> 27 28 #include "linux-compat.h" 29 30 #define PLL_STATUS 0x00000004 31 #define PLL_GO 0x00000008 32 #define PLL_CONFIGURATION1 0x0000000C 33 #define PLL_CONFIGURATION2 0x00000010 34 #define PLL_CONFIGURATION3 0x00000014 35 #define PLL_CONFIGURATION4 0x00000020 36 37 #define PLL_REGM_MASK 0x001FFE00 38 #define PLL_REGM_SHIFT 0x9 39 #define PLL_REGM_F_MASK 0x0003FFFF 40 #define PLL_REGM_F_SHIFT 0x0 41 #define PLL_REGN_MASK 0x000001FE 42 #define PLL_REGN_SHIFT 0x1 43 #define PLL_SELFREQDCO_MASK 0x0000000E 44 #define PLL_SELFREQDCO_SHIFT 0x1 45 #define PLL_SD_MASK 0x0003FC00 46 #define PLL_SD_SHIFT 10 47 #define SET_PLL_GO 0x1 48 #define PLL_LDOPWDN BIT(15) 49 #define PLL_TICOPWDN BIT(16) 50 #define PLL_LOCK 0x2 51 #define PLL_IDLE 0x1 52 53 #define OMAP_CTRL_DEV_PHY_PD BIT(0) 54 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 55 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE 56 57 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 58 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 59 60 #define OMAP_CTRL_USB3_PHY_TX_RX_POWERON 0x3 61 #define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF 0x0 62 63 #define OMAP_CTRL_USB2_PHY_PD BIT(28) 64 65 #define AM437X_CTRL_USB2_PHY_PD BIT(0) 66 #define AM437X_CTRL_USB2_OTG_PD BIT(1) 67 #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19) 68 #define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20) 69 70 static LIST_HEAD(ti_usb_phy_list); 71 typedef unsigned int u32; 72 73 struct usb3_dpll_params { 74 u16 m; 75 u8 n; 76 u8 freq:3; 77 u8 sd; 78 u32 mf; 79 }; 80 81 struct usb3_dpll_map { 82 unsigned long rate; 83 struct usb3_dpll_params params; 84 struct usb3_dpll_map *dpll_map; 85 }; 86 87 struct ti_usb_phy { 88 void __iomem *pll_ctrl_base; 89 void __iomem *usb2_phy_power; 90 void __iomem *usb3_phy_power; 91 struct usb3_dpll_map *dpll_map; 92 struct list_head list; 93 int index; 94 }; 95 96 static struct usb3_dpll_map dpll_map_usb[] = { 97 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ 98 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ 99 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ 100 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ 101 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ 102 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ 103 { }, /* Terminator */ 104 }; 105 106 static inline unsigned int ti_usb3_readl(void __iomem *base, u32 offset) 107 { 108 return readl(base + offset); 109 } 110 111 static inline void ti_usb3_writel(void __iomem *base, u32 offset, u32 value) 112 { 113 writel(value, base + offset); 114 } 115 116 #ifndef CONFIG_AM43XX 117 static struct usb3_dpll_params *ti_usb3_get_dpll_params(struct ti_usb_phy *phy) 118 { 119 unsigned long rate; 120 struct usb3_dpll_map *dpll_map = phy->dpll_map; 121 122 rate = get_sys_clk_freq(); 123 124 for (; dpll_map->rate; dpll_map++) { 125 if (rate == dpll_map->rate) 126 return &dpll_map->params; 127 } 128 129 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); 130 131 return NULL; 132 } 133 134 static int ti_usb3_dpll_wait_lock(struct ti_usb_phy *phy) 135 { 136 u32 val; 137 do { 138 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS); 139 if (val & PLL_LOCK) 140 break; 141 } while (1); 142 143 return 0; 144 } 145 146 static int ti_usb3_dpll_program(struct ti_usb_phy *phy) 147 { 148 u32 val; 149 struct usb3_dpll_params *dpll_params; 150 151 if (!phy->pll_ctrl_base) 152 return -EINVAL; 153 154 dpll_params = ti_usb3_get_dpll_params(phy); 155 if (!dpll_params) 156 return -EINVAL; 157 158 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); 159 val &= ~PLL_REGN_MASK; 160 val |= dpll_params->n << PLL_REGN_SHIFT; 161 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); 162 163 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); 164 val &= ~PLL_SELFREQDCO_MASK; 165 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; 166 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); 167 168 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); 169 val &= ~PLL_REGM_MASK; 170 val |= dpll_params->m << PLL_REGM_SHIFT; 171 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); 172 173 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); 174 val &= ~PLL_REGM_F_MASK; 175 val |= dpll_params->mf << PLL_REGM_F_SHIFT; 176 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); 177 178 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); 179 val &= ~PLL_SD_MASK; 180 val |= dpll_params->sd << PLL_SD_SHIFT; 181 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); 182 183 ti_usb3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); 184 185 return ti_usb3_dpll_wait_lock(phy); 186 } 187 #endif 188 189 void ti_usb2_phy_power(struct ti_usb_phy *phy, int on) 190 { 191 u32 val; 192 193 val = readl(phy->usb2_phy_power); 194 195 if (on) { 196 #if defined(CONFIG_DRA7XX) 197 if (phy->index == 1) 198 val &= ~OMAP_CTRL_USB2_PHY_PD; 199 else 200 val &= ~OMAP_CTRL_DEV_PHY_PD; 201 #elif defined(CONFIG_AM43XX) 202 val &= ~(AM437X_CTRL_USB2_PHY_PD | 203 AM437X_CTRL_USB2_OTG_PD); 204 val |= (AM437X_CTRL_USB2_OTGVDET_EN | 205 AM437X_CTRL_USB2_OTGSESSEND_EN); 206 #endif 207 } else { 208 #if defined(CONFIG_DRA7XX) 209 if (phy->index == 1) 210 val |= OMAP_CTRL_USB2_PHY_PD; 211 else 212 val |= OMAP_CTRL_DEV_PHY_PD; 213 214 #elif defined(CONFIG_AM43XX) 215 val &= ~(AM437X_CTRL_USB2_OTGVDET_EN | 216 AM437X_CTRL_USB2_OTGSESSEND_EN); 217 val |= (AM437X_CTRL_USB2_PHY_PD | 218 AM437X_CTRL_USB2_OTG_PD); 219 #endif 220 } 221 writel(val, phy->usb2_phy_power); 222 } 223 224 #ifndef CONFIG_AM43XX 225 void ti_usb3_phy_power(struct ti_usb_phy *phy, int on) 226 { 227 u32 val; 228 u32 rate; 229 rate = get_sys_clk_freq(); 230 rate = rate/1000000; 231 232 if (!phy->usb3_phy_power) 233 return; 234 235 val = readl(phy->usb3_phy_power); 236 if (on) { 237 val &= ~(OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK | 238 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK); 239 val |= (OMAP_CTRL_USB3_PHY_TX_RX_POWERON) << 240 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT; 241 val |= rate << 242 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT; 243 } else { 244 val &= ~OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK; 245 val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF << 246 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT; 247 } 248 writel(val, phy->usb3_phy_power); 249 } 250 #endif 251 252 /** 253 * ti_usb_phy_uboot_init - usb phy uboot initialization code 254 * @dev: struct ti_usb_phy_device containing initialization data 255 * 256 * Entry point for ti usb phy driver. This driver handles initialization 257 * of both usb2 phy and usb3 phy. Pointer to ti_usb_phy_device should be 258 * passed containing base address and other initialization data. 259 * Returns '0' on success and a negative value on failure. 260 * 261 * Generally called from board_usb_init() implemented in board file. 262 */ 263 int ti_usb_phy_uboot_init(struct ti_usb_phy_device *dev) 264 { 265 struct ti_usb_phy *phy; 266 267 phy = devm_kzalloc(NULL, sizeof(*phy), GFP_KERNEL); 268 if (!phy) { 269 dev_err(NULL, "unable to alloc mem for TI USB3 PHY\n"); 270 return -ENOMEM; 271 } 272 273 phy->dpll_map = dpll_map_usb; 274 phy->index = dev->index; 275 phy->pll_ctrl_base = dev->pll_ctrl_base; 276 phy->usb2_phy_power = dev->usb2_phy_power; 277 phy->usb3_phy_power = dev->usb3_phy_power; 278 279 #ifndef CONFIG_AM43XX 280 ti_usb3_dpll_program(phy); 281 ti_usb3_phy_power(phy, 1); 282 #endif 283 ti_usb2_phy_power(phy, 1); 284 mdelay(150); 285 list_add_tail(&phy->list, &ti_usb_phy_list); 286 287 return 0; 288 } 289 290 /** 291 * ti_usb_phy_uboot_exit - usb phy uboot cleanup code 292 * @index: index of this controller 293 * 294 * Performs cleanup of memory allocated in ti_usb_phy_uboot_init. 295 * index of _this_ controller should be passed and should match with 296 * the index passed in ti_usb_phy_device during init. 297 * 298 * Generally called from board file. 299 */ 300 void ti_usb_phy_uboot_exit(int index) 301 { 302 struct ti_usb_phy *phy = NULL; 303 304 list_for_each_entry(phy, &ti_usb_phy_list, list) { 305 if (phy->index != index) 306 continue; 307 308 ti_usb2_phy_power(phy, 0); 309 #ifndef CONFIG_AM43XX 310 ti_usb3_phy_power(phy, 0); 311 #endif 312 list_del(&phy->list); 313 kfree(phy); 314 break; 315 } 316 } 317