1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported 10 * to uboot. 11 * 12 * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete() 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <dwc3-omap-uboot.h> 21 #include <linux/usb/dwc3-omap.h> 22 #include <linux/ioport.h> 23 24 #include <linux/usb/otg.h> 25 #include <linux/compat.h> 26 27 #include "linux-compat.h" 28 29 /* 30 * All these registers belong to OMAP's Wrapper around the 31 * DesignWare USB3 Core. 32 */ 33 34 #define USBOTGSS_REVISION 0x0000 35 #define USBOTGSS_SYSCONFIG 0x0010 36 #define USBOTGSS_IRQ_EOI 0x0020 37 #define USBOTGSS_EOI_OFFSET 0x0008 38 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 39 #define USBOTGSS_IRQSTATUS_0 0x0028 40 #define USBOTGSS_IRQENABLE_SET_0 0x002c 41 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 42 #define USBOTGSS_IRQ0_OFFSET 0x0004 43 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 44 #define USBOTGSS_IRQSTATUS_1 0x0034 45 #define USBOTGSS_IRQENABLE_SET_1 0x0038 46 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 47 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 48 #define USBOTGSS_IRQSTATUS_2 0x0044 49 #define USBOTGSS_IRQENABLE_SET_2 0x0048 50 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 51 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 52 #define USBOTGSS_IRQSTATUS_3 0x0054 53 #define USBOTGSS_IRQENABLE_SET_3 0x0058 54 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 55 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 56 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 57 #define USBOTGSS_IRQSTATUS_MISC 0x0038 58 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 59 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 60 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 61 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 62 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 63 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 64 #define USBOTGSS_TXFIFO_DEPTH 0x0508 65 #define USBOTGSS_RXFIFO_DEPTH 0x050c 66 #define USBOTGSS_MMRAM_OFFSET 0x0100 67 #define USBOTGSS_FLADJ 0x0104 68 #define USBOTGSS_DEBUG_CFG 0x0108 69 #define USBOTGSS_DEBUG_DATA 0x010c 70 #define USBOTGSS_DEV_EBC_EN 0x0110 71 #define USBOTGSS_DEBUG_OFFSET 0x0600 72 73 /* SYSCONFIG REGISTER */ 74 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 75 76 /* IRQ_EOI REGISTER */ 77 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 78 79 /* IRQS0 BITS */ 80 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 81 82 /* IRQMISC BITS */ 83 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 84 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 85 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 86 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 87 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 88 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 89 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 90 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 91 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 92 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 93 94 /* UTMI_OTG_CTRL REGISTER */ 95 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 96 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 97 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 98 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 99 100 /* UTMI_OTG_STATUS REGISTER */ 101 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 102 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 103 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 104 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 105 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 106 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 107 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 108 109 struct dwc3_omap { 110 struct device *dev; 111 112 void __iomem *base; 113 114 u32 utmi_otg_status; 115 u32 utmi_otg_offset; 116 u32 irqmisc_offset; 117 u32 irq_eoi_offset; 118 u32 debug_offset; 119 u32 irq0_offset; 120 121 u32 dma_status:1; 122 }; 123 124 struct dwc3_omap *omap; 125 126 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 127 { 128 return readl(base + offset); 129 } 130 131 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 132 { 133 writel(value, base + offset); 134 } 135 136 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap) 137 { 138 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS + 139 omap->utmi_otg_offset); 140 } 141 142 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value) 143 { 144 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS + 145 omap->utmi_otg_offset, value); 146 147 } 148 149 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 150 { 151 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 152 omap->irq0_offset); 153 } 154 155 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 156 { 157 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 158 omap->irq0_offset, value); 159 160 } 161 162 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 163 { 164 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 165 omap->irqmisc_offset); 166 } 167 168 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 169 { 170 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 171 omap->irqmisc_offset, value); 172 173 } 174 175 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 176 { 177 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 178 omap->irqmisc_offset, value); 179 180 } 181 182 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 183 { 184 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 185 omap->irq0_offset, value); 186 } 187 188 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 189 enum omap_dwc3_vbus_id_status status) 190 { 191 u32 val; 192 193 switch (status) { 194 case OMAP_DWC3_ID_GROUND: 195 dev_dbg(omap->dev, "ID GND\n"); 196 197 val = dwc3_omap_read_utmi_status(omap); 198 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG 199 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 200 | USBOTGSS_UTMI_OTG_STATUS_SESSEND); 201 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID 202 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 203 dwc3_omap_write_utmi_status(omap, val); 204 break; 205 206 case OMAP_DWC3_VBUS_VALID: 207 dev_dbg(omap->dev, "VBUS Connect\n"); 208 209 val = dwc3_omap_read_utmi_status(omap); 210 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; 211 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG 212 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 213 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID 214 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 215 dwc3_omap_write_utmi_status(omap, val); 216 break; 217 218 case OMAP_DWC3_ID_FLOAT: 219 case OMAP_DWC3_VBUS_OFF: 220 dev_dbg(omap->dev, "VBUS Disconnect\n"); 221 222 val = dwc3_omap_read_utmi_status(omap); 223 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID 224 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 225 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); 226 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND 227 | USBOTGSS_UTMI_OTG_STATUS_IDDIG; 228 dwc3_omap_write_utmi_status(omap, val); 229 break; 230 231 default: 232 dev_dbg(omap->dev, "invalid state\n"); 233 } 234 } 235 236 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 237 { 238 struct dwc3_omap *omap = _omap; 239 u32 reg; 240 241 reg = dwc3_omap_read_irqmisc_status(omap); 242 243 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) { 244 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 245 omap->dma_status = false; 246 } 247 248 if (reg & USBOTGSS_IRQMISC_OEVT) 249 dev_dbg(omap->dev, "OTG Event\n"); 250 251 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE) 252 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 253 254 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE) 255 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 256 257 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE) 258 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 259 260 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE) 261 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 262 263 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL) 264 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 265 266 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL) 267 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 268 269 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL) 270 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 271 272 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL) 273 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 274 275 dwc3_omap_write_irqmisc_status(omap, reg); 276 277 reg = dwc3_omap_read_irq0_status(omap); 278 279 dwc3_omap_write_irq0_status(omap, reg); 280 281 return IRQ_HANDLED; 282 } 283 284 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 285 { 286 u32 reg; 287 288 /* enable all IRQs */ 289 reg = USBOTGSS_IRQO_COREIRQ_ST; 290 dwc3_omap_write_irq0_set(omap, reg); 291 292 reg = (USBOTGSS_IRQMISC_OEVT | 293 USBOTGSS_IRQMISC_DRVVBUS_RISE | 294 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 295 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 296 USBOTGSS_IRQMISC_IDPULLUP_RISE | 297 USBOTGSS_IRQMISC_DRVVBUS_FALL | 298 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 299 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 300 USBOTGSS_IRQMISC_IDPULLUP_FALL); 301 302 dwc3_omap_write_irqmisc_set(omap, reg); 303 } 304 305 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 306 { 307 /* disable all IRQs */ 308 dwc3_omap_write_irqmisc_set(omap, 0x00); 309 dwc3_omap_write_irq0_set(omap, 0x00); 310 } 311 312 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 313 { 314 /* 315 * Differentiate between OMAP5 and AM437x. 316 * 317 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 318 * though there are changes in wrapper register offsets. 319 * 320 * Using dt compatible to differentiate AM437x. 321 */ 322 #ifdef CONFIG_AM43XX 323 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 324 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 325 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 326 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 327 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 328 #endif 329 } 330 331 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode) 332 { 333 u32 reg; 334 335 reg = dwc3_omap_read_utmi_status(omap); 336 337 switch (utmi_mode) { 338 case DWC3_OMAP_UTMI_MODE_SW: 339 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 340 break; 341 case DWC3_OMAP_UTMI_MODE_HW: 342 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 343 break; 344 default: 345 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 346 } 347 348 dwc3_omap_write_utmi_status(omap, reg); 349 } 350 351 /** 352 * dwc3_omap_uboot_init - dwc3 omap uboot initialization code 353 * @dev: struct dwc3_omap_device containing initialization data 354 * 355 * Entry point for dwc3 omap driver (equivalent to dwc3_omap_probe in linux 356 * kernel driver). Pointer to dwc3_omap_device should be passed containing 357 * base address and other initialization data. Returns '0' on success and 358 * a negative value on failure. 359 * 360 * Generally called from board_usb_init() implemented in board file. 361 */ 362 int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev) 363 { 364 u32 reg; 365 struct device *dev; 366 367 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 368 if (!omap) 369 return -ENOMEM; 370 371 omap->base = omap_dev->base; 372 373 dwc3_omap_map_offset(omap); 374 dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode); 375 376 /* check the DMA Status */ 377 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 378 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 379 380 dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status); 381 382 dwc3_omap_enable_irqs(omap); 383 384 return 0; 385 } 386 387 /** 388 * dwc3_omap_uboot_exit - dwc3 omap uboot cleanup code 389 * @index: index of this controller 390 * 391 * Performs cleanup of memory allocated in dwc3_omap_uboot_init 392 * (equivalent to dwc3_omap_remove in linux). 393 * 394 * Generally called from board file. 395 */ 396 void dwc3_omap_uboot_exit(void) 397 { 398 dwc3_omap_disable_irqs(omap); 399 kfree(omap); 400 401 return 0; 402 } 403 404 MODULE_ALIAS("platform:omap-dwc3"); 405 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 406 MODULE_LICENSE("GPL v2"); 407 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 408