1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported 10 * to uboot. 11 * 12 * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete() 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <linux/usb/dwc3-omap.h> 21 #include <linux/ioport.h> 22 23 #include <linux/usb/otg.h> 24 #include <linux/compat.h> 25 26 #include "linux-compat.h" 27 28 /* 29 * All these registers belong to OMAP's Wrapper around the 30 * DesignWare USB3 Core. 31 */ 32 33 #define USBOTGSS_REVISION 0x0000 34 #define USBOTGSS_SYSCONFIG 0x0010 35 #define USBOTGSS_IRQ_EOI 0x0020 36 #define USBOTGSS_EOI_OFFSET 0x0008 37 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 38 #define USBOTGSS_IRQSTATUS_0 0x0028 39 #define USBOTGSS_IRQENABLE_SET_0 0x002c 40 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 41 #define USBOTGSS_IRQ0_OFFSET 0x0004 42 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 43 #define USBOTGSS_IRQSTATUS_1 0x0034 44 #define USBOTGSS_IRQENABLE_SET_1 0x0038 45 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 46 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 47 #define USBOTGSS_IRQSTATUS_2 0x0044 48 #define USBOTGSS_IRQENABLE_SET_2 0x0048 49 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 50 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 51 #define USBOTGSS_IRQSTATUS_3 0x0054 52 #define USBOTGSS_IRQENABLE_SET_3 0x0058 53 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 54 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 55 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 56 #define USBOTGSS_IRQSTATUS_MISC 0x0038 57 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 58 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 59 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 60 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 61 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 62 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 63 #define USBOTGSS_TXFIFO_DEPTH 0x0508 64 #define USBOTGSS_RXFIFO_DEPTH 0x050c 65 #define USBOTGSS_MMRAM_OFFSET 0x0100 66 #define USBOTGSS_FLADJ 0x0104 67 #define USBOTGSS_DEBUG_CFG 0x0108 68 #define USBOTGSS_DEBUG_DATA 0x010c 69 #define USBOTGSS_DEV_EBC_EN 0x0110 70 #define USBOTGSS_DEBUG_OFFSET 0x0600 71 72 /* SYSCONFIG REGISTER */ 73 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 74 75 /* IRQ_EOI REGISTER */ 76 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 77 78 /* IRQS0 BITS */ 79 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 80 81 /* IRQMISC BITS */ 82 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 83 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 84 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 85 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 86 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 87 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 88 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 89 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 90 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 91 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 92 93 /* UTMI_OTG_CTRL REGISTER */ 94 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 95 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 96 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 97 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 98 99 /* UTMI_OTG_STATUS REGISTER */ 100 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 101 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 102 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 103 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 104 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 105 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 106 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 107 108 struct dwc3_omap { 109 struct device *dev; 110 111 void __iomem *base; 112 113 u32 utmi_otg_status; 114 u32 utmi_otg_offset; 115 u32 irqmisc_offset; 116 u32 irq_eoi_offset; 117 u32 debug_offset; 118 u32 irq0_offset; 119 120 u32 dma_status:1; 121 }; 122 123 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 124 { 125 return readl(base + offset); 126 } 127 128 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 129 { 130 writel(value, base + offset); 131 } 132 133 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap) 134 { 135 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS + 136 omap->utmi_otg_offset); 137 } 138 139 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value) 140 { 141 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS + 142 omap->utmi_otg_offset, value); 143 144 } 145 146 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 147 { 148 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 149 omap->irq0_offset); 150 } 151 152 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 153 { 154 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 155 omap->irq0_offset, value); 156 157 } 158 159 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 160 { 161 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 162 omap->irqmisc_offset); 163 } 164 165 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 166 { 167 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 168 omap->irqmisc_offset, value); 169 170 } 171 172 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 173 { 174 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 175 omap->irqmisc_offset, value); 176 177 } 178 179 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 180 { 181 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 182 omap->irq0_offset, value); 183 } 184 185 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 186 enum omap_dwc3_vbus_id_status status) 187 { 188 u32 val; 189 190 switch (status) { 191 case OMAP_DWC3_ID_GROUND: 192 dev_dbg(omap->dev, "ID GND\n"); 193 194 val = dwc3_omap_read_utmi_status(omap); 195 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG 196 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 197 | USBOTGSS_UTMI_OTG_STATUS_SESSEND); 198 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID 199 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 200 dwc3_omap_write_utmi_status(omap, val); 201 break; 202 203 case OMAP_DWC3_VBUS_VALID: 204 dev_dbg(omap->dev, "VBUS Connect\n"); 205 206 val = dwc3_omap_read_utmi_status(omap); 207 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; 208 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG 209 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 210 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID 211 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 212 dwc3_omap_write_utmi_status(omap, val); 213 break; 214 215 case OMAP_DWC3_ID_FLOAT: 216 case OMAP_DWC3_VBUS_OFF: 217 dev_dbg(omap->dev, "VBUS Disconnect\n"); 218 219 val = dwc3_omap_read_utmi_status(omap); 220 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID 221 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 222 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); 223 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND 224 | USBOTGSS_UTMI_OTG_STATUS_IDDIG; 225 dwc3_omap_write_utmi_status(omap, val); 226 break; 227 228 default: 229 dev_dbg(omap->dev, "invalid state\n"); 230 } 231 } 232 233 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 234 { 235 struct dwc3_omap *omap = _omap; 236 u32 reg; 237 238 reg = dwc3_omap_read_irqmisc_status(omap); 239 240 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) { 241 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 242 omap->dma_status = false; 243 } 244 245 if (reg & USBOTGSS_IRQMISC_OEVT) 246 dev_dbg(omap->dev, "OTG Event\n"); 247 248 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE) 249 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 250 251 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE) 252 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 253 254 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE) 255 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 256 257 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE) 258 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 259 260 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL) 261 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 262 263 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL) 264 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 265 266 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL) 267 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 268 269 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL) 270 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 271 272 dwc3_omap_write_irqmisc_status(omap, reg); 273 274 reg = dwc3_omap_read_irq0_status(omap); 275 276 dwc3_omap_write_irq0_status(omap, reg); 277 278 return IRQ_HANDLED; 279 } 280 281 static int dwc3_omap_remove_core(struct device *dev, void *c) 282 { 283 struct platform_device *pdev = to_platform_device(dev); 284 285 of_device_unregister(pdev); 286 287 return 0; 288 } 289 290 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 291 { 292 u32 reg; 293 294 /* enable all IRQs */ 295 reg = USBOTGSS_IRQO_COREIRQ_ST; 296 dwc3_omap_write_irq0_set(omap, reg); 297 298 reg = (USBOTGSS_IRQMISC_OEVT | 299 USBOTGSS_IRQMISC_DRVVBUS_RISE | 300 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 301 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 302 USBOTGSS_IRQMISC_IDPULLUP_RISE | 303 USBOTGSS_IRQMISC_DRVVBUS_FALL | 304 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 305 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 306 USBOTGSS_IRQMISC_IDPULLUP_FALL); 307 308 dwc3_omap_write_irqmisc_set(omap, reg); 309 } 310 311 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 312 { 313 /* disable all IRQs */ 314 dwc3_omap_write_irqmisc_set(omap, 0x00); 315 dwc3_omap_write_irq0_set(omap, 0x00); 316 } 317 318 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32); 319 320 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 321 { 322 struct device_node *node = omap->dev->of_node; 323 324 /* 325 * Differentiate between OMAP5 and AM437x. 326 * 327 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 328 * though there are changes in wrapper register offsets. 329 * 330 * Using dt compatible to differentiate AM437x. 331 */ 332 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 333 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 334 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 335 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 336 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 337 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 338 } 339 } 340 341 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 342 { 343 u32 reg; 344 struct device_node *node = omap->dev->of_node; 345 int utmi_mode = 0; 346 347 reg = dwc3_omap_read_utmi_status(omap); 348 349 of_property_read_u32(node, "utmi-mode", &utmi_mode); 350 351 switch (utmi_mode) { 352 case DWC3_OMAP_UTMI_MODE_SW: 353 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 354 break; 355 case DWC3_OMAP_UTMI_MODE_HW: 356 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 357 break; 358 default: 359 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 360 } 361 362 dwc3_omap_write_utmi_status(omap, reg); 363 } 364 365 static int dwc3_omap_probe(struct platform_device *pdev) 366 { 367 struct device_node *node = pdev->dev.of_node; 368 369 struct dwc3_omap *omap; 370 struct resource *res; 371 struct device *dev = &pdev->dev; 372 373 int ret; 374 u32 reg; 375 376 void __iomem *base; 377 378 if (!node) { 379 dev_err(dev, "device node not found\n"); 380 return -EINVAL; 381 } 382 383 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 384 if (!omap) 385 return -ENOMEM; 386 387 platform_set_drvdata(pdev, omap); 388 389 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 390 base = devm_ioremap_resource(dev, res); 391 if (IS_ERR(base)) 392 return PTR_ERR(base); 393 394 omap->dev = dev; 395 omap->base = base; 396 dev->dma_mask = &dwc3_omap_dma_mask; 397 398 dwc3_omap_map_offset(omap); 399 dwc3_omap_set_utmi_mode(omap); 400 401 /* check the DMA Status */ 402 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 403 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 404 405 dwc3_omap_enable_irqs(omap); 406 407 ret = of_platform_populate(node, NULL, NULL, dev); 408 if (ret) { 409 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 410 goto err1; 411 } 412 413 return 0; 414 415 err1: 416 dwc3_omap_disable_irqs(omap); 417 418 err0: 419 return ret; 420 } 421 422 static int dwc3_omap_remove(struct platform_device *pdev) 423 { 424 struct dwc3_omap *omap = platform_get_drvdata(pdev); 425 426 dwc3_omap_disable_irqs(omap); 427 device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core); 428 429 return 0; 430 } 431 432 static const struct of_device_id of_dwc3_match[] = { 433 { 434 .compatible = "ti,dwc3" 435 }, 436 { 437 .compatible = "ti,am437x-dwc3" 438 }, 439 { }, 440 }; 441 MODULE_DEVICE_TABLE(of, of_dwc3_match); 442 443 static struct platform_driver dwc3_omap_driver = { 444 .probe = dwc3_omap_probe, 445 .remove = dwc3_omap_remove, 446 .driver = { 447 .name = "omap-dwc3", 448 .of_match_table = of_dwc3_match, 449 }, 450 }; 451 452 module_platform_driver(dwc3_omap_driver); 453 454 MODULE_ALIAS("platform:omap-dwc3"); 455 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 456 MODULE_LICENSE("GPL v2"); 457 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 458